rockchip-dfi.c 6.5 KB

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  1. /*
  2. * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
  3. * Author: Lin Huang <hl@rock-chips.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/devfreq-event.h>
  16. #include <linux/kernel.h>
  17. #include <linux/err.h>
  18. #include <linux/init.h>
  19. #include <linux/io.h>
  20. #include <linux/mfd/syscon.h>
  21. #include <linux/module.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/regmap.h>
  24. #include <linux/slab.h>
  25. #include <linux/list.h>
  26. #include <linux/of.h>
  27. #define RK3399_DMC_NUM_CH 2
  28. /* DDRMON_CTRL */
  29. #define DDRMON_CTRL 0x04
  30. #define CLR_DDRMON_CTRL (0x1f0000 << 0)
  31. #define LPDDR4_EN (0x10001 << 4)
  32. #define HARDWARE_EN (0x10001 << 3)
  33. #define LPDDR3_EN (0x10001 << 2)
  34. #define SOFTWARE_EN (0x10001 << 1)
  35. #define SOFTWARE_DIS (0x10000 << 1)
  36. #define TIME_CNT_EN (0x10001 << 0)
  37. #define DDRMON_CH0_COUNT_NUM 0x28
  38. #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
  39. #define DDRMON_CH1_COUNT_NUM 0x3c
  40. #define DDRMON_CH1_DFI_ACCESS_NUM 0x40
  41. /* pmu grf */
  42. #define PMUGRF_OS_REG2 0x308
  43. #define DDRTYPE_SHIFT 13
  44. #define DDRTYPE_MASK 7
  45. enum {
  46. DDR3 = 3,
  47. LPDDR3 = 6,
  48. LPDDR4 = 7,
  49. UNUSED = 0xFF
  50. };
  51. struct dmc_usage {
  52. u32 access;
  53. u32 total;
  54. };
  55. /*
  56. * The dfi controller can monitor DDR load. It has an upper and lower threshold
  57. * for the operating points. Whenever the usage leaves these bounds an event is
  58. * generated to indicate the DDR frequency should be changed.
  59. */
  60. struct rockchip_dfi {
  61. struct devfreq_event_dev *edev;
  62. struct devfreq_event_desc *desc;
  63. struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
  64. struct device *dev;
  65. void __iomem *regs;
  66. struct regmap *regmap_pmu;
  67. struct clk *clk;
  68. };
  69. static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
  70. {
  71. struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
  72. void __iomem *dfi_regs = info->regs;
  73. u32 val;
  74. u32 ddr_type;
  75. /* get ddr type */
  76. regmap_read(info->regmap_pmu, PMUGRF_OS_REG2, &val);
  77. ddr_type = (val >> DDRTYPE_SHIFT) & DDRTYPE_MASK;
  78. /* clear DDRMON_CTRL setting */
  79. writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
  80. /* set ddr type to dfi */
  81. if (ddr_type == LPDDR3)
  82. writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
  83. else if (ddr_type == LPDDR4)
  84. writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
  85. /* enable count, use software mode */
  86. writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
  87. }
  88. static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
  89. {
  90. struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
  91. void __iomem *dfi_regs = info->regs;
  92. writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
  93. }
  94. static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
  95. {
  96. struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
  97. u32 tmp, max = 0;
  98. u32 i, busier_ch = 0;
  99. void __iomem *dfi_regs = info->regs;
  100. rockchip_dfi_stop_hardware_counter(edev);
  101. /* Find out which channel is busier */
  102. for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
  103. info->ch_usage[i].access = readl_relaxed(dfi_regs +
  104. DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
  105. info->ch_usage[i].total = readl_relaxed(dfi_regs +
  106. DDRMON_CH0_COUNT_NUM + i * 20);
  107. tmp = info->ch_usage[i].access;
  108. if (tmp > max) {
  109. busier_ch = i;
  110. max = tmp;
  111. }
  112. }
  113. rockchip_dfi_start_hardware_counter(edev);
  114. return busier_ch;
  115. }
  116. static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
  117. {
  118. struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
  119. rockchip_dfi_stop_hardware_counter(edev);
  120. clk_disable_unprepare(info->clk);
  121. return 0;
  122. }
  123. static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
  124. {
  125. struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
  126. int ret;
  127. ret = clk_prepare_enable(info->clk);
  128. if (ret) {
  129. dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
  130. return ret;
  131. }
  132. rockchip_dfi_start_hardware_counter(edev);
  133. return 0;
  134. }
  135. static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
  136. {
  137. return 0;
  138. }
  139. static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
  140. struct devfreq_event_data *edata)
  141. {
  142. struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
  143. int busier_ch;
  144. busier_ch = rockchip_dfi_get_busier_ch(edev);
  145. edata->load_count = info->ch_usage[busier_ch].access;
  146. edata->total_count = info->ch_usage[busier_ch].total;
  147. return 0;
  148. }
  149. static const struct devfreq_event_ops rockchip_dfi_ops = {
  150. .disable = rockchip_dfi_disable,
  151. .enable = rockchip_dfi_enable,
  152. .get_event = rockchip_dfi_get_event,
  153. .set_event = rockchip_dfi_set_event,
  154. };
  155. static const struct of_device_id rockchip_dfi_id_match[] = {
  156. { .compatible = "rockchip,rk3399-dfi" },
  157. { },
  158. };
  159. static int rockchip_dfi_probe(struct platform_device *pdev)
  160. {
  161. struct device *dev = &pdev->dev;
  162. struct rockchip_dfi *data;
  163. struct resource *res;
  164. struct devfreq_event_desc *desc;
  165. struct device_node *np = pdev->dev.of_node, *node;
  166. data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
  167. if (!data)
  168. return -ENOMEM;
  169. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  170. data->regs = devm_ioremap_resource(&pdev->dev, res);
  171. if (IS_ERR(data->regs))
  172. return PTR_ERR(data->regs);
  173. data->clk = devm_clk_get(dev, "pclk_ddr_mon");
  174. if (IS_ERR(data->clk)) {
  175. dev_err(dev, "Cannot get the clk dmc_clk\n");
  176. return PTR_ERR(data->clk);
  177. };
  178. /* try to find the optional reference to the pmu syscon */
  179. node = of_parse_phandle(np, "rockchip,pmu", 0);
  180. if (node) {
  181. data->regmap_pmu = syscon_node_to_regmap(node);
  182. if (IS_ERR(data->regmap_pmu))
  183. return PTR_ERR(data->regmap_pmu);
  184. }
  185. data->dev = dev;
  186. desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
  187. if (!desc)
  188. return -ENOMEM;
  189. desc->ops = &rockchip_dfi_ops;
  190. desc->driver_data = data;
  191. desc->name = np->name;
  192. data->desc = desc;
  193. data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
  194. if (IS_ERR(data->edev)) {
  195. dev_err(&pdev->dev,
  196. "failed to add devfreq-event device\n");
  197. return PTR_ERR(data->edev);
  198. }
  199. platform_set_drvdata(pdev, data);
  200. return 0;
  201. }
  202. static struct platform_driver rockchip_dfi_driver = {
  203. .probe = rockchip_dfi_probe,
  204. .driver = {
  205. .name = "rockchip-dfi",
  206. .of_match_table = rockchip_dfi_id_match,
  207. },
  208. };
  209. module_platform_driver(rockchip_dfi_driver);
  210. MODULE_LICENSE("GPL v2");
  211. MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
  212. MODULE_DESCRIPTION("Rockchip DFI driver");