tpm_tis_core.h 4.3 KB

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  1. /*
  2. * Copyright (C) 2005, 2006 IBM Corporation
  3. * Copyright (C) 2014, 2015 Intel Corporation
  4. *
  5. * Authors:
  6. * Leendert van Doorn <leendert@watson.ibm.com>
  7. * Kylene Hall <kjhall@us.ibm.com>
  8. *
  9. * Maintained by: <tpmdd-devel@lists.sourceforge.net>
  10. *
  11. * Device driver for TCG/TCPA TPM (trusted platform module).
  12. * Specifications at www.trustedcomputinggroup.org
  13. *
  14. * This device driver implements the TPM interface as defined in
  15. * the TCG TPM Interface Spec version 1.2, revision 1.0.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation, version 2 of the
  20. * License.
  21. */
  22. #ifndef __TPM_TIS_CORE_H__
  23. #define __TPM_TIS_CORE_H__
  24. #include "tpm.h"
  25. enum tis_access {
  26. TPM_ACCESS_VALID = 0x80,
  27. TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
  28. TPM_ACCESS_REQUEST_PENDING = 0x04,
  29. TPM_ACCESS_REQUEST_USE = 0x02,
  30. };
  31. enum tis_status {
  32. TPM_STS_VALID = 0x80,
  33. TPM_STS_COMMAND_READY = 0x40,
  34. TPM_STS_GO = 0x20,
  35. TPM_STS_DATA_AVAIL = 0x10,
  36. TPM_STS_DATA_EXPECT = 0x08,
  37. };
  38. enum tis_int_flags {
  39. TPM_GLOBAL_INT_ENABLE = 0x80000000,
  40. TPM_INTF_BURST_COUNT_STATIC = 0x100,
  41. TPM_INTF_CMD_READY_INT = 0x080,
  42. TPM_INTF_INT_EDGE_FALLING = 0x040,
  43. TPM_INTF_INT_EDGE_RISING = 0x020,
  44. TPM_INTF_INT_LEVEL_LOW = 0x010,
  45. TPM_INTF_INT_LEVEL_HIGH = 0x008,
  46. TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
  47. TPM_INTF_STS_VALID_INT = 0x002,
  48. TPM_INTF_DATA_AVAIL_INT = 0x001,
  49. };
  50. enum tis_defaults {
  51. TIS_MEM_LEN = 0x5000,
  52. TIS_SHORT_TIMEOUT = 750, /* ms */
  53. TIS_LONG_TIMEOUT = 2000, /* 2 sec */
  54. };
  55. /* Some timeout values are needed before it is known whether the chip is
  56. * TPM 1.0 or TPM 2.0.
  57. */
  58. #define TIS_TIMEOUT_A_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A)
  59. #define TIS_TIMEOUT_B_MAX max(TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B)
  60. #define TIS_TIMEOUT_C_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C)
  61. #define TIS_TIMEOUT_D_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D)
  62. #define TPM_ACCESS(l) (0x0000 | ((l) << 12))
  63. #define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
  64. #define TPM_INT_VECTOR(l) (0x000C | ((l) << 12))
  65. #define TPM_INT_STATUS(l) (0x0010 | ((l) << 12))
  66. #define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12))
  67. #define TPM_STS(l) (0x0018 | ((l) << 12))
  68. #define TPM_STS3(l) (0x001b | ((l) << 12))
  69. #define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
  70. #define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
  71. #define TPM_RID(l) (0x0F04 | ((l) << 12))
  72. enum tpm_tis_flags {
  73. TPM_TIS_ITPM_POSSIBLE = BIT(0),
  74. };
  75. struct tpm_tis_data {
  76. u16 manufacturer_id;
  77. int locality;
  78. int irq;
  79. bool irq_tested;
  80. unsigned int flags;
  81. wait_queue_head_t int_queue;
  82. wait_queue_head_t read_queue;
  83. const struct tpm_tis_phy_ops *phy_ops;
  84. };
  85. struct tpm_tis_phy_ops {
  86. int (*read_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
  87. u8 *result);
  88. int (*write_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
  89. const u8 *value);
  90. int (*read16)(struct tpm_tis_data *data, u32 addr, u16 *result);
  91. int (*read32)(struct tpm_tis_data *data, u32 addr, u32 *result);
  92. int (*write32)(struct tpm_tis_data *data, u32 addr, u32 src);
  93. };
  94. static inline int tpm_tis_read_bytes(struct tpm_tis_data *data, u32 addr,
  95. u16 len, u8 *result)
  96. {
  97. return data->phy_ops->read_bytes(data, addr, len, result);
  98. }
  99. static inline int tpm_tis_read8(struct tpm_tis_data *data, u32 addr, u8 *result)
  100. {
  101. return data->phy_ops->read_bytes(data, addr, 1, result);
  102. }
  103. static inline int tpm_tis_read16(struct tpm_tis_data *data, u32 addr,
  104. u16 *result)
  105. {
  106. return data->phy_ops->read16(data, addr, result);
  107. }
  108. static inline int tpm_tis_read32(struct tpm_tis_data *data, u32 addr,
  109. u32 *result)
  110. {
  111. return data->phy_ops->read32(data, addr, result);
  112. }
  113. static inline int tpm_tis_write_bytes(struct tpm_tis_data *data, u32 addr,
  114. u16 len, const u8 *value)
  115. {
  116. return data->phy_ops->write_bytes(data, addr, len, value);
  117. }
  118. static inline int tpm_tis_write8(struct tpm_tis_data *data, u32 addr, u8 value)
  119. {
  120. return data->phy_ops->write_bytes(data, addr, 1, &value);
  121. }
  122. static inline int tpm_tis_write32(struct tpm_tis_data *data, u32 addr,
  123. u32 value)
  124. {
  125. return data->phy_ops->write32(data, addr, value);
  126. }
  127. void tpm_tis_remove(struct tpm_chip *chip);
  128. int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
  129. const struct tpm_tis_phy_ops *phy_ops,
  130. acpi_handle acpi_dev_handle);
  131. #ifdef CONFIG_PM_SLEEP
  132. int tpm_tis_resume(struct device *dev);
  133. #endif
  134. #endif