amd-rng.c 4.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212
  1. /*
  2. * RNG driver for AMD RNGs
  3. *
  4. * Copyright 2005 (c) MontaVista Software, Inc.
  5. *
  6. * with the majority of the code coming from:
  7. *
  8. * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
  9. * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
  10. *
  11. * derived from
  12. *
  13. * Hardware driver for the AMD 768 Random Number Generator (RNG)
  14. * (c) Copyright 2001 Red Hat Inc
  15. *
  16. * derived from
  17. *
  18. * Hardware driver for Intel i810 Random Number Generator (RNG)
  19. * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
  20. * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
  21. *
  22. * This file is licensed under the terms of the GNU General Public
  23. * License version 2. This program is licensed "as is" without any
  24. * warranty of any kind, whether express or implied.
  25. */
  26. #include <linux/delay.h>
  27. #include <linux/hw_random.h>
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/pci.h>
  31. #define DRV_NAME "AMD768-HWRNG"
  32. #define RNGDATA 0x00
  33. #define RNGDONE 0x04
  34. #define PMBASE_OFFSET 0xF0
  35. #define PMBASE_SIZE 8
  36. /*
  37. * Data for PCI driver interface
  38. *
  39. * This data only exists for exporting the supported
  40. * PCI ids via MODULE_DEVICE_TABLE. We do not actually
  41. * register a pci_driver, because someone else might one day
  42. * want to register another driver on the same PCI id.
  43. */
  44. static const struct pci_device_id pci_tbl[] = {
  45. { PCI_VDEVICE(AMD, 0x7443), 0, },
  46. { PCI_VDEVICE(AMD, 0x746b), 0, },
  47. { 0, }, /* terminate list */
  48. };
  49. MODULE_DEVICE_TABLE(pci, pci_tbl);
  50. struct amd768_priv {
  51. void __iomem *iobase;
  52. struct pci_dev *pcidev;
  53. u32 pmbase;
  54. };
  55. static int amd_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
  56. {
  57. u32 *data = buf;
  58. struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
  59. size_t read = 0;
  60. /* We will wait at maximum one time per read */
  61. int timeout = max / 4 + 1;
  62. /*
  63. * RNG data is available when RNGDONE is set to 1
  64. * New random numbers are generated approximately 128 microseconds
  65. * after RNGDATA is read
  66. */
  67. while (read < max) {
  68. if (ioread32(priv->iobase + RNGDONE) == 0) {
  69. if (wait) {
  70. /* Delay given by datasheet */
  71. usleep_range(128, 196);
  72. if (timeout-- == 0)
  73. return read;
  74. } else {
  75. return 0;
  76. }
  77. } else {
  78. *data = ioread32(priv->iobase + RNGDATA);
  79. data++;
  80. read += 4;
  81. }
  82. }
  83. return read;
  84. }
  85. static int amd_rng_init(struct hwrng *rng)
  86. {
  87. struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
  88. u8 rnen;
  89. pci_read_config_byte(priv->pcidev, 0x40, &rnen);
  90. rnen |= BIT(7); /* RNG on */
  91. pci_write_config_byte(priv->pcidev, 0x40, rnen);
  92. pci_read_config_byte(priv->pcidev, 0x41, &rnen);
  93. rnen |= BIT(7); /* PMIO enable */
  94. pci_write_config_byte(priv->pcidev, 0x41, rnen);
  95. return 0;
  96. }
  97. static void amd_rng_cleanup(struct hwrng *rng)
  98. {
  99. struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
  100. u8 rnen;
  101. pci_read_config_byte(priv->pcidev, 0x40, &rnen);
  102. rnen &= ~BIT(7); /* RNG off */
  103. pci_write_config_byte(priv->pcidev, 0x40, rnen);
  104. }
  105. static struct hwrng amd_rng = {
  106. .name = "amd",
  107. .init = amd_rng_init,
  108. .cleanup = amd_rng_cleanup,
  109. .read = amd_rng_read,
  110. };
  111. static int __init mod_init(void)
  112. {
  113. int err = -ENODEV;
  114. struct pci_dev *pdev = NULL;
  115. const struct pci_device_id *ent;
  116. u32 pmbase;
  117. struct amd768_priv *priv;
  118. for_each_pci_dev(pdev) {
  119. ent = pci_match_id(pci_tbl, pdev);
  120. if (ent)
  121. goto found;
  122. }
  123. /* Device not found. */
  124. return -ENODEV;
  125. found:
  126. err = pci_read_config_dword(pdev, 0x58, &pmbase);
  127. if (err)
  128. return err;
  129. pmbase &= 0x0000FF00;
  130. if (pmbase == 0)
  131. return -EIO;
  132. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  133. if (!priv)
  134. return -ENOMEM;
  135. if (!request_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE, DRV_NAME)) {
  136. dev_err(&pdev->dev, DRV_NAME " region 0x%x already in use!\n",
  137. pmbase + 0xF0);
  138. err = -EBUSY;
  139. goto out;
  140. }
  141. priv->iobase = ioport_map(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
  142. if (!priv->iobase) {
  143. pr_err(DRV_NAME "Cannot map ioport\n");
  144. err = -EINVAL;
  145. goto err_iomap;
  146. }
  147. amd_rng.priv = (unsigned long)priv;
  148. priv->pmbase = pmbase;
  149. priv->pcidev = pdev;
  150. pr_info(DRV_NAME " detected\n");
  151. err = hwrng_register(&amd_rng);
  152. if (err) {
  153. pr_err(DRV_NAME " registering failed (%d)\n", err);
  154. goto err_hwrng;
  155. }
  156. return 0;
  157. err_hwrng:
  158. ioport_unmap(priv->iobase);
  159. err_iomap:
  160. release_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
  161. out:
  162. kfree(priv);
  163. return err;
  164. }
  165. static void __exit mod_exit(void)
  166. {
  167. struct amd768_priv *priv;
  168. priv = (struct amd768_priv *)amd_rng.priv;
  169. hwrng_unregister(&amd_rng);
  170. ioport_unmap(priv->iobase);
  171. release_region(priv->pmbase + PMBASE_OFFSET, PMBASE_SIZE);
  172. kfree(priv);
  173. }
  174. module_init(mod_init);
  175. module_exit(mod_exit);
  176. MODULE_AUTHOR("The Linux Kernel team");
  177. MODULE_DESCRIPTION("H/W RNG driver for AMD chipsets");
  178. MODULE_LICENSE("GPL");