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subcore-asm.S

subcore-asm.S 2.0 KB
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  1. /*
    2. 

  2.  * Copyright 2013, Michael (Ellerman|Neuling), IBM Corporation.
    3. 

  3.  *
    4. 

  4.  * This program is free software; you can redistribute it and/or
    5. 

  5.  * modify it under the terms of the GNU General Public License
    6. 

  6.  * as published by the Free Software Foundation; either version
    7. 

  7.  * 2 of the License, or (at your option) any later version.
    8. 

  8.  */
    9. 

  9. 

  10. #include <asm/asm-offsets.h>
    11. 

  11. #include <asm/ppc_asm.h>
    12. 

  12. #include <asm/reg.h>
    13. 

  13. 

  14. #include "subcore.h"
    15. 

  15. 

  16. 

  17. _GLOBAL(split_core_secondary_loop)
    18. 

  18. 	/*
    19. 

  19. 	 * r3 = u8 *state, used throughout the routine
    20. 

  20. 	 * r4 = temp
    21. 

  21. 	 * r5 = temp
    22. 

  22. 	 * ..
    23. 

  23. 	 * r12 = MSR
    24. 

  24. 	 */
    25. 

  25. 	mfmsr	r12
    26. 

  26. 

  27. 	/* Disable interrupts so SRR0/1 don't get trashed */
    28. 

  28. 	li	r4,0
    29. 

  29. 	ori	r4,r4,MSR_EE|MSR_SE|MSR_BE|MSR_RI
    30. 

  30. 	andc	r4,r12,r4
    31. 

  31. 	sync
    32. 

  32. 	mtmsrd	r4
    33. 

  33. 

  34. 	/* Switch to real mode and leave interrupts off */
    35. 

  35. 	li	r5, MSR_IR|MSR_DR
    36. 

  36. 	andc	r5, r4, r5
    37. 

  37. 

  38. 	LOAD_REG_ADDR(r4, real_mode)
    39. 

  39. 

  40. 	mtspr	SPRN_SRR0,r4
    41. 

  41. 	mtspr	SPRN_SRR1,r5
    42. 

  42. 	rfid
    43. 

  43. 	b	.	/* prevent speculative execution */
    44. 

  44. 

  45. real_mode:
    46. 

  46. 	/* Grab values from unsplit SPRs */
    47. 

  47. 	mfspr	r6,  SPRN_LDBAR
    48. 

  48. 	mfspr	r7,  SPRN_PMMAR
    49. 

  49. 	mfspr	r8,  SPRN_PMCR
    50. 

  50. 	mfspr	r9,  SPRN_RPR
    51. 

  51. 	mfspr	r10, SPRN_SDR1
    52. 

  52. 

  53. 	/* Order reading the SPRs vs telling the primary we are ready to split */
    54. 

  54. 	sync
    55. 

  55. 

  56. 	/* Tell thread 0 we are in real mode */
    57. 

  57. 	li	r4, SYNC_STEP_REAL_MODE
    58. 

  58. 	stb	r4, 0(r3)
    59. 

  59. 

  60. 	li	r5, (HID0_POWER8_4LPARMODE | HID0_POWER8_2LPARMODE)@highest
    61. 

  61. 	sldi	r5, r5, 48
    62. 

  62. 

  63. 	/* Loop until we see the split happen in HID0 */
    64. 

  64. 1:	mfspr	r4, SPRN_HID0
    65. 

  65. 	and.	r4, r4, r5
    66. 

  66. 	beq	1b
    67. 

  67. 

  68. 	/*
    69. 

  69. 	 * We only need to initialise the below regs once for each subcore,
    70. 

  70. 	 * but it's simpler and harmless to do it on each thread.
    71. 

  71. 	 */
    72. 

  72. 

  73. 	/* Make sure various SPRS have sane values */
    74. 

  74. 	li	r4, 0
    75. 

  75. 	mtspr	SPRN_LPID, r4
    76. 

  76. 	mtspr	SPRN_PCR, r4
    77. 

  77. 	mtspr	SPRN_HDEC, r4
    78. 

  78. 

  79. 	/* Restore SPR values now we are split */
    80. 

  80. 	mtspr	SPRN_LDBAR, r6
    81. 

  81. 	mtspr	SPRN_PMMAR, r7
    82. 

  82. 	mtspr	SPRN_PMCR, r8
    83. 

  83. 	mtspr	SPRN_RPR, r9
    84. 

  84. 	mtspr	SPRN_SDR1, r10
    85. 

  85. 

  86. 	LOAD_REG_ADDR(r5, virtual_mode)
    87. 

  87. 

  88. 	/* Get out of real mode */
    89. 

  89. 	mtspr	SPRN_SRR0,r5
    90. 

  90. 	mtspr	SPRN_SRR1,r12
    91. 

  91. 	rfid
    92. 

  92. 	b	.	/* prevent speculative execution */
    93. 

  93. 

  94. virtual_mode:
    95. 

  95. 	blr
    96. 

  96.