setup.c 22 KB

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  1. /*
  2. * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
  3. * and RBTX49xx patch from CELF patch archive.
  4. *
  5. * 2003-2005 (c) MontaVista Software, Inc.
  6. * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/string.h>
  17. #include <linux/module.h>
  18. #include <linux/clk-provider.h>
  19. #include <linux/clkdev.h>
  20. #include <linux/err.h>
  21. #include <linux/gpio/driver.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/serial_core.h>
  24. #include <linux/mtd/physmap.h>
  25. #include <linux/leds.h>
  26. #include <linux/device.h>
  27. #include <linux/slab.h>
  28. #include <linux/irq.h>
  29. #include <asm/bootinfo.h>
  30. #include <asm/idle.h>
  31. #include <asm/time.h>
  32. #include <asm/reboot.h>
  33. #include <asm/r4kcache.h>
  34. #include <asm/sections.h>
  35. #include <asm/txx9/generic.h>
  36. #include <asm/txx9/pci.h>
  37. #include <asm/txx9tmr.h>
  38. #include <asm/txx9/ndfmc.h>
  39. #include <asm/txx9/dmac.h>
  40. #ifdef CONFIG_CPU_TX49XX
  41. #include <asm/txx9/tx4938.h>
  42. #endif
  43. /* EBUSC settings of TX4927, etc. */
  44. struct resource txx9_ce_res[8];
  45. static char txx9_ce_res_name[8][4]; /* "CEn" */
  46. /* pcode, internal register */
  47. unsigned int txx9_pcode;
  48. char txx9_pcode_str[8];
  49. static struct resource txx9_reg_res = {
  50. .name = txx9_pcode_str,
  51. .flags = IORESOURCE_MEM,
  52. };
  53. void __init
  54. txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size)
  55. {
  56. int i;
  57. for (i = 0; i < ARRAY_SIZE(txx9_ce_res); i++) {
  58. sprintf(txx9_ce_res_name[i], "CE%d", i);
  59. txx9_ce_res[i].flags = IORESOURCE_MEM;
  60. txx9_ce_res[i].name = txx9_ce_res_name[i];
  61. }
  62. txx9_pcode = pcode;
  63. sprintf(txx9_pcode_str, "TX%x", pcode);
  64. if (base) {
  65. txx9_reg_res.start = base & 0xfffffffffULL;
  66. txx9_reg_res.end = (base & 0xfffffffffULL) + (size - 1);
  67. request_resource(&iomem_resource, &txx9_reg_res);
  68. }
  69. }
  70. /* clocks */
  71. unsigned int txx9_master_clock;
  72. unsigned int txx9_cpu_clock;
  73. unsigned int txx9_gbus_clock;
  74. #ifdef CONFIG_CPU_TX39XX
  75. /* don't enable by default - see errata */
  76. int txx9_ccfg_toeon __initdata;
  77. #else
  78. int txx9_ccfg_toeon __initdata = 1;
  79. #endif
  80. #define BOARD_VEC(board) extern struct txx9_board_vec board;
  81. #include <asm/txx9/boards.h>
  82. #undef BOARD_VEC
  83. struct txx9_board_vec *txx9_board_vec __initdata;
  84. static char txx9_system_type[32];
  85. static struct txx9_board_vec *board_vecs[] __initdata = {
  86. #define BOARD_VEC(board) &board,
  87. #include <asm/txx9/boards.h>
  88. #undef BOARD_VEC
  89. };
  90. static struct txx9_board_vec *__init find_board_byname(const char *name)
  91. {
  92. int i;
  93. /* search board_vecs table */
  94. for (i = 0; i < ARRAY_SIZE(board_vecs); i++) {
  95. if (strstr(board_vecs[i]->system, name))
  96. return board_vecs[i];
  97. }
  98. return NULL;
  99. }
  100. static void __init prom_init_cmdline(void)
  101. {
  102. int argc;
  103. int *argv32;
  104. int i; /* Always ignore the "-c" at argv[0] */
  105. if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) {
  106. /*
  107. * argc is not a valid number, or argv32 is not a valid
  108. * pointer
  109. */
  110. argc = 0;
  111. argv32 = NULL;
  112. } else {
  113. argc = (int)fw_arg0;
  114. argv32 = (int *)fw_arg1;
  115. }
  116. arcs_cmdline[0] = '\0';
  117. for (i = 1; i < argc; i++) {
  118. char *str = (char *)(long)argv32[i];
  119. if (i != 1)
  120. strcat(arcs_cmdline, " ");
  121. if (strchr(str, ' ')) {
  122. strcat(arcs_cmdline, "\"");
  123. strcat(arcs_cmdline, str);
  124. strcat(arcs_cmdline, "\"");
  125. } else
  126. strcat(arcs_cmdline, str);
  127. }
  128. }
  129. static int txx9_ic_disable __initdata;
  130. static int txx9_dc_disable __initdata;
  131. #if defined(CONFIG_CPU_TX49XX)
  132. /* flush all cache on very early stage (before 4k_cache_init) */
  133. static void __init early_flush_dcache(void)
  134. {
  135. unsigned int conf = read_c0_config();
  136. unsigned int dc_size = 1 << (12 + ((conf & CONF_DC) >> 6));
  137. unsigned int linesz = 32;
  138. unsigned long addr, end;
  139. end = INDEX_BASE + dc_size / 4;
  140. /* 4way, waybit=0 */
  141. for (addr = INDEX_BASE; addr < end; addr += linesz) {
  142. cache_op(Index_Writeback_Inv_D, addr | 0);
  143. cache_op(Index_Writeback_Inv_D, addr | 1);
  144. cache_op(Index_Writeback_Inv_D, addr | 2);
  145. cache_op(Index_Writeback_Inv_D, addr | 3);
  146. }
  147. }
  148. static void __init txx9_cache_fixup(void)
  149. {
  150. unsigned int conf;
  151. conf = read_c0_config();
  152. /* flush and disable */
  153. if (txx9_ic_disable) {
  154. conf |= TX49_CONF_IC;
  155. write_c0_config(conf);
  156. }
  157. if (txx9_dc_disable) {
  158. early_flush_dcache();
  159. conf |= TX49_CONF_DC;
  160. write_c0_config(conf);
  161. }
  162. /* enable cache */
  163. conf = read_c0_config();
  164. if (!txx9_ic_disable)
  165. conf &= ~TX49_CONF_IC;
  166. if (!txx9_dc_disable)
  167. conf &= ~TX49_CONF_DC;
  168. write_c0_config(conf);
  169. if (conf & TX49_CONF_IC)
  170. pr_info("TX49XX I-Cache disabled.\n");
  171. if (conf & TX49_CONF_DC)
  172. pr_info("TX49XX D-Cache disabled.\n");
  173. }
  174. #elif defined(CONFIG_CPU_TX39XX)
  175. /* flush all cache on very early stage (before tx39_cache_init) */
  176. static void __init early_flush_dcache(void)
  177. {
  178. unsigned int conf = read_c0_config();
  179. unsigned int dc_size = 1 << (10 + ((conf & TX39_CONF_DCS_MASK) >>
  180. TX39_CONF_DCS_SHIFT));
  181. unsigned int linesz = 16;
  182. unsigned long addr, end;
  183. end = INDEX_BASE + dc_size / 2;
  184. /* 2way, waybit=0 */
  185. for (addr = INDEX_BASE; addr < end; addr += linesz) {
  186. cache_op(Index_Writeback_Inv_D, addr | 0);
  187. cache_op(Index_Writeback_Inv_D, addr | 1);
  188. }
  189. }
  190. static void __init txx9_cache_fixup(void)
  191. {
  192. unsigned int conf;
  193. conf = read_c0_config();
  194. /* flush and disable */
  195. if (txx9_ic_disable) {
  196. conf &= ~TX39_CONF_ICE;
  197. write_c0_config(conf);
  198. }
  199. if (txx9_dc_disable) {
  200. early_flush_dcache();
  201. conf &= ~TX39_CONF_DCE;
  202. write_c0_config(conf);
  203. }
  204. /* enable cache */
  205. conf = read_c0_config();
  206. if (!txx9_ic_disable)
  207. conf |= TX39_CONF_ICE;
  208. if (!txx9_dc_disable)
  209. conf |= TX39_CONF_DCE;
  210. write_c0_config(conf);
  211. if (!(conf & TX39_CONF_ICE))
  212. pr_info("TX39XX I-Cache disabled.\n");
  213. if (!(conf & TX39_CONF_DCE))
  214. pr_info("TX39XX D-Cache disabled.\n");
  215. }
  216. #else
  217. static inline void txx9_cache_fixup(void)
  218. {
  219. }
  220. #endif
  221. static void __init preprocess_cmdline(void)
  222. {
  223. static char cmdline[COMMAND_LINE_SIZE] __initdata;
  224. char *s;
  225. strcpy(cmdline, arcs_cmdline);
  226. s = cmdline;
  227. arcs_cmdline[0] = '\0';
  228. while (s && *s) {
  229. char *str = strsep(&s, " ");
  230. if (strncmp(str, "board=", 6) == 0) {
  231. txx9_board_vec = find_board_byname(str + 6);
  232. continue;
  233. } else if (strncmp(str, "masterclk=", 10) == 0) {
  234. unsigned int val;
  235. if (kstrtouint(str + 10, 10, &val) == 0)
  236. txx9_master_clock = val;
  237. continue;
  238. } else if (strcmp(str, "icdisable") == 0) {
  239. txx9_ic_disable = 1;
  240. continue;
  241. } else if (strcmp(str, "dcdisable") == 0) {
  242. txx9_dc_disable = 1;
  243. continue;
  244. } else if (strcmp(str, "toeoff") == 0) {
  245. txx9_ccfg_toeon = 0;
  246. continue;
  247. } else if (strcmp(str, "toeon") == 0) {
  248. txx9_ccfg_toeon = 1;
  249. continue;
  250. }
  251. if (arcs_cmdline[0])
  252. strcat(arcs_cmdline, " ");
  253. strcat(arcs_cmdline, str);
  254. }
  255. txx9_cache_fixup();
  256. }
  257. static void __init select_board(void)
  258. {
  259. const char *envstr;
  260. /* first, determine by "board=" argument in preprocess_cmdline() */
  261. if (txx9_board_vec)
  262. return;
  263. /* next, determine by "board" envvar */
  264. envstr = prom_getenv("board");
  265. if (envstr) {
  266. txx9_board_vec = find_board_byname(envstr);
  267. if (txx9_board_vec)
  268. return;
  269. }
  270. /* select "default" board */
  271. #ifdef CONFIG_TOSHIBA_JMR3927
  272. txx9_board_vec = &jmr3927_vec;
  273. #endif
  274. #ifdef CONFIG_CPU_TX49XX
  275. switch (TX4938_REV_PCODE()) {
  276. #ifdef CONFIG_TOSHIBA_RBTX4927
  277. case 0x4927:
  278. txx9_board_vec = &rbtx4927_vec;
  279. break;
  280. case 0x4937:
  281. txx9_board_vec = &rbtx4937_vec;
  282. break;
  283. #endif
  284. #ifdef CONFIG_TOSHIBA_RBTX4938
  285. case 0x4938:
  286. txx9_board_vec = &rbtx4938_vec;
  287. break;
  288. #endif
  289. #ifdef CONFIG_TOSHIBA_RBTX4939
  290. case 0x4939:
  291. txx9_board_vec = &rbtx4939_vec;
  292. break;
  293. #endif
  294. }
  295. #endif
  296. }
  297. void __init prom_init(void)
  298. {
  299. prom_init_cmdline();
  300. preprocess_cmdline();
  301. select_board();
  302. strcpy(txx9_system_type, txx9_board_vec->system);
  303. txx9_board_vec->prom_init();
  304. }
  305. void __init prom_free_prom_memory(void)
  306. {
  307. unsigned long saddr = PAGE_SIZE;
  308. unsigned long eaddr = __pa_symbol(&_text);
  309. if (saddr < eaddr)
  310. free_init_pages("prom memory", saddr, eaddr);
  311. }
  312. const char *get_system_type(void)
  313. {
  314. return txx9_system_type;
  315. }
  316. const char *__init prom_getenv(const char *name)
  317. {
  318. const s32 *str;
  319. if (fw_arg2 < CKSEG0)
  320. return NULL;
  321. str = (const s32 *)fw_arg2;
  322. /* YAMON style ("name", "value" pairs) */
  323. while (str[0] && str[1]) {
  324. if (!strcmp((const char *)(unsigned long)str[0], name))
  325. return (const char *)(unsigned long)str[1];
  326. str += 2;
  327. }
  328. return NULL;
  329. }
  330. static void __noreturn txx9_machine_halt(void)
  331. {
  332. local_irq_disable();
  333. clear_c0_status(ST0_IM);
  334. while (1) {
  335. if (cpu_wait) {
  336. (*cpu_wait)();
  337. if (cpu_has_counter) {
  338. /*
  339. * Clear counter interrupt while it
  340. * breaks WAIT instruction even if
  341. * masked.
  342. */
  343. write_c0_compare(0);
  344. }
  345. }
  346. }
  347. }
  348. /* Watchdog support */
  349. void __init txx9_wdt_init(unsigned long base)
  350. {
  351. struct resource res = {
  352. .start = base,
  353. .end = base + 0x100 - 1,
  354. .flags = IORESOURCE_MEM,
  355. };
  356. platform_device_register_simple("txx9wdt", -1, &res, 1);
  357. }
  358. void txx9_wdt_now(unsigned long base)
  359. {
  360. struct txx9_tmr_reg __iomem *tmrptr =
  361. ioremap(base, sizeof(struct txx9_tmr_reg));
  362. /* disable watch dog timer */
  363. __raw_writel(TXx9_TMWTMR_WDIS | TXx9_TMWTMR_TWC, &tmrptr->wtmr);
  364. __raw_writel(0, &tmrptr->tcr);
  365. /* kick watchdog */
  366. __raw_writel(TXx9_TMWTMR_TWIE, &tmrptr->wtmr);
  367. __raw_writel(1, &tmrptr->cpra); /* immediate */
  368. __raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG,
  369. &tmrptr->tcr);
  370. }
  371. /* SPI support */
  372. void __init txx9_spi_init(int busid, unsigned long base, int irq)
  373. {
  374. struct resource res[] = {
  375. {
  376. .start = base,
  377. .end = base + 0x20 - 1,
  378. .flags = IORESOURCE_MEM,
  379. }, {
  380. .start = irq,
  381. .flags = IORESOURCE_IRQ,
  382. },
  383. };
  384. platform_device_register_simple("spi_txx9", busid,
  385. res, ARRAY_SIZE(res));
  386. }
  387. void __init txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr)
  388. {
  389. struct platform_device *pdev =
  390. platform_device_alloc("tc35815-mac", id);
  391. if (!pdev ||
  392. platform_device_add_data(pdev, ethaddr, 6) ||
  393. platform_device_add(pdev))
  394. platform_device_put(pdev);
  395. }
  396. void __init txx9_sio_init(unsigned long baseaddr, int irq,
  397. unsigned int line, unsigned int sclk, int nocts)
  398. {
  399. #ifdef CONFIG_SERIAL_TXX9
  400. struct uart_port req;
  401. memset(&req, 0, sizeof(req));
  402. req.line = line;
  403. req.iotype = UPIO_MEM;
  404. req.membase = ioremap(baseaddr, 0x24);
  405. req.mapbase = baseaddr;
  406. req.irq = irq;
  407. if (!nocts)
  408. req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
  409. if (sclk) {
  410. req.flags |= UPF_MAGIC_MULTIPLIER /*USE_SCLK*/;
  411. req.uartclk = sclk;
  412. } else
  413. req.uartclk = TXX9_IMCLK;
  414. early_serial_txx9_setup(&req);
  415. #endif /* CONFIG_SERIAL_TXX9 */
  416. }
  417. #ifdef CONFIG_EARLY_PRINTK
  418. static void null_prom_putchar(char c)
  419. {
  420. }
  421. void (*txx9_prom_putchar)(char c) = null_prom_putchar;
  422. void prom_putchar(char c)
  423. {
  424. txx9_prom_putchar(c);
  425. }
  426. static void __iomem *early_txx9_sio_port;
  427. static void early_txx9_sio_putchar(char c)
  428. {
  429. #define TXX9_SICISR 0x0c
  430. #define TXX9_SITFIFO 0x1c
  431. #define TXX9_SICISR_TXALS 0x00000002
  432. while (!(__raw_readl(early_txx9_sio_port + TXX9_SICISR) &
  433. TXX9_SICISR_TXALS))
  434. ;
  435. __raw_writel(c, early_txx9_sio_port + TXX9_SITFIFO);
  436. }
  437. void __init txx9_sio_putchar_init(unsigned long baseaddr)
  438. {
  439. early_txx9_sio_port = ioremap(baseaddr, 0x24);
  440. txx9_prom_putchar = early_txx9_sio_putchar;
  441. }
  442. #endif /* CONFIG_EARLY_PRINTK */
  443. /* wrappers */
  444. void __init plat_mem_setup(void)
  445. {
  446. ioport_resource.start = 0;
  447. ioport_resource.end = ~0UL; /* no limit */
  448. iomem_resource.start = 0;
  449. iomem_resource.end = ~0UL; /* no limit */
  450. /* fallback restart/halt routines */
  451. _machine_restart = (void (*)(char *))txx9_machine_halt;
  452. _machine_halt = txx9_machine_halt;
  453. pm_power_off = txx9_machine_halt;
  454. #ifdef CONFIG_PCI
  455. pcibios_plat_setup = txx9_pcibios_setup;
  456. #endif
  457. txx9_board_vec->mem_setup();
  458. }
  459. void __init arch_init_irq(void)
  460. {
  461. txx9_board_vec->irq_setup();
  462. }
  463. void __init plat_time_init(void)
  464. {
  465. #ifdef CONFIG_CPU_TX49XX
  466. mips_hpt_frequency = txx9_cpu_clock / 2;
  467. #endif
  468. txx9_board_vec->time_init();
  469. }
  470. static void txx9_clk_init(void)
  471. {
  472. struct clk_hw *hw;
  473. int error;
  474. hw = clk_hw_register_fixed_rate(NULL, "gbus", NULL, 0, txx9_gbus_clock);
  475. if (IS_ERR(hw)) {
  476. error = PTR_ERR(hw);
  477. goto fail;
  478. }
  479. hw = clk_hw_register_fixed_factor(NULL, "imbus", "gbus", 0, 1, 2);
  480. error = clk_hw_register_clkdev(hw, "imbus_clk", NULL);
  481. if (error)
  482. goto fail;
  483. #ifdef CONFIG_CPU_TX49XX
  484. if (TX4938_REV_PCODE() == 0x4938) {
  485. hw = clk_hw_register_fixed_factor(NULL, "spi", "gbus", 0, 1, 4);
  486. error = clk_hw_register_clkdev(hw, "spi-baseclk", NULL);
  487. if (error)
  488. goto fail;
  489. }
  490. #endif
  491. return;
  492. fail:
  493. pr_err("Failed to register clocks: %d\n", error);
  494. }
  495. static int __init _txx9_arch_init(void)
  496. {
  497. txx9_clk_init();
  498. if (txx9_board_vec->arch_init)
  499. txx9_board_vec->arch_init();
  500. return 0;
  501. }
  502. arch_initcall(_txx9_arch_init);
  503. static int __init _txx9_device_init(void)
  504. {
  505. if (txx9_board_vec->device_init)
  506. txx9_board_vec->device_init();
  507. return 0;
  508. }
  509. device_initcall(_txx9_device_init);
  510. int (*txx9_irq_dispatch)(int pending);
  511. asmlinkage void plat_irq_dispatch(void)
  512. {
  513. int pending = read_c0_status() & read_c0_cause() & ST0_IM;
  514. int irq = txx9_irq_dispatch(pending);
  515. if (likely(irq >= 0))
  516. do_IRQ(irq);
  517. else
  518. spurious_interrupt();
  519. }
  520. /* see include/asm-mips/mach-tx39xx/mangle-port.h, for example. */
  521. #ifdef NEEDS_TXX9_SWIZZLE_ADDR_B
  522. static unsigned long __swizzle_addr_none(unsigned long port)
  523. {
  524. return port;
  525. }
  526. unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none;
  527. EXPORT_SYMBOL(__swizzle_addr_b);
  528. #endif
  529. #ifdef NEEDS_TXX9_IOSWABW
  530. static u16 ioswabw_default(volatile u16 *a, u16 x)
  531. {
  532. return le16_to_cpu(x);
  533. }
  534. static u16 __mem_ioswabw_default(volatile u16 *a, u16 x)
  535. {
  536. return x;
  537. }
  538. u16 (*ioswabw)(volatile u16 *a, u16 x) = ioswabw_default;
  539. EXPORT_SYMBOL(ioswabw);
  540. u16 (*__mem_ioswabw)(volatile u16 *a, u16 x) = __mem_ioswabw_default;
  541. EXPORT_SYMBOL(__mem_ioswabw);
  542. #endif
  543. void __init txx9_physmap_flash_init(int no, unsigned long addr,
  544. unsigned long size,
  545. const struct physmap_flash_data *pdata)
  546. {
  547. #if IS_ENABLED(CONFIG_MTD_PHYSMAP)
  548. struct resource res = {
  549. .start = addr,
  550. .end = addr + size - 1,
  551. .flags = IORESOURCE_MEM,
  552. };
  553. struct platform_device *pdev;
  554. static struct mtd_partition parts[2];
  555. struct physmap_flash_data pdata_part;
  556. /* If this area contained boot area, make separate partition */
  557. if (pdata->nr_parts == 0 && !pdata->parts &&
  558. addr < 0x1fc00000 && addr + size > 0x1fc00000 &&
  559. !parts[0].name) {
  560. parts[0].name = "boot";
  561. parts[0].offset = 0x1fc00000 - addr;
  562. parts[0].size = addr + size - 0x1fc00000;
  563. parts[1].name = "user";
  564. parts[1].offset = 0;
  565. parts[1].size = 0x1fc00000 - addr;
  566. pdata_part = *pdata;
  567. pdata_part.nr_parts = ARRAY_SIZE(parts);
  568. pdata_part.parts = parts;
  569. pdata = &pdata_part;
  570. }
  571. pdev = platform_device_alloc("physmap-flash", no);
  572. if (!pdev ||
  573. platform_device_add_resources(pdev, &res, 1) ||
  574. platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
  575. platform_device_add(pdev))
  576. platform_device_put(pdev);
  577. #endif
  578. }
  579. void __init txx9_ndfmc_init(unsigned long baseaddr,
  580. const struct txx9ndfmc_platform_data *pdata)
  581. {
  582. #if IS_ENABLED(CONFIG_MTD_NAND_TXX9NDFMC)
  583. struct resource res = {
  584. .start = baseaddr,
  585. .end = baseaddr + 0x1000 - 1,
  586. .flags = IORESOURCE_MEM,
  587. };
  588. struct platform_device *pdev = platform_device_alloc("txx9ndfmc", -1);
  589. if (!pdev ||
  590. platform_device_add_resources(pdev, &res, 1) ||
  591. platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
  592. platform_device_add(pdev))
  593. platform_device_put(pdev);
  594. #endif
  595. }
  596. #if IS_ENABLED(CONFIG_LEDS_GPIO)
  597. static DEFINE_SPINLOCK(txx9_iocled_lock);
  598. #define TXX9_IOCLED_MAXLEDS 8
  599. struct txx9_iocled_data {
  600. struct gpio_chip chip;
  601. u8 cur_val;
  602. void __iomem *mmioaddr;
  603. struct gpio_led_platform_data pdata;
  604. struct gpio_led leds[TXX9_IOCLED_MAXLEDS];
  605. char names[TXX9_IOCLED_MAXLEDS][32];
  606. };
  607. static int txx9_iocled_get(struct gpio_chip *chip, unsigned int offset)
  608. {
  609. struct txx9_iocled_data *data = gpiochip_get_data(chip);
  610. return !!(data->cur_val & (1 << offset));
  611. }
  612. static void txx9_iocled_set(struct gpio_chip *chip, unsigned int offset,
  613. int value)
  614. {
  615. struct txx9_iocled_data *data = gpiochip_get_data(chip);
  616. unsigned long flags;
  617. spin_lock_irqsave(&txx9_iocled_lock, flags);
  618. if (value)
  619. data->cur_val |= 1 << offset;
  620. else
  621. data->cur_val &= ~(1 << offset);
  622. writeb(data->cur_val, data->mmioaddr);
  623. mmiowb();
  624. spin_unlock_irqrestore(&txx9_iocled_lock, flags);
  625. }
  626. static int txx9_iocled_dir_in(struct gpio_chip *chip, unsigned int offset)
  627. {
  628. return 0;
  629. }
  630. static int txx9_iocled_dir_out(struct gpio_chip *chip, unsigned int offset,
  631. int value)
  632. {
  633. txx9_iocled_set(chip, offset, value);
  634. return 0;
  635. }
  636. void __init txx9_iocled_init(unsigned long baseaddr,
  637. int basenum, unsigned int num, int lowactive,
  638. const char *color, char **deftriggers)
  639. {
  640. struct txx9_iocled_data *iocled;
  641. struct platform_device *pdev;
  642. int i;
  643. static char *default_triggers[] __initdata = {
  644. "heartbeat",
  645. "disk-activity",
  646. "nand-disk",
  647. NULL,
  648. };
  649. if (!deftriggers)
  650. deftriggers = default_triggers;
  651. iocled = kzalloc(sizeof(*iocled), GFP_KERNEL);
  652. if (!iocled)
  653. return;
  654. iocled->mmioaddr = ioremap(baseaddr, 1);
  655. if (!iocled->mmioaddr)
  656. goto out_free;
  657. iocled->chip.get = txx9_iocled_get;
  658. iocled->chip.set = txx9_iocled_set;
  659. iocled->chip.direction_input = txx9_iocled_dir_in;
  660. iocled->chip.direction_output = txx9_iocled_dir_out;
  661. iocled->chip.label = "iocled";
  662. iocled->chip.base = basenum;
  663. iocled->chip.ngpio = num;
  664. if (gpiochip_add_data(&iocled->chip, iocled))
  665. goto out_unmap;
  666. if (basenum < 0)
  667. basenum = iocled->chip.base;
  668. pdev = platform_device_alloc("leds-gpio", basenum);
  669. if (!pdev)
  670. goto out_gpio;
  671. iocled->pdata.num_leds = num;
  672. iocled->pdata.leds = iocled->leds;
  673. for (i = 0; i < num; i++) {
  674. struct gpio_led *led = &iocled->leds[i];
  675. snprintf(iocled->names[i], sizeof(iocled->names[i]),
  676. "iocled:%s:%u", color, i);
  677. led->name = iocled->names[i];
  678. led->gpio = basenum + i;
  679. led->active_low = lowactive;
  680. if (deftriggers && *deftriggers)
  681. led->default_trigger = *deftriggers++;
  682. }
  683. pdev->dev.platform_data = &iocled->pdata;
  684. if (platform_device_add(pdev))
  685. goto out_pdev;
  686. return;
  687. out_pdev:
  688. platform_device_put(pdev);
  689. out_gpio:
  690. gpiochip_remove(&iocled->chip);
  691. out_unmap:
  692. iounmap(iocled->mmioaddr);
  693. out_free:
  694. kfree(iocled);
  695. }
  696. #else /* CONFIG_LEDS_GPIO */
  697. void __init txx9_iocled_init(unsigned long baseaddr,
  698. int basenum, unsigned int num, int lowactive,
  699. const char *color, char **deftriggers)
  700. {
  701. }
  702. #endif /* CONFIG_LEDS_GPIO */
  703. void __init txx9_dmac_init(int id, unsigned long baseaddr, int irq,
  704. const struct txx9dmac_platform_data *pdata)
  705. {
  706. #if IS_ENABLED(CONFIG_TXX9_DMAC)
  707. struct resource res[] = {
  708. {
  709. .start = baseaddr,
  710. .end = baseaddr + 0x800 - 1,
  711. .flags = IORESOURCE_MEM,
  712. #ifndef CONFIG_MACH_TX49XX
  713. }, {
  714. .start = irq,
  715. .flags = IORESOURCE_IRQ,
  716. #endif
  717. }
  718. };
  719. #ifdef CONFIG_MACH_TX49XX
  720. struct resource chan_res[] = {
  721. {
  722. .flags = IORESOURCE_IRQ,
  723. }
  724. };
  725. #endif
  726. struct platform_device *pdev = platform_device_alloc("txx9dmac", id);
  727. struct txx9dmac_chan_platform_data cpdata;
  728. int i;
  729. if (!pdev ||
  730. platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
  731. platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
  732. platform_device_add(pdev)) {
  733. platform_device_put(pdev);
  734. return;
  735. }
  736. memset(&cpdata, 0, sizeof(cpdata));
  737. cpdata.dmac_dev = pdev;
  738. for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
  739. #ifdef CONFIG_MACH_TX49XX
  740. chan_res[0].start = irq + i;
  741. #endif
  742. pdev = platform_device_alloc("txx9dmac-chan",
  743. id * TXX9_DMA_MAX_NR_CHANNELS + i);
  744. if (!pdev ||
  745. #ifdef CONFIG_MACH_TX49XX
  746. platform_device_add_resources(pdev, chan_res,
  747. ARRAY_SIZE(chan_res)) ||
  748. #endif
  749. platform_device_add_data(pdev, &cpdata, sizeof(cpdata)) ||
  750. platform_device_add(pdev))
  751. platform_device_put(pdev);
  752. }
  753. #endif
  754. }
  755. void __init txx9_aclc_init(unsigned long baseaddr, int irq,
  756. unsigned int dmac_id,
  757. unsigned int dma_chan_out,
  758. unsigned int dma_chan_in)
  759. {
  760. #if IS_ENABLED(CONFIG_SND_SOC_TXX9ACLC)
  761. unsigned int dma_base = dmac_id * TXX9_DMA_MAX_NR_CHANNELS;
  762. struct resource res[] = {
  763. {
  764. .start = baseaddr,
  765. .end = baseaddr + 0x100 - 1,
  766. .flags = IORESOURCE_MEM,
  767. }, {
  768. .start = irq,
  769. .flags = IORESOURCE_IRQ,
  770. }, {
  771. .name = "txx9dmac-chan",
  772. .start = dma_base + dma_chan_out,
  773. .flags = IORESOURCE_DMA,
  774. }, {
  775. .name = "txx9dmac-chan",
  776. .start = dma_base + dma_chan_in,
  777. .flags = IORESOURCE_DMA,
  778. }
  779. };
  780. struct platform_device *pdev =
  781. platform_device_alloc("txx9aclc-ac97", -1);
  782. if (!pdev ||
  783. platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
  784. platform_device_add(pdev))
  785. platform_device_put(pdev);
  786. #endif
  787. }
  788. static struct bus_type txx9_sramc_subsys = {
  789. .name = "txx9_sram",
  790. .dev_name = "txx9_sram",
  791. };
  792. struct txx9_sramc_dev {
  793. struct device dev;
  794. struct bin_attribute bindata_attr;
  795. void __iomem *base;
  796. };
  797. static ssize_t txx9_sram_read(struct file *filp, struct kobject *kobj,
  798. struct bin_attribute *bin_attr,
  799. char *buf, loff_t pos, size_t size)
  800. {
  801. struct txx9_sramc_dev *dev = bin_attr->private;
  802. size_t ramsize = bin_attr->size;
  803. if (pos >= ramsize)
  804. return 0;
  805. if (pos + size > ramsize)
  806. size = ramsize - pos;
  807. memcpy_fromio(buf, dev->base + pos, size);
  808. return size;
  809. }
  810. static ssize_t txx9_sram_write(struct file *filp, struct kobject *kobj,
  811. struct bin_attribute *bin_attr,
  812. char *buf, loff_t pos, size_t size)
  813. {
  814. struct txx9_sramc_dev *dev = bin_attr->private;
  815. size_t ramsize = bin_attr->size;
  816. if (pos >= ramsize)
  817. return 0;
  818. if (pos + size > ramsize)
  819. size = ramsize - pos;
  820. memcpy_toio(dev->base + pos, buf, size);
  821. return size;
  822. }
  823. static void txx9_device_release(struct device *dev)
  824. {
  825. struct txx9_sramc_dev *tdev;
  826. tdev = container_of(dev, struct txx9_sramc_dev, dev);
  827. kfree(tdev);
  828. }
  829. void __init txx9_sramc_init(struct resource *r)
  830. {
  831. struct txx9_sramc_dev *dev;
  832. size_t size;
  833. int err;
  834. err = subsys_system_register(&txx9_sramc_subsys, NULL);
  835. if (err)
  836. return;
  837. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  838. if (!dev)
  839. return;
  840. size = resource_size(r);
  841. dev->base = ioremap(r->start, size);
  842. if (!dev->base) {
  843. kfree(dev);
  844. return;
  845. }
  846. dev->dev.release = &txx9_device_release;
  847. dev->dev.bus = &txx9_sramc_subsys;
  848. sysfs_bin_attr_init(&dev->bindata_attr);
  849. dev->bindata_attr.attr.name = "bindata";
  850. dev->bindata_attr.attr.mode = S_IRUSR | S_IWUSR;
  851. dev->bindata_attr.read = txx9_sram_read;
  852. dev->bindata_attr.write = txx9_sram_write;
  853. dev->bindata_attr.size = size;
  854. dev->bindata_attr.private = dev;
  855. err = device_register(&dev->dev);
  856. if (err)
  857. goto exit_put;
  858. err = sysfs_create_bin_file(&dev->dev.kobj, &dev->bindata_attr);
  859. if (err) {
  860. device_unregister(&dev->dev);
  861. iounmap(dev->base);
  862. kfree(dev);
  863. }
  864. return;
  865. exit_put:
  866. put_device(&dev->dev);
  867. return;
  868. }