smpboot.S 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142
  1. /*
  2. * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
  3. * reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the NetLogic
  9. * license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or without
  12. * modification, are permitted provided that the following conditions
  13. * are met:
  14. *
  15. * 1. Redistributions of source code must retain the above copyright
  16. * notice, this list of conditions and the following disclaimer.
  17. * 2. Redistributions in binary form must reproduce the above copyright
  18. * notice, this list of conditions and the following disclaimer in
  19. * the documentation and/or other materials provided with the
  20. * distribution.
  21. *
  22. * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23. * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25. * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29. * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30. * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31. * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32. * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. #include <asm/asm.h>
  35. #include <asm/asm-offsets.h>
  36. #include <asm/regdef.h>
  37. #include <asm/mipsregs.h>
  38. #include <asm/stackframe.h>
  39. #include <asm/asmmacro.h>
  40. #include <asm/addrspace.h>
  41. #include <asm/netlogic/common.h>
  42. #include <asm/netlogic/xlp-hal/iomap.h>
  43. #include <asm/netlogic/xlp-hal/xlp.h>
  44. #include <asm/netlogic/xlp-hal/sys.h>
  45. #include <asm/netlogic/xlp-hal/cpucontrol.h>
  46. .set noreorder
  47. .set noat
  48. .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
  49. /* Called by the boot cpu to wake up its sibling threads */
  50. NESTED(xlp_boot_core0_siblings, PT_SIZE, sp)
  51. /* CPU register contents lost when enabling threads, save them first */
  52. SAVE_ALL
  53. sync
  54. /* find the location to which nlm_boot_siblings was relocated */
  55. li t0, CKSEG1ADDR(RESET_VEC_PHYS)
  56. dla t1, nlm_reset_entry
  57. dla t2, nlm_boot_siblings
  58. dsubu t2, t1
  59. daddu t2, t0
  60. /* call it */
  61. jalr t2
  62. nop
  63. RESTORE_ALL
  64. jr ra
  65. nop
  66. END(xlp_boot_core0_siblings)
  67. NESTED(nlm_boot_secondary_cpus, 16, sp)
  68. /* Initialize CP0 Status */
  69. move t1, zero
  70. #ifdef CONFIG_64BIT
  71. ori t1, ST0_KX
  72. #endif
  73. mtc0 t1, CP0_STATUS
  74. PTR_LA t1, nlm_next_sp
  75. PTR_L sp, 0(t1)
  76. PTR_LA t1, nlm_next_gp
  77. PTR_L gp, 0(t1)
  78. /* a0 has the processor id */
  79. mfc0 a0, CP0_EBASE
  80. andi a0, 0x3ff /* a0 <- node/core */
  81. PTR_LA t0, nlm_early_init_secondary
  82. jalr t0
  83. nop
  84. PTR_LA t0, smp_bootstrap
  85. jr t0
  86. nop
  87. END(nlm_boot_secondary_cpus)
  88. /*
  89. * In case of RMIboot bootloader which is used on XLR boards, the CPUs
  90. * be already woken up and waiting in bootloader code.
  91. * This will get them out of the bootloader code and into linux. Needed
  92. * because the bootloader area will be taken and initialized by linux.
  93. */
  94. NESTED(nlm_rmiboot_preboot, 16, sp)
  95. mfc0 t0, $15, 1 /* read ebase */
  96. andi t0, 0x1f /* t0 has the processor_id() */
  97. andi t2, t0, 0x3 /* thread num */
  98. sll t0, 2 /* offset in cpu array */
  99. li t3, CKSEG1ADDR(RESET_DATA_PHYS)
  100. ADDIU t1, t3, BOOT_CPU_READY
  101. ADDU t1, t0
  102. li t3, 1
  103. sw t3, 0(t1)
  104. bnez t2, 1f /* skip thread programming */
  105. nop /* for thread id != 0 */
  106. /*
  107. * XLR MMU setup only for first thread in core
  108. */
  109. li t0, 0x400
  110. mfcr t1, t0
  111. li t2, 6 /* XLR thread mode mask */
  112. nor t3, t2, zero
  113. and t2, t1, t2 /* t2 - current thread mode */
  114. li v0, CKSEG1ADDR(RESET_DATA_PHYS)
  115. lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
  116. sll v1, 1
  117. beq v1, t2, 1f /* same as request value */
  118. nop /* nothing to do */
  119. and t2, t1, t3 /* mask out old thread mode */
  120. or t1, t2, v1 /* put in new value */
  121. mtcr t1, t0 /* update core control */
  122. /* wait for NMI to hit */
  123. 1: wait
  124. b 1b
  125. nop
  126. END(nlm_rmiboot_preboot)