cp1emu.c 63 KB

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  1. /*
  2. * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
  3. *
  4. * MIPS floating point support
  5. * Copyright (C) 1994-2000 Algorithmics Ltd.
  6. *
  7. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  8. * Copyright (C) 2000 MIPS Technologies, Inc.
  9. *
  10. * This program is free software; you can distribute it and/or modify it
  11. * under the terms of the GNU General Public License (Version 2) as
  12. * published by the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope it will be useful, but WITHOUT
  15. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  17. * for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License along
  20. * with this program; if not, write to the Free Software Foundation, Inc.,
  21. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  22. *
  23. * A complete emulator for MIPS coprocessor 1 instructions. This is
  24. * required for #float(switch) or #float(trap), where it catches all
  25. * COP1 instructions via the "CoProcessor Unusable" exception.
  26. *
  27. * More surprisingly it is also required for #float(ieee), to help out
  28. * the hardware FPU at the boundaries of the IEEE-754 representation
  29. * (denormalised values, infinities, underflow, etc). It is made
  30. * quite nasty because emulation of some non-COP1 instructions is
  31. * required, e.g. in branch delay slots.
  32. *
  33. * Note if you know that you won't have an FPU, then you'll get much
  34. * better performance by compiling with -msoft-float!
  35. */
  36. #include <linux/sched.h>
  37. #include <linux/debugfs.h>
  38. #include <linux/percpu-defs.h>
  39. #include <linux/perf_event.h>
  40. #include <asm/branch.h>
  41. #include <asm/inst.h>
  42. #include <asm/ptrace.h>
  43. #include <asm/signal.h>
  44. #include <asm/uaccess.h>
  45. #include <asm/cpu-info.h>
  46. #include <asm/processor.h>
  47. #include <asm/fpu_emulator.h>
  48. #include <asm/fpu.h>
  49. #include <asm/mips-r2-to-r6-emul.h>
  50. #include "ieee754.h"
  51. /* Function which emulates a floating point instruction. */
  52. static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
  53. mips_instruction);
  54. static int fpux_emu(struct pt_regs *,
  55. struct mips_fpu_struct *, mips_instruction, void *__user *);
  56. /* Control registers */
  57. #define FPCREG_RID 0 /* $0 = revision id */
  58. #define FPCREG_FCCR 25 /* $25 = fccr */
  59. #define FPCREG_FEXR 26 /* $26 = fexr */
  60. #define FPCREG_FENR 28 /* $28 = fenr */
  61. #define FPCREG_CSR 31 /* $31 = csr */
  62. /* convert condition code register number to csr bit */
  63. const unsigned int fpucondbit[8] = {
  64. FPU_CSR_COND,
  65. FPU_CSR_COND1,
  66. FPU_CSR_COND2,
  67. FPU_CSR_COND3,
  68. FPU_CSR_COND4,
  69. FPU_CSR_COND5,
  70. FPU_CSR_COND6,
  71. FPU_CSR_COND7
  72. };
  73. /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
  74. static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
  75. static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
  76. static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
  77. static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
  78. /*
  79. * This functions translates a 32-bit microMIPS instruction
  80. * into a 32-bit MIPS32 instruction. Returns 0 on success
  81. * and SIGILL otherwise.
  82. */
  83. static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
  84. {
  85. union mips_instruction insn = *insn_ptr;
  86. union mips_instruction mips32_insn = insn;
  87. int func, fmt, op;
  88. switch (insn.mm_i_format.opcode) {
  89. case mm_ldc132_op:
  90. mips32_insn.mm_i_format.opcode = ldc1_op;
  91. mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
  92. mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
  93. break;
  94. case mm_lwc132_op:
  95. mips32_insn.mm_i_format.opcode = lwc1_op;
  96. mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
  97. mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
  98. break;
  99. case mm_sdc132_op:
  100. mips32_insn.mm_i_format.opcode = sdc1_op;
  101. mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
  102. mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
  103. break;
  104. case mm_swc132_op:
  105. mips32_insn.mm_i_format.opcode = swc1_op;
  106. mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
  107. mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
  108. break;
  109. case mm_pool32i_op:
  110. /* NOTE: offset is << by 1 if in microMIPS mode. */
  111. if ((insn.mm_i_format.rt == mm_bc1f_op) ||
  112. (insn.mm_i_format.rt == mm_bc1t_op)) {
  113. mips32_insn.fb_format.opcode = cop1_op;
  114. mips32_insn.fb_format.bc = bc_op;
  115. mips32_insn.fb_format.flag =
  116. (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
  117. } else
  118. return SIGILL;
  119. break;
  120. case mm_pool32f_op:
  121. switch (insn.mm_fp0_format.func) {
  122. case mm_32f_01_op:
  123. case mm_32f_11_op:
  124. case mm_32f_02_op:
  125. case mm_32f_12_op:
  126. case mm_32f_41_op:
  127. case mm_32f_51_op:
  128. case mm_32f_42_op:
  129. case mm_32f_52_op:
  130. op = insn.mm_fp0_format.func;
  131. if (op == mm_32f_01_op)
  132. func = madd_s_op;
  133. else if (op == mm_32f_11_op)
  134. func = madd_d_op;
  135. else if (op == mm_32f_02_op)
  136. func = nmadd_s_op;
  137. else if (op == mm_32f_12_op)
  138. func = nmadd_d_op;
  139. else if (op == mm_32f_41_op)
  140. func = msub_s_op;
  141. else if (op == mm_32f_51_op)
  142. func = msub_d_op;
  143. else if (op == mm_32f_42_op)
  144. func = nmsub_s_op;
  145. else
  146. func = nmsub_d_op;
  147. mips32_insn.fp6_format.opcode = cop1x_op;
  148. mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
  149. mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
  150. mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
  151. mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
  152. mips32_insn.fp6_format.func = func;
  153. break;
  154. case mm_32f_10_op:
  155. func = -1; /* Invalid */
  156. op = insn.mm_fp5_format.op & 0x7;
  157. if (op == mm_ldxc1_op)
  158. func = ldxc1_op;
  159. else if (op == mm_sdxc1_op)
  160. func = sdxc1_op;
  161. else if (op == mm_lwxc1_op)
  162. func = lwxc1_op;
  163. else if (op == mm_swxc1_op)
  164. func = swxc1_op;
  165. if (func != -1) {
  166. mips32_insn.r_format.opcode = cop1x_op;
  167. mips32_insn.r_format.rs =
  168. insn.mm_fp5_format.base;
  169. mips32_insn.r_format.rt =
  170. insn.mm_fp5_format.index;
  171. mips32_insn.r_format.rd = 0;
  172. mips32_insn.r_format.re = insn.mm_fp5_format.fd;
  173. mips32_insn.r_format.func = func;
  174. } else
  175. return SIGILL;
  176. break;
  177. case mm_32f_40_op:
  178. op = -1; /* Invalid */
  179. if (insn.mm_fp2_format.op == mm_fmovt_op)
  180. op = 1;
  181. else if (insn.mm_fp2_format.op == mm_fmovf_op)
  182. op = 0;
  183. if (op != -1) {
  184. mips32_insn.fp0_format.opcode = cop1_op;
  185. mips32_insn.fp0_format.fmt =
  186. sdps_format[insn.mm_fp2_format.fmt];
  187. mips32_insn.fp0_format.ft =
  188. (insn.mm_fp2_format.cc<<2) + op;
  189. mips32_insn.fp0_format.fs =
  190. insn.mm_fp2_format.fs;
  191. mips32_insn.fp0_format.fd =
  192. insn.mm_fp2_format.fd;
  193. mips32_insn.fp0_format.func = fmovc_op;
  194. } else
  195. return SIGILL;
  196. break;
  197. case mm_32f_60_op:
  198. func = -1; /* Invalid */
  199. if (insn.mm_fp0_format.op == mm_fadd_op)
  200. func = fadd_op;
  201. else if (insn.mm_fp0_format.op == mm_fsub_op)
  202. func = fsub_op;
  203. else if (insn.mm_fp0_format.op == mm_fmul_op)
  204. func = fmul_op;
  205. else if (insn.mm_fp0_format.op == mm_fdiv_op)
  206. func = fdiv_op;
  207. if (func != -1) {
  208. mips32_insn.fp0_format.opcode = cop1_op;
  209. mips32_insn.fp0_format.fmt =
  210. sdps_format[insn.mm_fp0_format.fmt];
  211. mips32_insn.fp0_format.ft =
  212. insn.mm_fp0_format.ft;
  213. mips32_insn.fp0_format.fs =
  214. insn.mm_fp0_format.fs;
  215. mips32_insn.fp0_format.fd =
  216. insn.mm_fp0_format.fd;
  217. mips32_insn.fp0_format.func = func;
  218. } else
  219. return SIGILL;
  220. break;
  221. case mm_32f_70_op:
  222. func = -1; /* Invalid */
  223. if (insn.mm_fp0_format.op == mm_fmovn_op)
  224. func = fmovn_op;
  225. else if (insn.mm_fp0_format.op == mm_fmovz_op)
  226. func = fmovz_op;
  227. if (func != -1) {
  228. mips32_insn.fp0_format.opcode = cop1_op;
  229. mips32_insn.fp0_format.fmt =
  230. sdps_format[insn.mm_fp0_format.fmt];
  231. mips32_insn.fp0_format.ft =
  232. insn.mm_fp0_format.ft;
  233. mips32_insn.fp0_format.fs =
  234. insn.mm_fp0_format.fs;
  235. mips32_insn.fp0_format.fd =
  236. insn.mm_fp0_format.fd;
  237. mips32_insn.fp0_format.func = func;
  238. } else
  239. return SIGILL;
  240. break;
  241. case mm_32f_73_op: /* POOL32FXF */
  242. switch (insn.mm_fp1_format.op) {
  243. case mm_movf0_op:
  244. case mm_movf1_op:
  245. case mm_movt0_op:
  246. case mm_movt1_op:
  247. if ((insn.mm_fp1_format.op & 0x7f) ==
  248. mm_movf0_op)
  249. op = 0;
  250. else
  251. op = 1;
  252. mips32_insn.r_format.opcode = spec_op;
  253. mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
  254. mips32_insn.r_format.rt =
  255. (insn.mm_fp4_format.cc << 2) + op;
  256. mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
  257. mips32_insn.r_format.re = 0;
  258. mips32_insn.r_format.func = movc_op;
  259. break;
  260. case mm_fcvtd0_op:
  261. case mm_fcvtd1_op:
  262. case mm_fcvts0_op:
  263. case mm_fcvts1_op:
  264. if ((insn.mm_fp1_format.op & 0x7f) ==
  265. mm_fcvtd0_op) {
  266. func = fcvtd_op;
  267. fmt = swl_format[insn.mm_fp3_format.fmt];
  268. } else {
  269. func = fcvts_op;
  270. fmt = dwl_format[insn.mm_fp3_format.fmt];
  271. }
  272. mips32_insn.fp0_format.opcode = cop1_op;
  273. mips32_insn.fp0_format.fmt = fmt;
  274. mips32_insn.fp0_format.ft = 0;
  275. mips32_insn.fp0_format.fs =
  276. insn.mm_fp3_format.fs;
  277. mips32_insn.fp0_format.fd =
  278. insn.mm_fp3_format.rt;
  279. mips32_insn.fp0_format.func = func;
  280. break;
  281. case mm_fmov0_op:
  282. case mm_fmov1_op:
  283. case mm_fabs0_op:
  284. case mm_fabs1_op:
  285. case mm_fneg0_op:
  286. case mm_fneg1_op:
  287. if ((insn.mm_fp1_format.op & 0x7f) ==
  288. mm_fmov0_op)
  289. func = fmov_op;
  290. else if ((insn.mm_fp1_format.op & 0x7f) ==
  291. mm_fabs0_op)
  292. func = fabs_op;
  293. else
  294. func = fneg_op;
  295. mips32_insn.fp0_format.opcode = cop1_op;
  296. mips32_insn.fp0_format.fmt =
  297. sdps_format[insn.mm_fp3_format.fmt];
  298. mips32_insn.fp0_format.ft = 0;
  299. mips32_insn.fp0_format.fs =
  300. insn.mm_fp3_format.fs;
  301. mips32_insn.fp0_format.fd =
  302. insn.mm_fp3_format.rt;
  303. mips32_insn.fp0_format.func = func;
  304. break;
  305. case mm_ffloorl_op:
  306. case mm_ffloorw_op:
  307. case mm_fceill_op:
  308. case mm_fceilw_op:
  309. case mm_ftruncl_op:
  310. case mm_ftruncw_op:
  311. case mm_froundl_op:
  312. case mm_froundw_op:
  313. case mm_fcvtl_op:
  314. case mm_fcvtw_op:
  315. if (insn.mm_fp1_format.op == mm_ffloorl_op)
  316. func = ffloorl_op;
  317. else if (insn.mm_fp1_format.op == mm_ffloorw_op)
  318. func = ffloor_op;
  319. else if (insn.mm_fp1_format.op == mm_fceill_op)
  320. func = fceill_op;
  321. else if (insn.mm_fp1_format.op == mm_fceilw_op)
  322. func = fceil_op;
  323. else if (insn.mm_fp1_format.op == mm_ftruncl_op)
  324. func = ftruncl_op;
  325. else if (insn.mm_fp1_format.op == mm_ftruncw_op)
  326. func = ftrunc_op;
  327. else if (insn.mm_fp1_format.op == mm_froundl_op)
  328. func = froundl_op;
  329. else if (insn.mm_fp1_format.op == mm_froundw_op)
  330. func = fround_op;
  331. else if (insn.mm_fp1_format.op == mm_fcvtl_op)
  332. func = fcvtl_op;
  333. else
  334. func = fcvtw_op;
  335. mips32_insn.fp0_format.opcode = cop1_op;
  336. mips32_insn.fp0_format.fmt =
  337. sd_format[insn.mm_fp1_format.fmt];
  338. mips32_insn.fp0_format.ft = 0;
  339. mips32_insn.fp0_format.fs =
  340. insn.mm_fp1_format.fs;
  341. mips32_insn.fp0_format.fd =
  342. insn.mm_fp1_format.rt;
  343. mips32_insn.fp0_format.func = func;
  344. break;
  345. case mm_frsqrt_op:
  346. case mm_fsqrt_op:
  347. case mm_frecip_op:
  348. if (insn.mm_fp1_format.op == mm_frsqrt_op)
  349. func = frsqrt_op;
  350. else if (insn.mm_fp1_format.op == mm_fsqrt_op)
  351. func = fsqrt_op;
  352. else
  353. func = frecip_op;
  354. mips32_insn.fp0_format.opcode = cop1_op;
  355. mips32_insn.fp0_format.fmt =
  356. sdps_format[insn.mm_fp1_format.fmt];
  357. mips32_insn.fp0_format.ft = 0;
  358. mips32_insn.fp0_format.fs =
  359. insn.mm_fp1_format.fs;
  360. mips32_insn.fp0_format.fd =
  361. insn.mm_fp1_format.rt;
  362. mips32_insn.fp0_format.func = func;
  363. break;
  364. case mm_mfc1_op:
  365. case mm_mtc1_op:
  366. case mm_cfc1_op:
  367. case mm_ctc1_op:
  368. case mm_mfhc1_op:
  369. case mm_mthc1_op:
  370. if (insn.mm_fp1_format.op == mm_mfc1_op)
  371. op = mfc_op;
  372. else if (insn.mm_fp1_format.op == mm_mtc1_op)
  373. op = mtc_op;
  374. else if (insn.mm_fp1_format.op == mm_cfc1_op)
  375. op = cfc_op;
  376. else if (insn.mm_fp1_format.op == mm_ctc1_op)
  377. op = ctc_op;
  378. else if (insn.mm_fp1_format.op == mm_mfhc1_op)
  379. op = mfhc_op;
  380. else
  381. op = mthc_op;
  382. mips32_insn.fp1_format.opcode = cop1_op;
  383. mips32_insn.fp1_format.op = op;
  384. mips32_insn.fp1_format.rt =
  385. insn.mm_fp1_format.rt;
  386. mips32_insn.fp1_format.fs =
  387. insn.mm_fp1_format.fs;
  388. mips32_insn.fp1_format.fd = 0;
  389. mips32_insn.fp1_format.func = 0;
  390. break;
  391. default:
  392. return SIGILL;
  393. }
  394. break;
  395. case mm_32f_74_op: /* c.cond.fmt */
  396. mips32_insn.fp0_format.opcode = cop1_op;
  397. mips32_insn.fp0_format.fmt =
  398. sdps_format[insn.mm_fp4_format.fmt];
  399. mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
  400. mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
  401. mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
  402. mips32_insn.fp0_format.func =
  403. insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
  404. break;
  405. default:
  406. return SIGILL;
  407. }
  408. break;
  409. default:
  410. return SIGILL;
  411. }
  412. *insn_ptr = mips32_insn;
  413. return 0;
  414. }
  415. /*
  416. * Redundant with logic already in kernel/branch.c,
  417. * embedded in compute_return_epc. At some point,
  418. * a single subroutine should be used across both
  419. * modules.
  420. */
  421. int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
  422. unsigned long *contpc)
  423. {
  424. union mips_instruction insn = (union mips_instruction)dec_insn.insn;
  425. unsigned int fcr31;
  426. unsigned int bit = 0;
  427. switch (insn.i_format.opcode) {
  428. case spec_op:
  429. switch (insn.r_format.func) {
  430. case jalr_op:
  431. if (insn.r_format.rd != 0) {
  432. regs->regs[insn.r_format.rd] =
  433. regs->cp0_epc + dec_insn.pc_inc +
  434. dec_insn.next_pc_inc;
  435. }
  436. /* Fall through */
  437. case jr_op:
  438. /* For R6, JR already emulated in jalr_op */
  439. if (NO_R6EMU && insn.r_format.func == jr_op)
  440. break;
  441. *contpc = regs->regs[insn.r_format.rs];
  442. return 1;
  443. }
  444. break;
  445. case bcond_op:
  446. switch (insn.i_format.rt) {
  447. case bltzal_op:
  448. case bltzall_op:
  449. if (NO_R6EMU && (insn.i_format.rs ||
  450. insn.i_format.rt == bltzall_op))
  451. break;
  452. regs->regs[31] = regs->cp0_epc +
  453. dec_insn.pc_inc +
  454. dec_insn.next_pc_inc;
  455. /* Fall through */
  456. case bltzl_op:
  457. if (NO_R6EMU)
  458. break;
  459. case bltz_op:
  460. if ((long)regs->regs[insn.i_format.rs] < 0)
  461. *contpc = regs->cp0_epc +
  462. dec_insn.pc_inc +
  463. (insn.i_format.simmediate << 2);
  464. else
  465. *contpc = regs->cp0_epc +
  466. dec_insn.pc_inc +
  467. dec_insn.next_pc_inc;
  468. return 1;
  469. case bgezal_op:
  470. case bgezall_op:
  471. if (NO_R6EMU && (insn.i_format.rs ||
  472. insn.i_format.rt == bgezall_op))
  473. break;
  474. regs->regs[31] = regs->cp0_epc +
  475. dec_insn.pc_inc +
  476. dec_insn.next_pc_inc;
  477. /* Fall through */
  478. case bgezl_op:
  479. if (NO_R6EMU)
  480. break;
  481. case bgez_op:
  482. if ((long)regs->regs[insn.i_format.rs] >= 0)
  483. *contpc = regs->cp0_epc +
  484. dec_insn.pc_inc +
  485. (insn.i_format.simmediate << 2);
  486. else
  487. *contpc = regs->cp0_epc +
  488. dec_insn.pc_inc +
  489. dec_insn.next_pc_inc;
  490. return 1;
  491. }
  492. break;
  493. case jalx_op:
  494. set_isa16_mode(bit);
  495. case jal_op:
  496. regs->regs[31] = regs->cp0_epc +
  497. dec_insn.pc_inc +
  498. dec_insn.next_pc_inc;
  499. /* Fall through */
  500. case j_op:
  501. *contpc = regs->cp0_epc + dec_insn.pc_inc;
  502. *contpc >>= 28;
  503. *contpc <<= 28;
  504. *contpc |= (insn.j_format.target << 2);
  505. /* Set microMIPS mode bit: XOR for jalx. */
  506. *contpc ^= bit;
  507. return 1;
  508. case beql_op:
  509. if (NO_R6EMU)
  510. break;
  511. case beq_op:
  512. if (regs->regs[insn.i_format.rs] ==
  513. regs->regs[insn.i_format.rt])
  514. *contpc = regs->cp0_epc +
  515. dec_insn.pc_inc +
  516. (insn.i_format.simmediate << 2);
  517. else
  518. *contpc = regs->cp0_epc +
  519. dec_insn.pc_inc +
  520. dec_insn.next_pc_inc;
  521. return 1;
  522. case bnel_op:
  523. if (NO_R6EMU)
  524. break;
  525. case bne_op:
  526. if (regs->regs[insn.i_format.rs] !=
  527. regs->regs[insn.i_format.rt])
  528. *contpc = regs->cp0_epc +
  529. dec_insn.pc_inc +
  530. (insn.i_format.simmediate << 2);
  531. else
  532. *contpc = regs->cp0_epc +
  533. dec_insn.pc_inc +
  534. dec_insn.next_pc_inc;
  535. return 1;
  536. case blezl_op:
  537. if (!insn.i_format.rt && NO_R6EMU)
  538. break;
  539. case blez_op:
  540. /*
  541. * Compact branches for R6 for the
  542. * blez and blezl opcodes.
  543. * BLEZ | rs = 0 | rt != 0 == BLEZALC
  544. * BLEZ | rs = rt != 0 == BGEZALC
  545. * BLEZ | rs != 0 | rt != 0 == BGEUC
  546. * BLEZL | rs = 0 | rt != 0 == BLEZC
  547. * BLEZL | rs = rt != 0 == BGEZC
  548. * BLEZL | rs != 0 | rt != 0 == BGEC
  549. *
  550. * For real BLEZ{,L}, rt is always 0.
  551. */
  552. if (cpu_has_mips_r6 && insn.i_format.rt) {
  553. if ((insn.i_format.opcode == blez_op) &&
  554. ((!insn.i_format.rs && insn.i_format.rt) ||
  555. (insn.i_format.rs == insn.i_format.rt)))
  556. regs->regs[31] = regs->cp0_epc +
  557. dec_insn.pc_inc;
  558. *contpc = regs->cp0_epc + dec_insn.pc_inc +
  559. dec_insn.next_pc_inc;
  560. return 1;
  561. }
  562. if ((long)regs->regs[insn.i_format.rs] <= 0)
  563. *contpc = regs->cp0_epc +
  564. dec_insn.pc_inc +
  565. (insn.i_format.simmediate << 2);
  566. else
  567. *contpc = regs->cp0_epc +
  568. dec_insn.pc_inc +
  569. dec_insn.next_pc_inc;
  570. return 1;
  571. case bgtzl_op:
  572. if (!insn.i_format.rt && NO_R6EMU)
  573. break;
  574. case bgtz_op:
  575. /*
  576. * Compact branches for R6 for the
  577. * bgtz and bgtzl opcodes.
  578. * BGTZ | rs = 0 | rt != 0 == BGTZALC
  579. * BGTZ | rs = rt != 0 == BLTZALC
  580. * BGTZ | rs != 0 | rt != 0 == BLTUC
  581. * BGTZL | rs = 0 | rt != 0 == BGTZC
  582. * BGTZL | rs = rt != 0 == BLTZC
  583. * BGTZL | rs != 0 | rt != 0 == BLTC
  584. *
  585. * *ZALC varint for BGTZ &&& rt != 0
  586. * For real GTZ{,L}, rt is always 0.
  587. */
  588. if (cpu_has_mips_r6 && insn.i_format.rt) {
  589. if ((insn.i_format.opcode == blez_op) &&
  590. ((!insn.i_format.rs && insn.i_format.rt) ||
  591. (insn.i_format.rs == insn.i_format.rt)))
  592. regs->regs[31] = regs->cp0_epc +
  593. dec_insn.pc_inc;
  594. *contpc = regs->cp0_epc + dec_insn.pc_inc +
  595. dec_insn.next_pc_inc;
  596. return 1;
  597. }
  598. if ((long)regs->regs[insn.i_format.rs] > 0)
  599. *contpc = regs->cp0_epc +
  600. dec_insn.pc_inc +
  601. (insn.i_format.simmediate << 2);
  602. else
  603. *contpc = regs->cp0_epc +
  604. dec_insn.pc_inc +
  605. dec_insn.next_pc_inc;
  606. return 1;
  607. case pop10_op:
  608. case pop30_op:
  609. if (!cpu_has_mips_r6)
  610. break;
  611. if (insn.i_format.rt && !insn.i_format.rs)
  612. regs->regs[31] = regs->cp0_epc + 4;
  613. *contpc = regs->cp0_epc + dec_insn.pc_inc +
  614. dec_insn.next_pc_inc;
  615. return 1;
  616. #ifdef CONFIG_CPU_CAVIUM_OCTEON
  617. case lwc2_op: /* This is bbit0 on Octeon */
  618. if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
  619. *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
  620. else
  621. *contpc = regs->cp0_epc + 8;
  622. return 1;
  623. case ldc2_op: /* This is bbit032 on Octeon */
  624. if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
  625. *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
  626. else
  627. *contpc = regs->cp0_epc + 8;
  628. return 1;
  629. case swc2_op: /* This is bbit1 on Octeon */
  630. if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
  631. *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
  632. else
  633. *contpc = regs->cp0_epc + 8;
  634. return 1;
  635. case sdc2_op: /* This is bbit132 on Octeon */
  636. if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
  637. *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
  638. else
  639. *contpc = regs->cp0_epc + 8;
  640. return 1;
  641. #else
  642. case bc6_op:
  643. /*
  644. * Only valid for MIPS R6 but we can still end up
  645. * here from a broken userland so just tell emulator
  646. * this is not a branch and let it break later on.
  647. */
  648. if (!cpu_has_mips_r6)
  649. break;
  650. *contpc = regs->cp0_epc + dec_insn.pc_inc +
  651. dec_insn.next_pc_inc;
  652. return 1;
  653. case balc6_op:
  654. if (!cpu_has_mips_r6)
  655. break;
  656. regs->regs[31] = regs->cp0_epc + 4;
  657. *contpc = regs->cp0_epc + dec_insn.pc_inc +
  658. dec_insn.next_pc_inc;
  659. return 1;
  660. case pop66_op:
  661. if (!cpu_has_mips_r6)
  662. break;
  663. *contpc = regs->cp0_epc + dec_insn.pc_inc +
  664. dec_insn.next_pc_inc;
  665. return 1;
  666. case pop76_op:
  667. if (!cpu_has_mips_r6)
  668. break;
  669. if (!insn.i_format.rs)
  670. regs->regs[31] = regs->cp0_epc + 4;
  671. *contpc = regs->cp0_epc + dec_insn.pc_inc +
  672. dec_insn.next_pc_inc;
  673. return 1;
  674. #endif
  675. case cop0_op:
  676. case cop1_op:
  677. /* Need to check for R6 bc1nez and bc1eqz branches */
  678. if (cpu_has_mips_r6 &&
  679. ((insn.i_format.rs == bc1eqz_op) ||
  680. (insn.i_format.rs == bc1nez_op))) {
  681. bit = 0;
  682. switch (insn.i_format.rs) {
  683. case bc1eqz_op:
  684. if (get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
  685. bit = 1;
  686. break;
  687. case bc1nez_op:
  688. if (!(get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
  689. bit = 1;
  690. break;
  691. }
  692. if (bit)
  693. *contpc = regs->cp0_epc +
  694. dec_insn.pc_inc +
  695. (insn.i_format.simmediate << 2);
  696. else
  697. *contpc = regs->cp0_epc +
  698. dec_insn.pc_inc +
  699. dec_insn.next_pc_inc;
  700. return 1;
  701. }
  702. /* R2/R6 compatible cop1 instruction. Fall through */
  703. case cop2_op:
  704. case cop1x_op:
  705. if (insn.i_format.rs == bc_op) {
  706. preempt_disable();
  707. if (is_fpu_owner())
  708. fcr31 = read_32bit_cp1_register(CP1_STATUS);
  709. else
  710. fcr31 = current->thread.fpu.fcr31;
  711. preempt_enable();
  712. bit = (insn.i_format.rt >> 2);
  713. bit += (bit != 0);
  714. bit += 23;
  715. switch (insn.i_format.rt & 3) {
  716. case 0: /* bc1f */
  717. case 2: /* bc1fl */
  718. if (~fcr31 & (1 << bit))
  719. *contpc = regs->cp0_epc +
  720. dec_insn.pc_inc +
  721. (insn.i_format.simmediate << 2);
  722. else
  723. *contpc = regs->cp0_epc +
  724. dec_insn.pc_inc +
  725. dec_insn.next_pc_inc;
  726. return 1;
  727. case 1: /* bc1t */
  728. case 3: /* bc1tl */
  729. if (fcr31 & (1 << bit))
  730. *contpc = regs->cp0_epc +
  731. dec_insn.pc_inc +
  732. (insn.i_format.simmediate << 2);
  733. else
  734. *contpc = regs->cp0_epc +
  735. dec_insn.pc_inc +
  736. dec_insn.next_pc_inc;
  737. return 1;
  738. }
  739. }
  740. break;
  741. }
  742. return 0;
  743. }
  744. /*
  745. * In the Linux kernel, we support selection of FPR format on the
  746. * basis of the Status.FR bit. If an FPU is not present, the FR bit
  747. * is hardwired to zero, which would imply a 32-bit FPU even for
  748. * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
  749. * FPU emu is slow and bulky and optimizing this function offers fairly
  750. * sizeable benefits so we try to be clever and make this function return
  751. * a constant whenever possible, that is on 64-bit kernels without O32
  752. * compatibility enabled and on 32-bit without 64-bit FPU support.
  753. */
  754. static inline int cop1_64bit(struct pt_regs *xcp)
  755. {
  756. if (IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_MIPS32_O32))
  757. return 1;
  758. else if (IS_ENABLED(CONFIG_32BIT) &&
  759. !IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
  760. return 0;
  761. return !test_thread_flag(TIF_32BIT_FPREGS);
  762. }
  763. static inline bool hybrid_fprs(void)
  764. {
  765. return test_thread_flag(TIF_HYBRID_FPREGS);
  766. }
  767. #define SIFROMREG(si, x) \
  768. do { \
  769. if (cop1_64bit(xcp) && !hybrid_fprs()) \
  770. (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
  771. else \
  772. (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
  773. } while (0)
  774. #define SITOREG(si, x) \
  775. do { \
  776. if (cop1_64bit(xcp) && !hybrid_fprs()) { \
  777. unsigned i; \
  778. set_fpr32(&ctx->fpr[x], 0, si); \
  779. for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
  780. set_fpr32(&ctx->fpr[x], i, 0); \
  781. } else { \
  782. set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
  783. } \
  784. } while (0)
  785. #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
  786. #define SITOHREG(si, x) \
  787. do { \
  788. unsigned i; \
  789. set_fpr32(&ctx->fpr[x], 1, si); \
  790. for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
  791. set_fpr32(&ctx->fpr[x], i, 0); \
  792. } while (0)
  793. #define DIFROMREG(di, x) \
  794. ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
  795. #define DITOREG(di, x) \
  796. do { \
  797. unsigned fpr, i; \
  798. fpr = (x) & ~(cop1_64bit(xcp) == 0); \
  799. set_fpr64(&ctx->fpr[fpr], 0, di); \
  800. for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
  801. set_fpr64(&ctx->fpr[fpr], i, 0); \
  802. } while (0)
  803. #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
  804. #define SPTOREG(sp, x) SITOREG((sp).bits, x)
  805. #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
  806. #define DPTOREG(dp, x) DITOREG((dp).bits, x)
  807. /*
  808. * Emulate a CFC1 instruction.
  809. */
  810. static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
  811. mips_instruction ir)
  812. {
  813. u32 fcr31 = ctx->fcr31;
  814. u32 value = 0;
  815. switch (MIPSInst_RD(ir)) {
  816. case FPCREG_CSR:
  817. value = fcr31;
  818. pr_debug("%p gpr[%d]<-csr=%08x\n",
  819. (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
  820. break;
  821. case FPCREG_FENR:
  822. if (!cpu_has_mips_r)
  823. break;
  824. value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
  825. MIPS_FENR_FS;
  826. value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
  827. pr_debug("%p gpr[%d]<-enr=%08x\n",
  828. (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
  829. break;
  830. case FPCREG_FEXR:
  831. if (!cpu_has_mips_r)
  832. break;
  833. value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
  834. pr_debug("%p gpr[%d]<-exr=%08x\n",
  835. (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
  836. break;
  837. case FPCREG_FCCR:
  838. if (!cpu_has_mips_r)
  839. break;
  840. value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
  841. MIPS_FCCR_COND0;
  842. value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
  843. (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
  844. pr_debug("%p gpr[%d]<-ccr=%08x\n",
  845. (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
  846. break;
  847. case FPCREG_RID:
  848. value = boot_cpu_data.fpu_id;
  849. break;
  850. default:
  851. break;
  852. }
  853. if (MIPSInst_RT(ir))
  854. xcp->regs[MIPSInst_RT(ir)] = value;
  855. }
  856. /*
  857. * Emulate a CTC1 instruction.
  858. */
  859. static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
  860. mips_instruction ir)
  861. {
  862. u32 fcr31 = ctx->fcr31;
  863. u32 value;
  864. u32 mask;
  865. if (MIPSInst_RT(ir) == 0)
  866. value = 0;
  867. else
  868. value = xcp->regs[MIPSInst_RT(ir)];
  869. switch (MIPSInst_RD(ir)) {
  870. case FPCREG_CSR:
  871. pr_debug("%p gpr[%d]->csr=%08x\n",
  872. (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
  873. /* Preserve read-only bits. */
  874. mask = boot_cpu_data.fpu_msk31;
  875. fcr31 = (value & ~mask) | (fcr31 & mask);
  876. break;
  877. case FPCREG_FENR:
  878. if (!cpu_has_mips_r)
  879. break;
  880. pr_debug("%p gpr[%d]->enr=%08x\n",
  881. (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
  882. fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
  883. fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
  884. FPU_CSR_FS;
  885. fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
  886. break;
  887. case FPCREG_FEXR:
  888. if (!cpu_has_mips_r)
  889. break;
  890. pr_debug("%p gpr[%d]->exr=%08x\n",
  891. (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
  892. fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
  893. fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
  894. break;
  895. case FPCREG_FCCR:
  896. if (!cpu_has_mips_r)
  897. break;
  898. pr_debug("%p gpr[%d]->ccr=%08x\n",
  899. (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
  900. fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
  901. fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
  902. FPU_CSR_COND;
  903. fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
  904. FPU_CSR_CONDX;
  905. break;
  906. default:
  907. break;
  908. }
  909. ctx->fcr31 = fcr31;
  910. }
  911. /*
  912. * Emulate the single floating point instruction pointed at by EPC.
  913. * Two instructions if the instruction is in a branch delay slot.
  914. */
  915. static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
  916. struct mm_decoded_insn dec_insn, void *__user *fault_addr)
  917. {
  918. unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
  919. unsigned int cond, cbit, bit0;
  920. mips_instruction ir;
  921. int likely, pc_inc;
  922. union fpureg *fpr;
  923. u32 __user *wva;
  924. u64 __user *dva;
  925. u32 wval;
  926. u64 dval;
  927. int sig;
  928. /*
  929. * These are giving gcc a gentle hint about what to expect in
  930. * dec_inst in order to do better optimization.
  931. */
  932. if (!cpu_has_mmips && dec_insn.micro_mips_mode)
  933. unreachable();
  934. /* XXX NEC Vr54xx bug workaround */
  935. if (delay_slot(xcp)) {
  936. if (dec_insn.micro_mips_mode) {
  937. if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
  938. clear_delay_slot(xcp);
  939. } else {
  940. if (!isBranchInstr(xcp, dec_insn, &contpc))
  941. clear_delay_slot(xcp);
  942. }
  943. }
  944. if (delay_slot(xcp)) {
  945. /*
  946. * The instruction to be emulated is in a branch delay slot
  947. * which means that we have to emulate the branch instruction
  948. * BEFORE we do the cop1 instruction.
  949. *
  950. * This branch could be a COP1 branch, but in that case we
  951. * would have had a trap for that instruction, and would not
  952. * come through this route.
  953. *
  954. * Linux MIPS branch emulator operates on context, updating the
  955. * cp0_epc.
  956. */
  957. ir = dec_insn.next_insn; /* process delay slot instr */
  958. pc_inc = dec_insn.next_pc_inc;
  959. } else {
  960. ir = dec_insn.insn; /* process current instr */
  961. pc_inc = dec_insn.pc_inc;
  962. }
  963. /*
  964. * Since microMIPS FPU instructios are a subset of MIPS32 FPU
  965. * instructions, we want to convert microMIPS FPU instructions
  966. * into MIPS32 instructions so that we could reuse all of the
  967. * FPU emulation code.
  968. *
  969. * NOTE: We cannot do this for branch instructions since they
  970. * are not a subset. Example: Cannot emulate a 16-bit
  971. * aligned target address with a MIPS32 instruction.
  972. */
  973. if (dec_insn.micro_mips_mode) {
  974. /*
  975. * If next instruction is a 16-bit instruction, then it
  976. * it cannot be a FPU instruction. This could happen
  977. * since we can be called for non-FPU instructions.
  978. */
  979. if ((pc_inc == 2) ||
  980. (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
  981. == SIGILL))
  982. return SIGILL;
  983. }
  984. emul:
  985. perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
  986. MIPS_FPU_EMU_INC_STATS(emulated);
  987. switch (MIPSInst_OPCODE(ir)) {
  988. case ldc1_op:
  989. dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
  990. MIPSInst_SIMM(ir));
  991. MIPS_FPU_EMU_INC_STATS(loads);
  992. if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
  993. MIPS_FPU_EMU_INC_STATS(errors);
  994. *fault_addr = dva;
  995. return SIGBUS;
  996. }
  997. if (__get_user(dval, dva)) {
  998. MIPS_FPU_EMU_INC_STATS(errors);
  999. *fault_addr = dva;
  1000. return SIGSEGV;
  1001. }
  1002. DITOREG(dval, MIPSInst_RT(ir));
  1003. break;
  1004. case sdc1_op:
  1005. dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
  1006. MIPSInst_SIMM(ir));
  1007. MIPS_FPU_EMU_INC_STATS(stores);
  1008. DIFROMREG(dval, MIPSInst_RT(ir));
  1009. if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
  1010. MIPS_FPU_EMU_INC_STATS(errors);
  1011. *fault_addr = dva;
  1012. return SIGBUS;
  1013. }
  1014. if (__put_user(dval, dva)) {
  1015. MIPS_FPU_EMU_INC_STATS(errors);
  1016. *fault_addr = dva;
  1017. return SIGSEGV;
  1018. }
  1019. break;
  1020. case lwc1_op:
  1021. wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
  1022. MIPSInst_SIMM(ir));
  1023. MIPS_FPU_EMU_INC_STATS(loads);
  1024. if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
  1025. MIPS_FPU_EMU_INC_STATS(errors);
  1026. *fault_addr = wva;
  1027. return SIGBUS;
  1028. }
  1029. if (__get_user(wval, wva)) {
  1030. MIPS_FPU_EMU_INC_STATS(errors);
  1031. *fault_addr = wva;
  1032. return SIGSEGV;
  1033. }
  1034. SITOREG(wval, MIPSInst_RT(ir));
  1035. break;
  1036. case swc1_op:
  1037. wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
  1038. MIPSInst_SIMM(ir));
  1039. MIPS_FPU_EMU_INC_STATS(stores);
  1040. SIFROMREG(wval, MIPSInst_RT(ir));
  1041. if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
  1042. MIPS_FPU_EMU_INC_STATS(errors);
  1043. *fault_addr = wva;
  1044. return SIGBUS;
  1045. }
  1046. if (__put_user(wval, wva)) {
  1047. MIPS_FPU_EMU_INC_STATS(errors);
  1048. *fault_addr = wva;
  1049. return SIGSEGV;
  1050. }
  1051. break;
  1052. case cop1_op:
  1053. switch (MIPSInst_RS(ir)) {
  1054. case dmfc_op:
  1055. if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
  1056. return SIGILL;
  1057. /* copregister fs -> gpr[rt] */
  1058. if (MIPSInst_RT(ir) != 0) {
  1059. DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
  1060. MIPSInst_RD(ir));
  1061. }
  1062. break;
  1063. case dmtc_op:
  1064. if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
  1065. return SIGILL;
  1066. /* copregister fs <- rt */
  1067. DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
  1068. break;
  1069. case mfhc_op:
  1070. if (!cpu_has_mips_r2_r6)
  1071. goto sigill;
  1072. /* copregister rd -> gpr[rt] */
  1073. if (MIPSInst_RT(ir) != 0) {
  1074. SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
  1075. MIPSInst_RD(ir));
  1076. }
  1077. break;
  1078. case mthc_op:
  1079. if (!cpu_has_mips_r2_r6)
  1080. goto sigill;
  1081. /* copregister rd <- gpr[rt] */
  1082. SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
  1083. break;
  1084. case mfc_op:
  1085. /* copregister rd -> gpr[rt] */
  1086. if (MIPSInst_RT(ir) != 0) {
  1087. SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
  1088. MIPSInst_RD(ir));
  1089. }
  1090. break;
  1091. case mtc_op:
  1092. /* copregister rd <- rt */
  1093. SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
  1094. break;
  1095. case cfc_op:
  1096. /* cop control register rd -> gpr[rt] */
  1097. cop1_cfc(xcp, ctx, ir);
  1098. break;
  1099. case ctc_op:
  1100. /* copregister rd <- rt */
  1101. cop1_ctc(xcp, ctx, ir);
  1102. if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
  1103. return SIGFPE;
  1104. }
  1105. break;
  1106. case bc1eqz_op:
  1107. case bc1nez_op:
  1108. if (!cpu_has_mips_r6 || delay_slot(xcp))
  1109. return SIGILL;
  1110. cond = likely = 0;
  1111. fpr = &current->thread.fpu.fpr[MIPSInst_RT(ir)];
  1112. bit0 = get_fpr32(fpr, 0) & 0x1;
  1113. switch (MIPSInst_RS(ir)) {
  1114. case bc1eqz_op:
  1115. cond = bit0 == 0;
  1116. break;
  1117. case bc1nez_op:
  1118. cond = bit0 != 0;
  1119. break;
  1120. }
  1121. goto branch_common;
  1122. case bc_op:
  1123. if (delay_slot(xcp))
  1124. return SIGILL;
  1125. if (cpu_has_mips_4_5_r)
  1126. cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
  1127. else
  1128. cbit = FPU_CSR_COND;
  1129. cond = ctx->fcr31 & cbit;
  1130. likely = 0;
  1131. switch (MIPSInst_RT(ir) & 3) {
  1132. case bcfl_op:
  1133. if (cpu_has_mips_2_3_4_5_r)
  1134. likely = 1;
  1135. /* Fall through */
  1136. case bcf_op:
  1137. cond = !cond;
  1138. break;
  1139. case bctl_op:
  1140. if (cpu_has_mips_2_3_4_5_r)
  1141. likely = 1;
  1142. /* Fall through */
  1143. case bct_op:
  1144. break;
  1145. }
  1146. branch_common:
  1147. set_delay_slot(xcp);
  1148. if (cond) {
  1149. /*
  1150. * Branch taken: emulate dslot instruction
  1151. */
  1152. unsigned long bcpc;
  1153. /*
  1154. * Remember EPC at the branch to point back
  1155. * at so that any delay-slot instruction
  1156. * signal is not silently ignored.
  1157. */
  1158. bcpc = xcp->cp0_epc;
  1159. xcp->cp0_epc += dec_insn.pc_inc;
  1160. contpc = MIPSInst_SIMM(ir);
  1161. ir = dec_insn.next_insn;
  1162. if (dec_insn.micro_mips_mode) {
  1163. contpc = (xcp->cp0_epc + (contpc << 1));
  1164. /* If 16-bit instruction, not FPU. */
  1165. if ((dec_insn.next_pc_inc == 2) ||
  1166. (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
  1167. /*
  1168. * Since this instruction will
  1169. * be put on the stack with
  1170. * 32-bit words, get around
  1171. * this problem by putting a
  1172. * NOP16 as the second one.
  1173. */
  1174. if (dec_insn.next_pc_inc == 2)
  1175. ir = (ir & (~0xffff)) | MM_NOP16;
  1176. /*
  1177. * Single step the non-CP1
  1178. * instruction in the dslot.
  1179. */
  1180. sig = mips_dsemul(xcp, ir,
  1181. bcpc, contpc);
  1182. if (sig < 0)
  1183. break;
  1184. if (sig)
  1185. xcp->cp0_epc = bcpc;
  1186. /*
  1187. * SIGILL forces out of
  1188. * the emulation loop.
  1189. */
  1190. return sig ? sig : SIGILL;
  1191. }
  1192. } else
  1193. contpc = (xcp->cp0_epc + (contpc << 2));
  1194. switch (MIPSInst_OPCODE(ir)) {
  1195. case lwc1_op:
  1196. case swc1_op:
  1197. goto emul;
  1198. case ldc1_op:
  1199. case sdc1_op:
  1200. if (cpu_has_mips_2_3_4_5_r)
  1201. goto emul;
  1202. goto bc_sigill;
  1203. case cop1_op:
  1204. goto emul;
  1205. case cop1x_op:
  1206. if (cpu_has_mips_4_5_64_r2_r6)
  1207. /* its one of ours */
  1208. goto emul;
  1209. goto bc_sigill;
  1210. case spec_op:
  1211. switch (MIPSInst_FUNC(ir)) {
  1212. case movc_op:
  1213. if (cpu_has_mips_4_5_r)
  1214. goto emul;
  1215. goto bc_sigill;
  1216. }
  1217. break;
  1218. bc_sigill:
  1219. xcp->cp0_epc = bcpc;
  1220. return SIGILL;
  1221. }
  1222. /*
  1223. * Single step the non-cp1
  1224. * instruction in the dslot
  1225. */
  1226. sig = mips_dsemul(xcp, ir, bcpc, contpc);
  1227. if (sig < 0)
  1228. break;
  1229. if (sig)
  1230. xcp->cp0_epc = bcpc;
  1231. /* SIGILL forces out of the emulation loop. */
  1232. return sig ? sig : SIGILL;
  1233. } else if (likely) { /* branch not taken */
  1234. /*
  1235. * branch likely nullifies
  1236. * dslot if not taken
  1237. */
  1238. xcp->cp0_epc += dec_insn.pc_inc;
  1239. contpc += dec_insn.pc_inc;
  1240. /*
  1241. * else continue & execute
  1242. * dslot as normal insn
  1243. */
  1244. }
  1245. break;
  1246. default:
  1247. if (!(MIPSInst_RS(ir) & 0x10))
  1248. return SIGILL;
  1249. /* a real fpu computation instruction */
  1250. if ((sig = fpu_emu(xcp, ctx, ir)))
  1251. return sig;
  1252. }
  1253. break;
  1254. case cop1x_op:
  1255. if (!cpu_has_mips_4_5_64_r2_r6)
  1256. return SIGILL;
  1257. sig = fpux_emu(xcp, ctx, ir, fault_addr);
  1258. if (sig)
  1259. return sig;
  1260. break;
  1261. case spec_op:
  1262. if (!cpu_has_mips_4_5_r)
  1263. return SIGILL;
  1264. if (MIPSInst_FUNC(ir) != movc_op)
  1265. return SIGILL;
  1266. cond = fpucondbit[MIPSInst_RT(ir) >> 2];
  1267. if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
  1268. xcp->regs[MIPSInst_RD(ir)] =
  1269. xcp->regs[MIPSInst_RS(ir)];
  1270. break;
  1271. default:
  1272. sigill:
  1273. return SIGILL;
  1274. }
  1275. /* we did it !! */
  1276. xcp->cp0_epc = contpc;
  1277. clear_delay_slot(xcp);
  1278. return 0;
  1279. }
  1280. /*
  1281. * Conversion table from MIPS compare ops 48-63
  1282. * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
  1283. */
  1284. static const unsigned char cmptab[8] = {
  1285. 0, /* cmp_0 (sig) cmp_sf */
  1286. IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
  1287. IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
  1288. IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
  1289. IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
  1290. IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
  1291. IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
  1292. IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
  1293. };
  1294. static const unsigned char negative_cmptab[8] = {
  1295. 0, /* Reserved */
  1296. IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
  1297. IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
  1298. IEEE754_CLT | IEEE754_CGT,
  1299. /* Reserved */
  1300. };
  1301. /*
  1302. * Additional MIPS4 instructions
  1303. */
  1304. #define DEF3OP(name, p, f1, f2, f3) \
  1305. static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
  1306. union ieee754##p s, union ieee754##p t) \
  1307. { \
  1308. struct _ieee754_csr ieee754_csr_save; \
  1309. s = f1(s, t); \
  1310. ieee754_csr_save = ieee754_csr; \
  1311. s = f2(s, r); \
  1312. ieee754_csr_save.cx |= ieee754_csr.cx; \
  1313. ieee754_csr_save.sx |= ieee754_csr.sx; \
  1314. s = f3(s); \
  1315. ieee754_csr.cx |= ieee754_csr_save.cx; \
  1316. ieee754_csr.sx |= ieee754_csr_save.sx; \
  1317. return s; \
  1318. }
  1319. static union ieee754dp fpemu_dp_recip(union ieee754dp d)
  1320. {
  1321. return ieee754dp_div(ieee754dp_one(0), d);
  1322. }
  1323. static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
  1324. {
  1325. return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
  1326. }
  1327. static union ieee754sp fpemu_sp_recip(union ieee754sp s)
  1328. {
  1329. return ieee754sp_div(ieee754sp_one(0), s);
  1330. }
  1331. static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
  1332. {
  1333. return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
  1334. }
  1335. DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
  1336. DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
  1337. DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
  1338. DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
  1339. DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
  1340. DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
  1341. DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
  1342. DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
  1343. static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
  1344. mips_instruction ir, void *__user *fault_addr)
  1345. {
  1346. unsigned rcsr = 0; /* resulting csr */
  1347. MIPS_FPU_EMU_INC_STATS(cp1xops);
  1348. switch (MIPSInst_FMA_FFMT(ir)) {
  1349. case s_fmt:{ /* 0 */
  1350. union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
  1351. union ieee754sp fd, fr, fs, ft;
  1352. u32 __user *va;
  1353. u32 val;
  1354. switch (MIPSInst_FUNC(ir)) {
  1355. case lwxc1_op:
  1356. va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
  1357. xcp->regs[MIPSInst_FT(ir)]);
  1358. MIPS_FPU_EMU_INC_STATS(loads);
  1359. if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
  1360. MIPS_FPU_EMU_INC_STATS(errors);
  1361. *fault_addr = va;
  1362. return SIGBUS;
  1363. }
  1364. if (__get_user(val, va)) {
  1365. MIPS_FPU_EMU_INC_STATS(errors);
  1366. *fault_addr = va;
  1367. return SIGSEGV;
  1368. }
  1369. SITOREG(val, MIPSInst_FD(ir));
  1370. break;
  1371. case swxc1_op:
  1372. va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
  1373. xcp->regs[MIPSInst_FT(ir)]);
  1374. MIPS_FPU_EMU_INC_STATS(stores);
  1375. SIFROMREG(val, MIPSInst_FS(ir));
  1376. if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
  1377. MIPS_FPU_EMU_INC_STATS(errors);
  1378. *fault_addr = va;
  1379. return SIGBUS;
  1380. }
  1381. if (put_user(val, va)) {
  1382. MIPS_FPU_EMU_INC_STATS(errors);
  1383. *fault_addr = va;
  1384. return SIGSEGV;
  1385. }
  1386. break;
  1387. case madd_s_op:
  1388. handler = fpemu_sp_madd;
  1389. goto scoptop;
  1390. case msub_s_op:
  1391. handler = fpemu_sp_msub;
  1392. goto scoptop;
  1393. case nmadd_s_op:
  1394. handler = fpemu_sp_nmadd;
  1395. goto scoptop;
  1396. case nmsub_s_op:
  1397. handler = fpemu_sp_nmsub;
  1398. goto scoptop;
  1399. scoptop:
  1400. SPFROMREG(fr, MIPSInst_FR(ir));
  1401. SPFROMREG(fs, MIPSInst_FS(ir));
  1402. SPFROMREG(ft, MIPSInst_FT(ir));
  1403. fd = (*handler) (fr, fs, ft);
  1404. SPTOREG(fd, MIPSInst_FD(ir));
  1405. copcsr:
  1406. if (ieee754_cxtest(IEEE754_INEXACT)) {
  1407. MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
  1408. rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
  1409. }
  1410. if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
  1411. MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
  1412. rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
  1413. }
  1414. if (ieee754_cxtest(IEEE754_OVERFLOW)) {
  1415. MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
  1416. rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
  1417. }
  1418. if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
  1419. MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
  1420. rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
  1421. }
  1422. ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
  1423. if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
  1424. /*printk ("SIGFPE: FPU csr = %08x\n",
  1425. ctx->fcr31); */
  1426. return SIGFPE;
  1427. }
  1428. break;
  1429. default:
  1430. return SIGILL;
  1431. }
  1432. break;
  1433. }
  1434. case d_fmt:{ /* 1 */
  1435. union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
  1436. union ieee754dp fd, fr, fs, ft;
  1437. u64 __user *va;
  1438. u64 val;
  1439. switch (MIPSInst_FUNC(ir)) {
  1440. case ldxc1_op:
  1441. va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
  1442. xcp->regs[MIPSInst_FT(ir)]);
  1443. MIPS_FPU_EMU_INC_STATS(loads);
  1444. if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
  1445. MIPS_FPU_EMU_INC_STATS(errors);
  1446. *fault_addr = va;
  1447. return SIGBUS;
  1448. }
  1449. if (__get_user(val, va)) {
  1450. MIPS_FPU_EMU_INC_STATS(errors);
  1451. *fault_addr = va;
  1452. return SIGSEGV;
  1453. }
  1454. DITOREG(val, MIPSInst_FD(ir));
  1455. break;
  1456. case sdxc1_op:
  1457. va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
  1458. xcp->regs[MIPSInst_FT(ir)]);
  1459. MIPS_FPU_EMU_INC_STATS(stores);
  1460. DIFROMREG(val, MIPSInst_FS(ir));
  1461. if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
  1462. MIPS_FPU_EMU_INC_STATS(errors);
  1463. *fault_addr = va;
  1464. return SIGBUS;
  1465. }
  1466. if (__put_user(val, va)) {
  1467. MIPS_FPU_EMU_INC_STATS(errors);
  1468. *fault_addr = va;
  1469. return SIGSEGV;
  1470. }
  1471. break;
  1472. case madd_d_op:
  1473. handler = fpemu_dp_madd;
  1474. goto dcoptop;
  1475. case msub_d_op:
  1476. handler = fpemu_dp_msub;
  1477. goto dcoptop;
  1478. case nmadd_d_op:
  1479. handler = fpemu_dp_nmadd;
  1480. goto dcoptop;
  1481. case nmsub_d_op:
  1482. handler = fpemu_dp_nmsub;
  1483. goto dcoptop;
  1484. dcoptop:
  1485. DPFROMREG(fr, MIPSInst_FR(ir));
  1486. DPFROMREG(fs, MIPSInst_FS(ir));
  1487. DPFROMREG(ft, MIPSInst_FT(ir));
  1488. fd = (*handler) (fr, fs, ft);
  1489. DPTOREG(fd, MIPSInst_FD(ir));
  1490. goto copcsr;
  1491. default:
  1492. return SIGILL;
  1493. }
  1494. break;
  1495. }
  1496. case 0x3:
  1497. if (MIPSInst_FUNC(ir) != pfetch_op)
  1498. return SIGILL;
  1499. /* ignore prefx operation */
  1500. break;
  1501. default:
  1502. return SIGILL;
  1503. }
  1504. return 0;
  1505. }
  1506. /*
  1507. * Emulate a single COP1 arithmetic instruction.
  1508. */
  1509. static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
  1510. mips_instruction ir)
  1511. {
  1512. int rfmt; /* resulting format */
  1513. unsigned rcsr = 0; /* resulting csr */
  1514. unsigned int oldrm;
  1515. unsigned int cbit;
  1516. unsigned cond;
  1517. union {
  1518. union ieee754dp d;
  1519. union ieee754sp s;
  1520. int w;
  1521. s64 l;
  1522. } rv; /* resulting value */
  1523. u64 bits;
  1524. MIPS_FPU_EMU_INC_STATS(cp1ops);
  1525. switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
  1526. case s_fmt: { /* 0 */
  1527. union {
  1528. union ieee754sp(*b) (union ieee754sp, union ieee754sp);
  1529. union ieee754sp(*u) (union ieee754sp);
  1530. } handler;
  1531. union ieee754sp fd, fs, ft;
  1532. switch (MIPSInst_FUNC(ir)) {
  1533. /* binary ops */
  1534. case fadd_op:
  1535. handler.b = ieee754sp_add;
  1536. goto scopbop;
  1537. case fsub_op:
  1538. handler.b = ieee754sp_sub;
  1539. goto scopbop;
  1540. case fmul_op:
  1541. handler.b = ieee754sp_mul;
  1542. goto scopbop;
  1543. case fdiv_op:
  1544. handler.b = ieee754sp_div;
  1545. goto scopbop;
  1546. /* unary ops */
  1547. case fsqrt_op:
  1548. if (!cpu_has_mips_2_3_4_5_r)
  1549. return SIGILL;
  1550. handler.u = ieee754sp_sqrt;
  1551. goto scopuop;
  1552. /*
  1553. * Note that on some MIPS IV implementations such as the
  1554. * R5000 and R8000 the FSQRT and FRECIP instructions do not
  1555. * achieve full IEEE-754 accuracy - however this emulator does.
  1556. */
  1557. case frsqrt_op:
  1558. if (!cpu_has_mips_4_5_64_r2_r6)
  1559. return SIGILL;
  1560. handler.u = fpemu_sp_rsqrt;
  1561. goto scopuop;
  1562. case frecip_op:
  1563. if (!cpu_has_mips_4_5_64_r2_r6)
  1564. return SIGILL;
  1565. handler.u = fpemu_sp_recip;
  1566. goto scopuop;
  1567. case fmovc_op:
  1568. if (!cpu_has_mips_4_5_r)
  1569. return SIGILL;
  1570. cond = fpucondbit[MIPSInst_FT(ir) >> 2];
  1571. if (((ctx->fcr31 & cond) != 0) !=
  1572. ((MIPSInst_FT(ir) & 1) != 0))
  1573. return 0;
  1574. SPFROMREG(rv.s, MIPSInst_FS(ir));
  1575. break;
  1576. case fmovz_op:
  1577. if (!cpu_has_mips_4_5_r)
  1578. return SIGILL;
  1579. if (xcp->regs[MIPSInst_FT(ir)] != 0)
  1580. return 0;
  1581. SPFROMREG(rv.s, MIPSInst_FS(ir));
  1582. break;
  1583. case fmovn_op:
  1584. if (!cpu_has_mips_4_5_r)
  1585. return SIGILL;
  1586. if (xcp->regs[MIPSInst_FT(ir)] == 0)
  1587. return 0;
  1588. SPFROMREG(rv.s, MIPSInst_FS(ir));
  1589. break;
  1590. case fseleqz_op:
  1591. if (!cpu_has_mips_r6)
  1592. return SIGILL;
  1593. SPFROMREG(rv.s, MIPSInst_FT(ir));
  1594. if (rv.w & 0x1)
  1595. rv.w = 0;
  1596. else
  1597. SPFROMREG(rv.s, MIPSInst_FS(ir));
  1598. break;
  1599. case fselnez_op:
  1600. if (!cpu_has_mips_r6)
  1601. return SIGILL;
  1602. SPFROMREG(rv.s, MIPSInst_FT(ir));
  1603. if (rv.w & 0x1)
  1604. SPFROMREG(rv.s, MIPSInst_FS(ir));
  1605. else
  1606. rv.w = 0;
  1607. break;
  1608. case fmaddf_op: {
  1609. union ieee754sp ft, fs, fd;
  1610. if (!cpu_has_mips_r6)
  1611. return SIGILL;
  1612. SPFROMREG(ft, MIPSInst_FT(ir));
  1613. SPFROMREG(fs, MIPSInst_FS(ir));
  1614. SPFROMREG(fd, MIPSInst_FD(ir));
  1615. rv.s = ieee754sp_maddf(fd, fs, ft);
  1616. goto copcsr;
  1617. }
  1618. case fmsubf_op: {
  1619. union ieee754sp ft, fs, fd;
  1620. if (!cpu_has_mips_r6)
  1621. return SIGILL;
  1622. SPFROMREG(ft, MIPSInst_FT(ir));
  1623. SPFROMREG(fs, MIPSInst_FS(ir));
  1624. SPFROMREG(fd, MIPSInst_FD(ir));
  1625. rv.s = ieee754sp_msubf(fd, fs, ft);
  1626. goto copcsr;
  1627. }
  1628. case frint_op: {
  1629. union ieee754sp fs;
  1630. if (!cpu_has_mips_r6)
  1631. return SIGILL;
  1632. SPFROMREG(fs, MIPSInst_FS(ir));
  1633. rv.l = ieee754sp_tlong(fs);
  1634. rv.s = ieee754sp_flong(rv.l);
  1635. goto copcsr;
  1636. }
  1637. case fclass_op: {
  1638. union ieee754sp fs;
  1639. if (!cpu_has_mips_r6)
  1640. return SIGILL;
  1641. SPFROMREG(fs, MIPSInst_FS(ir));
  1642. rv.w = ieee754sp_2008class(fs);
  1643. rfmt = w_fmt;
  1644. goto copcsr;
  1645. }
  1646. case fmin_op: {
  1647. union ieee754sp fs, ft;
  1648. if (!cpu_has_mips_r6)
  1649. return SIGILL;
  1650. SPFROMREG(ft, MIPSInst_FT(ir));
  1651. SPFROMREG(fs, MIPSInst_FS(ir));
  1652. rv.s = ieee754sp_fmin(fs, ft);
  1653. goto copcsr;
  1654. }
  1655. case fmina_op: {
  1656. union ieee754sp fs, ft;
  1657. if (!cpu_has_mips_r6)
  1658. return SIGILL;
  1659. SPFROMREG(ft, MIPSInst_FT(ir));
  1660. SPFROMREG(fs, MIPSInst_FS(ir));
  1661. rv.s = ieee754sp_fmina(fs, ft);
  1662. goto copcsr;
  1663. }
  1664. case fmax_op: {
  1665. union ieee754sp fs, ft;
  1666. if (!cpu_has_mips_r6)
  1667. return SIGILL;
  1668. SPFROMREG(ft, MIPSInst_FT(ir));
  1669. SPFROMREG(fs, MIPSInst_FS(ir));
  1670. rv.s = ieee754sp_fmax(fs, ft);
  1671. goto copcsr;
  1672. }
  1673. case fmaxa_op: {
  1674. union ieee754sp fs, ft;
  1675. if (!cpu_has_mips_r6)
  1676. return SIGILL;
  1677. SPFROMREG(ft, MIPSInst_FT(ir));
  1678. SPFROMREG(fs, MIPSInst_FS(ir));
  1679. rv.s = ieee754sp_fmaxa(fs, ft);
  1680. goto copcsr;
  1681. }
  1682. case fabs_op:
  1683. handler.u = ieee754sp_abs;
  1684. goto scopuop;
  1685. case fneg_op:
  1686. handler.u = ieee754sp_neg;
  1687. goto scopuop;
  1688. case fmov_op:
  1689. /* an easy one */
  1690. SPFROMREG(rv.s, MIPSInst_FS(ir));
  1691. goto copcsr;
  1692. /* binary op on handler */
  1693. scopbop:
  1694. SPFROMREG(fs, MIPSInst_FS(ir));
  1695. SPFROMREG(ft, MIPSInst_FT(ir));
  1696. rv.s = (*handler.b) (fs, ft);
  1697. goto copcsr;
  1698. scopuop:
  1699. SPFROMREG(fs, MIPSInst_FS(ir));
  1700. rv.s = (*handler.u) (fs);
  1701. goto copcsr;
  1702. copcsr:
  1703. if (ieee754_cxtest(IEEE754_INEXACT)) {
  1704. MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
  1705. rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
  1706. }
  1707. if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
  1708. MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
  1709. rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
  1710. }
  1711. if (ieee754_cxtest(IEEE754_OVERFLOW)) {
  1712. MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
  1713. rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
  1714. }
  1715. if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
  1716. MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
  1717. rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
  1718. }
  1719. if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
  1720. MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
  1721. rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
  1722. }
  1723. break;
  1724. /* unary conv ops */
  1725. case fcvts_op:
  1726. return SIGILL; /* not defined */
  1727. case fcvtd_op:
  1728. SPFROMREG(fs, MIPSInst_FS(ir));
  1729. rv.d = ieee754dp_fsp(fs);
  1730. rfmt = d_fmt;
  1731. goto copcsr;
  1732. case fcvtw_op:
  1733. SPFROMREG(fs, MIPSInst_FS(ir));
  1734. rv.w = ieee754sp_tint(fs);
  1735. rfmt = w_fmt;
  1736. goto copcsr;
  1737. case fround_op:
  1738. case ftrunc_op:
  1739. case fceil_op:
  1740. case ffloor_op:
  1741. if (!cpu_has_mips_2_3_4_5_r)
  1742. return SIGILL;
  1743. oldrm = ieee754_csr.rm;
  1744. SPFROMREG(fs, MIPSInst_FS(ir));
  1745. ieee754_csr.rm = MIPSInst_FUNC(ir);
  1746. rv.w = ieee754sp_tint(fs);
  1747. ieee754_csr.rm = oldrm;
  1748. rfmt = w_fmt;
  1749. goto copcsr;
  1750. case fsel_op:
  1751. if (!cpu_has_mips_r6)
  1752. return SIGILL;
  1753. SPFROMREG(fd, MIPSInst_FD(ir));
  1754. if (fd.bits & 0x1)
  1755. SPFROMREG(rv.s, MIPSInst_FT(ir));
  1756. else
  1757. SPFROMREG(rv.s, MIPSInst_FS(ir));
  1758. break;
  1759. case fcvtl_op:
  1760. if (!cpu_has_mips_3_4_5_64_r2_r6)
  1761. return SIGILL;
  1762. SPFROMREG(fs, MIPSInst_FS(ir));
  1763. rv.l = ieee754sp_tlong(fs);
  1764. rfmt = l_fmt;
  1765. goto copcsr;
  1766. case froundl_op:
  1767. case ftruncl_op:
  1768. case fceill_op:
  1769. case ffloorl_op:
  1770. if (!cpu_has_mips_3_4_5_64_r2_r6)
  1771. return SIGILL;
  1772. oldrm = ieee754_csr.rm;
  1773. SPFROMREG(fs, MIPSInst_FS(ir));
  1774. ieee754_csr.rm = MIPSInst_FUNC(ir);
  1775. rv.l = ieee754sp_tlong(fs);
  1776. ieee754_csr.rm = oldrm;
  1777. rfmt = l_fmt;
  1778. goto copcsr;
  1779. default:
  1780. if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
  1781. unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
  1782. union ieee754sp fs, ft;
  1783. SPFROMREG(fs, MIPSInst_FS(ir));
  1784. SPFROMREG(ft, MIPSInst_FT(ir));
  1785. rv.w = ieee754sp_cmp(fs, ft,
  1786. cmptab[cmpop & 0x7], cmpop & 0x8);
  1787. rfmt = -1;
  1788. if ((cmpop & 0x8) && ieee754_cxtest
  1789. (IEEE754_INVALID_OPERATION))
  1790. rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
  1791. else
  1792. goto copcsr;
  1793. } else
  1794. return SIGILL;
  1795. break;
  1796. }
  1797. break;
  1798. }
  1799. case d_fmt: {
  1800. union ieee754dp fd, fs, ft;
  1801. union {
  1802. union ieee754dp(*b) (union ieee754dp, union ieee754dp);
  1803. union ieee754dp(*u) (union ieee754dp);
  1804. } handler;
  1805. switch (MIPSInst_FUNC(ir)) {
  1806. /* binary ops */
  1807. case fadd_op:
  1808. handler.b = ieee754dp_add;
  1809. goto dcopbop;
  1810. case fsub_op:
  1811. handler.b = ieee754dp_sub;
  1812. goto dcopbop;
  1813. case fmul_op:
  1814. handler.b = ieee754dp_mul;
  1815. goto dcopbop;
  1816. case fdiv_op:
  1817. handler.b = ieee754dp_div;
  1818. goto dcopbop;
  1819. /* unary ops */
  1820. case fsqrt_op:
  1821. if (!cpu_has_mips_2_3_4_5_r)
  1822. return SIGILL;
  1823. handler.u = ieee754dp_sqrt;
  1824. goto dcopuop;
  1825. /*
  1826. * Note that on some MIPS IV implementations such as the
  1827. * R5000 and R8000 the FSQRT and FRECIP instructions do not
  1828. * achieve full IEEE-754 accuracy - however this emulator does.
  1829. */
  1830. case frsqrt_op:
  1831. if (!cpu_has_mips_4_5_64_r2_r6)
  1832. return SIGILL;
  1833. handler.u = fpemu_dp_rsqrt;
  1834. goto dcopuop;
  1835. case frecip_op:
  1836. if (!cpu_has_mips_4_5_64_r2_r6)
  1837. return SIGILL;
  1838. handler.u = fpemu_dp_recip;
  1839. goto dcopuop;
  1840. case fmovc_op:
  1841. if (!cpu_has_mips_4_5_r)
  1842. return SIGILL;
  1843. cond = fpucondbit[MIPSInst_FT(ir) >> 2];
  1844. if (((ctx->fcr31 & cond) != 0) !=
  1845. ((MIPSInst_FT(ir) & 1) != 0))
  1846. return 0;
  1847. DPFROMREG(rv.d, MIPSInst_FS(ir));
  1848. break;
  1849. case fmovz_op:
  1850. if (!cpu_has_mips_4_5_r)
  1851. return SIGILL;
  1852. if (xcp->regs[MIPSInst_FT(ir)] != 0)
  1853. return 0;
  1854. DPFROMREG(rv.d, MIPSInst_FS(ir));
  1855. break;
  1856. case fmovn_op:
  1857. if (!cpu_has_mips_4_5_r)
  1858. return SIGILL;
  1859. if (xcp->regs[MIPSInst_FT(ir)] == 0)
  1860. return 0;
  1861. DPFROMREG(rv.d, MIPSInst_FS(ir));
  1862. break;
  1863. case fseleqz_op:
  1864. if (!cpu_has_mips_r6)
  1865. return SIGILL;
  1866. DPFROMREG(rv.d, MIPSInst_FT(ir));
  1867. if (rv.l & 0x1)
  1868. rv.l = 0;
  1869. else
  1870. DPFROMREG(rv.d, MIPSInst_FS(ir));
  1871. break;
  1872. case fselnez_op:
  1873. if (!cpu_has_mips_r6)
  1874. return SIGILL;
  1875. DPFROMREG(rv.d, MIPSInst_FT(ir));
  1876. if (rv.l & 0x1)
  1877. DPFROMREG(rv.d, MIPSInst_FS(ir));
  1878. else
  1879. rv.l = 0;
  1880. break;
  1881. case fmaddf_op: {
  1882. union ieee754dp ft, fs, fd;
  1883. if (!cpu_has_mips_r6)
  1884. return SIGILL;
  1885. DPFROMREG(ft, MIPSInst_FT(ir));
  1886. DPFROMREG(fs, MIPSInst_FS(ir));
  1887. DPFROMREG(fd, MIPSInst_FD(ir));
  1888. rv.d = ieee754dp_maddf(fd, fs, ft);
  1889. goto copcsr;
  1890. }
  1891. case fmsubf_op: {
  1892. union ieee754dp ft, fs, fd;
  1893. if (!cpu_has_mips_r6)
  1894. return SIGILL;
  1895. DPFROMREG(ft, MIPSInst_FT(ir));
  1896. DPFROMREG(fs, MIPSInst_FS(ir));
  1897. DPFROMREG(fd, MIPSInst_FD(ir));
  1898. rv.d = ieee754dp_msubf(fd, fs, ft);
  1899. goto copcsr;
  1900. }
  1901. case frint_op: {
  1902. union ieee754dp fs;
  1903. if (!cpu_has_mips_r6)
  1904. return SIGILL;
  1905. DPFROMREG(fs, MIPSInst_FS(ir));
  1906. rv.l = ieee754dp_tlong(fs);
  1907. rv.d = ieee754dp_flong(rv.l);
  1908. goto copcsr;
  1909. }
  1910. case fclass_op: {
  1911. union ieee754dp fs;
  1912. if (!cpu_has_mips_r6)
  1913. return SIGILL;
  1914. DPFROMREG(fs, MIPSInst_FS(ir));
  1915. rv.w = ieee754dp_2008class(fs);
  1916. rfmt = w_fmt;
  1917. goto copcsr;
  1918. }
  1919. case fmin_op: {
  1920. union ieee754dp fs, ft;
  1921. if (!cpu_has_mips_r6)
  1922. return SIGILL;
  1923. DPFROMREG(ft, MIPSInst_FT(ir));
  1924. DPFROMREG(fs, MIPSInst_FS(ir));
  1925. rv.d = ieee754dp_fmin(fs, ft);
  1926. goto copcsr;
  1927. }
  1928. case fmina_op: {
  1929. union ieee754dp fs, ft;
  1930. if (!cpu_has_mips_r6)
  1931. return SIGILL;
  1932. DPFROMREG(ft, MIPSInst_FT(ir));
  1933. DPFROMREG(fs, MIPSInst_FS(ir));
  1934. rv.d = ieee754dp_fmina(fs, ft);
  1935. goto copcsr;
  1936. }
  1937. case fmax_op: {
  1938. union ieee754dp fs, ft;
  1939. if (!cpu_has_mips_r6)
  1940. return SIGILL;
  1941. DPFROMREG(ft, MIPSInst_FT(ir));
  1942. DPFROMREG(fs, MIPSInst_FS(ir));
  1943. rv.d = ieee754dp_fmax(fs, ft);
  1944. goto copcsr;
  1945. }
  1946. case fmaxa_op: {
  1947. union ieee754dp fs, ft;
  1948. if (!cpu_has_mips_r6)
  1949. return SIGILL;
  1950. DPFROMREG(ft, MIPSInst_FT(ir));
  1951. DPFROMREG(fs, MIPSInst_FS(ir));
  1952. rv.d = ieee754dp_fmaxa(fs, ft);
  1953. goto copcsr;
  1954. }
  1955. case fabs_op:
  1956. handler.u = ieee754dp_abs;
  1957. goto dcopuop;
  1958. case fneg_op:
  1959. handler.u = ieee754dp_neg;
  1960. goto dcopuop;
  1961. case fmov_op:
  1962. /* an easy one */
  1963. DPFROMREG(rv.d, MIPSInst_FS(ir));
  1964. goto copcsr;
  1965. /* binary op on handler */
  1966. dcopbop:
  1967. DPFROMREG(fs, MIPSInst_FS(ir));
  1968. DPFROMREG(ft, MIPSInst_FT(ir));
  1969. rv.d = (*handler.b) (fs, ft);
  1970. goto copcsr;
  1971. dcopuop:
  1972. DPFROMREG(fs, MIPSInst_FS(ir));
  1973. rv.d = (*handler.u) (fs);
  1974. goto copcsr;
  1975. /*
  1976. * unary conv ops
  1977. */
  1978. case fcvts_op:
  1979. DPFROMREG(fs, MIPSInst_FS(ir));
  1980. rv.s = ieee754sp_fdp(fs);
  1981. rfmt = s_fmt;
  1982. goto copcsr;
  1983. case fcvtd_op:
  1984. return SIGILL; /* not defined */
  1985. case fcvtw_op:
  1986. DPFROMREG(fs, MIPSInst_FS(ir));
  1987. rv.w = ieee754dp_tint(fs); /* wrong */
  1988. rfmt = w_fmt;
  1989. goto copcsr;
  1990. case fround_op:
  1991. case ftrunc_op:
  1992. case fceil_op:
  1993. case ffloor_op:
  1994. if (!cpu_has_mips_2_3_4_5_r)
  1995. return SIGILL;
  1996. oldrm = ieee754_csr.rm;
  1997. DPFROMREG(fs, MIPSInst_FS(ir));
  1998. ieee754_csr.rm = MIPSInst_FUNC(ir);
  1999. rv.w = ieee754dp_tint(fs);
  2000. ieee754_csr.rm = oldrm;
  2001. rfmt = w_fmt;
  2002. goto copcsr;
  2003. case fsel_op:
  2004. if (!cpu_has_mips_r6)
  2005. return SIGILL;
  2006. DPFROMREG(fd, MIPSInst_FD(ir));
  2007. if (fd.bits & 0x1)
  2008. DPFROMREG(rv.d, MIPSInst_FT(ir));
  2009. else
  2010. DPFROMREG(rv.d, MIPSInst_FS(ir));
  2011. break;
  2012. case fcvtl_op:
  2013. if (!cpu_has_mips_3_4_5_64_r2_r6)
  2014. return SIGILL;
  2015. DPFROMREG(fs, MIPSInst_FS(ir));
  2016. rv.l = ieee754dp_tlong(fs);
  2017. rfmt = l_fmt;
  2018. goto copcsr;
  2019. case froundl_op:
  2020. case ftruncl_op:
  2021. case fceill_op:
  2022. case ffloorl_op:
  2023. if (!cpu_has_mips_3_4_5_64_r2_r6)
  2024. return SIGILL;
  2025. oldrm = ieee754_csr.rm;
  2026. DPFROMREG(fs, MIPSInst_FS(ir));
  2027. ieee754_csr.rm = MIPSInst_FUNC(ir);
  2028. rv.l = ieee754dp_tlong(fs);
  2029. ieee754_csr.rm = oldrm;
  2030. rfmt = l_fmt;
  2031. goto copcsr;
  2032. default:
  2033. if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
  2034. unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
  2035. union ieee754dp fs, ft;
  2036. DPFROMREG(fs, MIPSInst_FS(ir));
  2037. DPFROMREG(ft, MIPSInst_FT(ir));
  2038. rv.w = ieee754dp_cmp(fs, ft,
  2039. cmptab[cmpop & 0x7], cmpop & 0x8);
  2040. rfmt = -1;
  2041. if ((cmpop & 0x8)
  2042. &&
  2043. ieee754_cxtest
  2044. (IEEE754_INVALID_OPERATION))
  2045. rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
  2046. else
  2047. goto copcsr;
  2048. }
  2049. else {
  2050. return SIGILL;
  2051. }
  2052. break;
  2053. }
  2054. break;
  2055. }
  2056. case w_fmt: {
  2057. union ieee754dp fs;
  2058. switch (MIPSInst_FUNC(ir)) {
  2059. case fcvts_op:
  2060. /* convert word to single precision real */
  2061. SPFROMREG(fs, MIPSInst_FS(ir));
  2062. rv.s = ieee754sp_fint(fs.bits);
  2063. rfmt = s_fmt;
  2064. goto copcsr;
  2065. case fcvtd_op:
  2066. /* convert word to double precision real */
  2067. SPFROMREG(fs, MIPSInst_FS(ir));
  2068. rv.d = ieee754dp_fint(fs.bits);
  2069. rfmt = d_fmt;
  2070. goto copcsr;
  2071. default: {
  2072. /* Emulating the new CMP.condn.fmt R6 instruction */
  2073. #define CMPOP_MASK 0x7
  2074. #define SIGN_BIT (0x1 << 3)
  2075. #define PREDICATE_BIT (0x1 << 4)
  2076. int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
  2077. int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
  2078. union ieee754sp fs, ft;
  2079. /* This is an R6 only instruction */
  2080. if (!cpu_has_mips_r6 ||
  2081. (MIPSInst_FUNC(ir) & 0x20))
  2082. return SIGILL;
  2083. /* fmt is w_fmt for single precision so fix it */
  2084. rfmt = s_fmt;
  2085. /* default to false */
  2086. rv.w = 0;
  2087. /* CMP.condn.S */
  2088. SPFROMREG(fs, MIPSInst_FS(ir));
  2089. SPFROMREG(ft, MIPSInst_FT(ir));
  2090. /* positive predicates */
  2091. if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
  2092. if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
  2093. sig))
  2094. rv.w = -1; /* true, all 1s */
  2095. if ((sig) &&
  2096. ieee754_cxtest(IEEE754_INVALID_OPERATION))
  2097. rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
  2098. else
  2099. goto copcsr;
  2100. } else {
  2101. /* negative predicates */
  2102. switch (cmpop) {
  2103. case 1:
  2104. case 2:
  2105. case 3:
  2106. if (ieee754sp_cmp(fs, ft,
  2107. negative_cmptab[cmpop],
  2108. sig))
  2109. rv.w = -1; /* true, all 1s */
  2110. if (sig &&
  2111. ieee754_cxtest(IEEE754_INVALID_OPERATION))
  2112. rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
  2113. else
  2114. goto copcsr;
  2115. break;
  2116. default:
  2117. /* Reserved R6 ops */
  2118. return SIGILL;
  2119. }
  2120. }
  2121. break;
  2122. }
  2123. }
  2124. }
  2125. case l_fmt:
  2126. if (!cpu_has_mips_3_4_5_64_r2_r6)
  2127. return SIGILL;
  2128. DIFROMREG(bits, MIPSInst_FS(ir));
  2129. switch (MIPSInst_FUNC(ir)) {
  2130. case fcvts_op:
  2131. /* convert long to single precision real */
  2132. rv.s = ieee754sp_flong(bits);
  2133. rfmt = s_fmt;
  2134. goto copcsr;
  2135. case fcvtd_op:
  2136. /* convert long to double precision real */
  2137. rv.d = ieee754dp_flong(bits);
  2138. rfmt = d_fmt;
  2139. goto copcsr;
  2140. default: {
  2141. /* Emulating the new CMP.condn.fmt R6 instruction */
  2142. int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
  2143. int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
  2144. union ieee754dp fs, ft;
  2145. if (!cpu_has_mips_r6 ||
  2146. (MIPSInst_FUNC(ir) & 0x20))
  2147. return SIGILL;
  2148. /* fmt is l_fmt for double precision so fix it */
  2149. rfmt = d_fmt;
  2150. /* default to false */
  2151. rv.l = 0;
  2152. /* CMP.condn.D */
  2153. DPFROMREG(fs, MIPSInst_FS(ir));
  2154. DPFROMREG(ft, MIPSInst_FT(ir));
  2155. /* positive predicates */
  2156. if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
  2157. if (ieee754dp_cmp(fs, ft,
  2158. cmptab[cmpop], sig))
  2159. rv.l = -1LL; /* true, all 1s */
  2160. if (sig &&
  2161. ieee754_cxtest(IEEE754_INVALID_OPERATION))
  2162. rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
  2163. else
  2164. goto copcsr;
  2165. } else {
  2166. /* negative predicates */
  2167. switch (cmpop) {
  2168. case 1:
  2169. case 2:
  2170. case 3:
  2171. if (ieee754dp_cmp(fs, ft,
  2172. negative_cmptab[cmpop],
  2173. sig))
  2174. rv.l = -1LL; /* true, all 1s */
  2175. if (sig &&
  2176. ieee754_cxtest(IEEE754_INVALID_OPERATION))
  2177. rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
  2178. else
  2179. goto copcsr;
  2180. break;
  2181. default:
  2182. /* Reserved R6 ops */
  2183. return SIGILL;
  2184. }
  2185. }
  2186. break;
  2187. }
  2188. }
  2189. default:
  2190. return SIGILL;
  2191. }
  2192. /*
  2193. * Update the fpu CSR register for this operation.
  2194. * If an exception is required, generate a tidy SIGFPE exception,
  2195. * without updating the result register.
  2196. * Note: cause exception bits do not accumulate, they are rewritten
  2197. * for each op; only the flag/sticky bits accumulate.
  2198. */
  2199. ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
  2200. if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
  2201. /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
  2202. return SIGFPE;
  2203. }
  2204. /*
  2205. * Now we can safely write the result back to the register file.
  2206. */
  2207. switch (rfmt) {
  2208. case -1:
  2209. if (cpu_has_mips_4_5_r)
  2210. cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
  2211. else
  2212. cbit = FPU_CSR_COND;
  2213. if (rv.w)
  2214. ctx->fcr31 |= cbit;
  2215. else
  2216. ctx->fcr31 &= ~cbit;
  2217. break;
  2218. case d_fmt:
  2219. DPTOREG(rv.d, MIPSInst_FD(ir));
  2220. break;
  2221. case s_fmt:
  2222. SPTOREG(rv.s, MIPSInst_FD(ir));
  2223. break;
  2224. case w_fmt:
  2225. SITOREG(rv.w, MIPSInst_FD(ir));
  2226. break;
  2227. case l_fmt:
  2228. if (!cpu_has_mips_3_4_5_64_r2_r6)
  2229. return SIGILL;
  2230. DITOREG(rv.l, MIPSInst_FD(ir));
  2231. break;
  2232. default:
  2233. return SIGILL;
  2234. }
  2235. return 0;
  2236. }
  2237. /*
  2238. * Emulate FPU instructions.
  2239. *
  2240. * If we use FPU hardware, then we have been typically called to handle
  2241. * an unimplemented operation, such as where an operand is a NaN or
  2242. * denormalized. In that case exit the emulation loop after a single
  2243. * iteration so as to let hardware execute any subsequent instructions.
  2244. *
  2245. * If we have no FPU hardware or it has been disabled, then continue
  2246. * emulating floating-point instructions until one of these conditions
  2247. * has occurred:
  2248. *
  2249. * - a non-FPU instruction has been encountered,
  2250. *
  2251. * - an attempt to emulate has ended with a signal,
  2252. *
  2253. * - the ISA mode has been switched.
  2254. *
  2255. * We need to terminate the emulation loop if we got switched to the
  2256. * MIPS16 mode, whether supported or not, so that we do not attempt
  2257. * to emulate a MIPS16 instruction as a regular MIPS FPU instruction.
  2258. * Similarly if we got switched to the microMIPS mode and only the
  2259. * regular MIPS mode is supported, so that we do not attempt to emulate
  2260. * a microMIPS instruction as a regular MIPS FPU instruction. Or if
  2261. * we got switched to the regular MIPS mode and only the microMIPS mode
  2262. * is supported, so that we do not attempt to emulate a regular MIPS
  2263. * instruction that should cause an Address Error exception instead.
  2264. * For simplicity we always terminate upon an ISA mode switch.
  2265. */
  2266. int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
  2267. int has_fpu, void *__user *fault_addr)
  2268. {
  2269. unsigned long oldepc, prevepc;
  2270. struct mm_decoded_insn dec_insn;
  2271. u16 instr[4];
  2272. u16 *instr_ptr;
  2273. int sig = 0;
  2274. oldepc = xcp->cp0_epc;
  2275. do {
  2276. prevepc = xcp->cp0_epc;
  2277. if (get_isa16_mode(prevepc) && cpu_has_mmips) {
  2278. /*
  2279. * Get next 2 microMIPS instructions and convert them
  2280. * into 32-bit instructions.
  2281. */
  2282. if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
  2283. (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
  2284. (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
  2285. (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
  2286. MIPS_FPU_EMU_INC_STATS(errors);
  2287. return SIGBUS;
  2288. }
  2289. instr_ptr = instr;
  2290. /* Get first instruction. */
  2291. if (mm_insn_16bit(*instr_ptr)) {
  2292. /* Duplicate the half-word. */
  2293. dec_insn.insn = (*instr_ptr << 16) |
  2294. (*instr_ptr);
  2295. /* 16-bit instruction. */
  2296. dec_insn.pc_inc = 2;
  2297. instr_ptr += 1;
  2298. } else {
  2299. dec_insn.insn = (*instr_ptr << 16) |
  2300. *(instr_ptr+1);
  2301. /* 32-bit instruction. */
  2302. dec_insn.pc_inc = 4;
  2303. instr_ptr += 2;
  2304. }
  2305. /* Get second instruction. */
  2306. if (mm_insn_16bit(*instr_ptr)) {
  2307. /* Duplicate the half-word. */
  2308. dec_insn.next_insn = (*instr_ptr << 16) |
  2309. (*instr_ptr);
  2310. /* 16-bit instruction. */
  2311. dec_insn.next_pc_inc = 2;
  2312. } else {
  2313. dec_insn.next_insn = (*instr_ptr << 16) |
  2314. *(instr_ptr+1);
  2315. /* 32-bit instruction. */
  2316. dec_insn.next_pc_inc = 4;
  2317. }
  2318. dec_insn.micro_mips_mode = 1;
  2319. } else {
  2320. if ((get_user(dec_insn.insn,
  2321. (mips_instruction __user *) xcp->cp0_epc)) ||
  2322. (get_user(dec_insn.next_insn,
  2323. (mips_instruction __user *)(xcp->cp0_epc+4)))) {
  2324. MIPS_FPU_EMU_INC_STATS(errors);
  2325. return SIGBUS;
  2326. }
  2327. dec_insn.pc_inc = 4;
  2328. dec_insn.next_pc_inc = 4;
  2329. dec_insn.micro_mips_mode = 0;
  2330. }
  2331. if ((dec_insn.insn == 0) ||
  2332. ((dec_insn.pc_inc == 2) &&
  2333. ((dec_insn.insn & 0xffff) == MM_NOP16)))
  2334. xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
  2335. else {
  2336. /*
  2337. * The 'ieee754_csr' is an alias of ctx->fcr31.
  2338. * No need to copy ctx->fcr31 to ieee754_csr.
  2339. */
  2340. sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
  2341. }
  2342. if (has_fpu)
  2343. break;
  2344. if (sig)
  2345. break;
  2346. /*
  2347. * We have to check for the ISA bit explicitly here,
  2348. * because `get_isa16_mode' may return 0 if support
  2349. * for code compression has been globally disabled,
  2350. * or otherwise we may produce the wrong signal or
  2351. * even proceed successfully where we must not.
  2352. */
  2353. if ((xcp->cp0_epc ^ prevepc) & 0x1)
  2354. break;
  2355. cond_resched();
  2356. } while (xcp->cp0_epc > prevepc);
  2357. /* SIGILL indicates a non-fpu instruction */
  2358. if (sig == SIGILL && xcp->cp0_epc != oldepc)
  2359. /* but if EPC has advanced, then ignore it */
  2360. sig = 0;
  2361. return sig;
  2362. }