sb1250_uart.h 12 KB

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  1. /* *********************************************************************
  2. * SB1250 Board Support Package
  3. *
  4. * UART Constants File: sb1250_uart.h
  5. *
  6. * This module contains constants and macros useful for
  7. * manipulating the SB1250's UARTs
  8. *
  9. * SB1250 specification level: User's manual 1/02/02
  10. *
  11. *********************************************************************
  12. *
  13. * Copyright 2000,2001,2002,2003
  14. * Broadcom Corporation. All rights reserved.
  15. *
  16. * This program is free software; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License as
  18. * published by the Free Software Foundation; either version 2 of
  19. * the License, or (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software
  28. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29. * MA 02111-1307 USA
  30. ********************************************************************* */
  31. #ifndef _SB1250_UART_H
  32. #define _SB1250_UART_H
  33. #include <asm/sibyte/sb1250_defs.h>
  34. /* **********************************************************************
  35. * DUART Registers
  36. ********************************************************************** */
  37. /*
  38. * DUART Mode Register #1 (Table 10-3)
  39. * Register: DUART_MODE_REG_1_A
  40. * Register: DUART_MODE_REG_1_B
  41. */
  42. #define S_DUART_BITS_PER_CHAR 0
  43. #define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR)
  44. #define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR)
  45. #define K_DUART_BITS_PER_CHAR_RSV0 0
  46. #define K_DUART_BITS_PER_CHAR_RSV1 1
  47. #define K_DUART_BITS_PER_CHAR_7 2
  48. #define K_DUART_BITS_PER_CHAR_8 3
  49. #define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0)
  50. #define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1)
  51. #define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7)
  52. #define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8)
  53. #define M_DUART_PARITY_TYPE_EVEN 0x00
  54. #define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2)
  55. #define S_DUART_PARITY_MODE 3
  56. #define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE)
  57. #define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE)
  58. #define K_DUART_PARITY_MODE_ADD 0
  59. #define K_DUART_PARITY_MODE_ADD_FIXED 1
  60. #define K_DUART_PARITY_MODE_NONE 2
  61. #define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD)
  62. #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED)
  63. #define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE)
  64. #define M_DUART_TX_IRQ_SEL_TXRDY 0
  65. #define M_DUART_TX_IRQ_SEL_TXEMPT _SB_MAKEMASK1(5)
  66. #define M_DUART_RX_IRQ_SEL_RXRDY 0
  67. #define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6)
  68. #define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7)
  69. /*
  70. * DUART Mode Register #2 (Table 10-4)
  71. * Register: DUART_MODE_REG_2_A
  72. * Register: DUART_MODE_REG_2_B
  73. */
  74. #define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */
  75. #define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3)
  76. #define M_DUART_STOP_BIT_LEN_1 0
  77. #define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4)
  78. #define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */
  79. #define S_DUART_CHAN_MODE 6
  80. #define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE)
  81. #define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE)
  82. #define K_DUART_CHAN_MODE_NORMAL 0
  83. #define K_DUART_CHAN_MODE_LCL_LOOP 2
  84. #define K_DUART_CHAN_MODE_REM_LOOP 3
  85. #define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL)
  86. #define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP)
  87. #define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP)
  88. /*
  89. * DUART Command Register (Table 10-5)
  90. * Register: DUART_CMD_A
  91. * Register: DUART_CMD_B
  92. */
  93. #define M_DUART_RX_EN _SB_MAKEMASK1(0)
  94. #define M_DUART_RX_DIS _SB_MAKEMASK1(1)
  95. #define M_DUART_TX_EN _SB_MAKEMASK1(2)
  96. #define M_DUART_TX_DIS _SB_MAKEMASK1(3)
  97. #define S_DUART_MISC_CMD 4
  98. #define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD)
  99. #define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD)
  100. #define K_DUART_MISC_CMD_NOACTION0 0
  101. #define K_DUART_MISC_CMD_NOACTION1 1
  102. #define K_DUART_MISC_CMD_RESET_RX 2
  103. #define K_DUART_MISC_CMD_RESET_TX 3
  104. #define K_DUART_MISC_CMD_NOACTION4 4
  105. #define K_DUART_MISC_CMD_RESET_BREAK_INT 5
  106. #define K_DUART_MISC_CMD_START_BREAK 6
  107. #define K_DUART_MISC_CMD_STOP_BREAK 7
  108. #define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0)
  109. #define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1)
  110. #define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX)
  111. #define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX)
  112. #define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4)
  113. #define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT)
  114. #define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
  115. #define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
  116. #define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7)
  117. /*
  118. * DUART Status Register (Table 10-6)
  119. * Register: DUART_STATUS_A
  120. * Register: DUART_STATUS_B
  121. * READ-ONLY
  122. */
  123. #define M_DUART_RX_RDY _SB_MAKEMASK1(0)
  124. #define M_DUART_RX_FFUL _SB_MAKEMASK1(1)
  125. #define M_DUART_TX_RDY _SB_MAKEMASK1(2)
  126. #define M_DUART_TX_EMT _SB_MAKEMASK1(3)
  127. #define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4)
  128. #define M_DUART_PARITY_ERR _SB_MAKEMASK1(5)
  129. #define M_DUART_FRM_ERR _SB_MAKEMASK1(6)
  130. #define M_DUART_RCVD_BRK _SB_MAKEMASK1(7)
  131. /*
  132. * DUART Baud Rate Register (Table 10-7)
  133. * Register: DUART_CLK_SEL_A
  134. * Register: DUART_CLK_SEL_B
  135. */
  136. #define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0)
  137. #define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1)
  138. /*
  139. * DUART Data Registers (Table 10-8 and 10-9)
  140. * Register: DUART_RX_HOLD_A
  141. * Register: DUART_RX_HOLD_B
  142. * Register: DUART_TX_HOLD_A
  143. * Register: DUART_TX_HOLD_B
  144. */
  145. #define M_DUART_RX_DATA _SB_MAKEMASK(8, 0)
  146. #define M_DUART_TX_DATA _SB_MAKEMASK(8, 0)
  147. /*
  148. * DUART Input Port Register (Table 10-10)
  149. * Register: DUART_IN_PORT
  150. */
  151. #define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0)
  152. #define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1)
  153. #define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2)
  154. #define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3)
  155. #define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4)
  156. #define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5)
  157. #define M_DUART_RIN0_PIN _SB_MAKEMASK1(6)
  158. #define M_DUART_RIN1_PIN _SB_MAKEMASK1(7)
  159. /*
  160. * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13)
  161. * Register: DUART_INPORT_CHNG
  162. */
  163. #define S_DUART_IN_PIN_VAL 0
  164. #define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL)
  165. #define S_DUART_IN_PIN_CHNG 4
  166. #define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG)
  167. /*
  168. * DUART Output port control register (Table 10-14)
  169. * Register: DUART_OPCR
  170. */
  171. #define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */
  172. #define M_DUART_OPC2_SEL _SB_MAKEMASK1(1)
  173. #define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */
  174. #define M_DUART_OPC3_SEL _SB_MAKEMASK1(3)
  175. #define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */
  176. /*
  177. * DUART Aux Control Register (Table 10-15)
  178. * Register: DUART_AUX_CTRL
  179. */
  180. #define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0)
  181. #define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1)
  182. #define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2)
  183. #define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3)
  184. #define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4)
  185. #define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0)
  186. #define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2)
  187. /*
  188. * DUART Interrupt Status Register (Table 10-16)
  189. * Register: DUART_ISR
  190. */
  191. #define M_DUART_ISR_TX_A _SB_MAKEMASK1(0)
  192. #define S_DUART_ISR_RX_A 1
  193. #define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A)
  194. #define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A)
  195. #define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A)
  196. #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2)
  197. #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3)
  198. #define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0)
  199. #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4)
  200. #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5)
  201. #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6)
  202. #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7)
  203. #define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4)
  204. /*
  205. * DUART Channel A Interrupt Status Register (Table 10-17)
  206. * DUART Channel B Interrupt Status Register (Table 10-18)
  207. * Register: DUART_ISR_A
  208. * Register: DUART_ISR_B
  209. */
  210. #define M_DUART_ISR_TX _SB_MAKEMASK1(0)
  211. #define M_DUART_ISR_RX _SB_MAKEMASK1(1)
  212. #define M_DUART_ISR_BRK _SB_MAKEMASK1(2)
  213. #define M_DUART_ISR_IN _SB_MAKEMASK1(3)
  214. #define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0)
  215. #define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4)
  216. /*
  217. * DUART Interrupt Mask Register (Table 10-19)
  218. * Register: DUART_IMR
  219. */
  220. #define M_DUART_IMR_TX_A _SB_MAKEMASK1(0)
  221. #define M_DUART_IMR_RX_A _SB_MAKEMASK1(1)
  222. #define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2)
  223. #define M_DUART_IMR_IN_A _SB_MAKEMASK1(3)
  224. #define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0)
  225. #define M_DUART_IMR_TX_B _SB_MAKEMASK1(4)
  226. #define M_DUART_IMR_RX_B _SB_MAKEMASK1(5)
  227. #define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6)
  228. #define M_DUART_IMR_IN_B _SB_MAKEMASK1(7)
  229. #define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4)
  230. /*
  231. * DUART Channel A Interrupt Mask Register (Table 10-20)
  232. * DUART Channel B Interrupt Mask Register (Table 10-21)
  233. * Register: DUART_IMR_A
  234. * Register: DUART_IMR_B
  235. */
  236. #define M_DUART_IMR_TX _SB_MAKEMASK1(0)
  237. #define M_DUART_IMR_RX _SB_MAKEMASK1(1)
  238. #define M_DUART_IMR_BRK _SB_MAKEMASK1(2)
  239. #define M_DUART_IMR_IN _SB_MAKEMASK1(3)
  240. #define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0)
  241. #define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4)
  242. /*
  243. * DUART Output Port Set Register (Table 10-22)
  244. * Register: DUART_SET_OPR
  245. */
  246. #define M_DUART_SET_OPR0 _SB_MAKEMASK1(0)
  247. #define M_DUART_SET_OPR1 _SB_MAKEMASK1(1)
  248. #define M_DUART_SET_OPR2 _SB_MAKEMASK1(2)
  249. #define M_DUART_SET_OPR3 _SB_MAKEMASK1(3)
  250. #define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4)
  251. /*
  252. * DUART Output Port Clear Register (Table 10-23)
  253. * Register: DUART_CLEAR_OPR
  254. */
  255. #define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0)
  256. #define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1)
  257. #define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2)
  258. #define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3)
  259. #define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4)
  260. /*
  261. * DUART Output Port RTS Register (Table 10-24)
  262. * Register: DUART_OUT_PORT
  263. */
  264. #define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0)
  265. #define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1)
  266. #define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2)
  267. #define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3)
  268. #define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4)
  269. #define M_DUART_OUT_PIN_SET(chan) \
  270. (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)
  271. #define M_DUART_OUT_PIN_CLR(chan) \
  272. (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
  273. #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
  274. /*
  275. * Full Interrupt Control Register
  276. */
  277. #define S_DUART_SIG_FULL _SB_MAKE64(0)
  278. #define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL)
  279. #define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL)
  280. #define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL)
  281. #define S_DUART_INT_TIME _SB_MAKE64(4)
  282. #define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME)
  283. #define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME)
  284. #define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME)
  285. #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
  286. /* ********************************************************************** */
  287. #endif