platform.c 12 KB

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  1. /*
  2. * Platform device support for Au1x00 SoCs.
  3. *
  4. * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
  5. *
  6. * (C) Copyright Embedded Alley Solutions, Inc 2005
  7. * Author: Pantelis Antoniou <pantelis@embeddedalley.com>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/etherdevice.h>
  16. #include <linux/init.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/serial_8250.h>
  19. #include <linux/slab.h>
  20. #include <linux/usb/ehci_pdriver.h>
  21. #include <linux/usb/ohci_pdriver.h>
  22. #include <asm/mach-au1x00/au1000.h>
  23. #include <asm/mach-au1x00/au1xxx_dbdma.h>
  24. #include <asm/mach-au1x00/au1100_mmc.h>
  25. #include <asm/mach-au1x00/au1xxx_eth.h>
  26. #include <prom.h>
  27. static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
  28. unsigned int old_state)
  29. {
  30. #ifdef CONFIG_SERIAL_8250
  31. switch (state) {
  32. case 0:
  33. alchemy_uart_enable(CPHYSADDR(port->membase));
  34. serial8250_do_pm(port, state, old_state);
  35. break;
  36. case 3: /* power off */
  37. serial8250_do_pm(port, state, old_state);
  38. alchemy_uart_disable(CPHYSADDR(port->membase));
  39. break;
  40. default:
  41. serial8250_do_pm(port, state, old_state);
  42. break;
  43. }
  44. #endif
  45. }
  46. #define PORT(_base, _irq) \
  47. { \
  48. .mapbase = _base, \
  49. .irq = _irq, \
  50. .regshift = 2, \
  51. .iotype = UPIO_AU, \
  52. .flags = UPF_SKIP_TEST | UPF_IOREMAP | \
  53. UPF_FIXED_TYPE, \
  54. .type = PORT_16550A, \
  55. .pm = alchemy_8250_pm, \
  56. }
  57. static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = {
  58. [ALCHEMY_CPU_AU1000] = {
  59. PORT(AU1000_UART0_PHYS_ADDR, AU1000_UART0_INT),
  60. PORT(AU1000_UART1_PHYS_ADDR, AU1000_UART1_INT),
  61. PORT(AU1000_UART2_PHYS_ADDR, AU1000_UART2_INT),
  62. PORT(AU1000_UART3_PHYS_ADDR, AU1000_UART3_INT),
  63. },
  64. [ALCHEMY_CPU_AU1500] = {
  65. PORT(AU1000_UART0_PHYS_ADDR, AU1500_UART0_INT),
  66. PORT(AU1000_UART3_PHYS_ADDR, AU1500_UART3_INT),
  67. },
  68. [ALCHEMY_CPU_AU1100] = {
  69. PORT(AU1000_UART0_PHYS_ADDR, AU1100_UART0_INT),
  70. PORT(AU1000_UART1_PHYS_ADDR, AU1100_UART1_INT),
  71. PORT(AU1000_UART3_PHYS_ADDR, AU1100_UART3_INT),
  72. },
  73. [ALCHEMY_CPU_AU1550] = {
  74. PORT(AU1000_UART0_PHYS_ADDR, AU1550_UART0_INT),
  75. PORT(AU1000_UART1_PHYS_ADDR, AU1550_UART1_INT),
  76. PORT(AU1000_UART3_PHYS_ADDR, AU1550_UART3_INT),
  77. },
  78. [ALCHEMY_CPU_AU1200] = {
  79. PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT),
  80. PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT),
  81. },
  82. [ALCHEMY_CPU_AU1300] = {
  83. PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT),
  84. PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT),
  85. PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT),
  86. PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT),
  87. },
  88. };
  89. static struct platform_device au1xx0_uart_device = {
  90. .name = "serial8250",
  91. .id = PLAT8250_DEV_AU1X00,
  92. };
  93. static void __init alchemy_setup_uarts(int ctype)
  94. {
  95. long uartclk;
  96. int s = sizeof(struct plat_serial8250_port);
  97. int c = alchemy_get_uarts(ctype);
  98. struct plat_serial8250_port *ports;
  99. struct clk *clk = clk_get(NULL, ALCHEMY_PERIPH_CLK);
  100. if (IS_ERR(clk))
  101. return;
  102. if (clk_prepare_enable(clk)) {
  103. clk_put(clk);
  104. return;
  105. }
  106. uartclk = clk_get_rate(clk);
  107. clk_put(clk);
  108. ports = kzalloc(s * (c + 1), GFP_KERNEL);
  109. if (!ports) {
  110. printk(KERN_INFO "Alchemy: no memory for UART data\n");
  111. return;
  112. }
  113. memcpy(ports, au1x00_uart_data[ctype], s * c);
  114. au1xx0_uart_device.dev.platform_data = ports;
  115. /* Fill up uartclk. */
  116. for (s = 0; s < c; s++)
  117. ports[s].uartclk = uartclk;
  118. if (platform_device_register(&au1xx0_uart_device))
  119. printk(KERN_INFO "Alchemy: failed to register UARTs\n");
  120. }
  121. /* The dmamask must be set for OHCI/EHCI to work */
  122. static u64 alchemy_ohci_dmamask = DMA_BIT_MASK(32);
  123. static u64 __maybe_unused alchemy_ehci_dmamask = DMA_BIT_MASK(32);
  124. /* Power on callback for the ehci platform driver */
  125. static int alchemy_ehci_power_on(struct platform_device *pdev)
  126. {
  127. return alchemy_usb_control(ALCHEMY_USB_EHCI0, 1);
  128. }
  129. /* Power off/suspend callback for the ehci platform driver */
  130. static void alchemy_ehci_power_off(struct platform_device *pdev)
  131. {
  132. alchemy_usb_control(ALCHEMY_USB_EHCI0, 0);
  133. }
  134. static struct usb_ehci_pdata alchemy_ehci_pdata = {
  135. .no_io_watchdog = 1,
  136. .power_on = alchemy_ehci_power_on,
  137. .power_off = alchemy_ehci_power_off,
  138. .power_suspend = alchemy_ehci_power_off,
  139. };
  140. /* Power on callback for the ohci platform driver */
  141. static int alchemy_ohci_power_on(struct platform_device *pdev)
  142. {
  143. int unit;
  144. unit = (pdev->id == 1) ?
  145. ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0;
  146. return alchemy_usb_control(unit, 1);
  147. }
  148. /* Power off/suspend callback for the ohci platform driver */
  149. static void alchemy_ohci_power_off(struct platform_device *pdev)
  150. {
  151. int unit;
  152. unit = (pdev->id == 1) ?
  153. ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0;
  154. alchemy_usb_control(unit, 0);
  155. }
  156. static struct usb_ohci_pdata alchemy_ohci_pdata = {
  157. .power_on = alchemy_ohci_power_on,
  158. .power_off = alchemy_ohci_power_off,
  159. .power_suspend = alchemy_ohci_power_off,
  160. };
  161. static unsigned long alchemy_ohci_data[][2] __initdata = {
  162. [ALCHEMY_CPU_AU1000] = { AU1000_USB_OHCI_PHYS_ADDR, AU1000_USB_HOST_INT },
  163. [ALCHEMY_CPU_AU1500] = { AU1000_USB_OHCI_PHYS_ADDR, AU1500_USB_HOST_INT },
  164. [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT },
  165. [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT },
  166. [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT },
  167. [ALCHEMY_CPU_AU1300] = { AU1300_USB_OHCI0_PHYS_ADDR, AU1300_USB_INT },
  168. };
  169. static unsigned long alchemy_ehci_data[][2] __initdata = {
  170. [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT },
  171. [ALCHEMY_CPU_AU1300] = { AU1300_USB_EHCI_PHYS_ADDR, AU1300_USB_INT },
  172. };
  173. static int __init _new_usbres(struct resource **r, struct platform_device **d)
  174. {
  175. *r = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
  176. if (!*r)
  177. return -ENOMEM;
  178. *d = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
  179. if (!*d) {
  180. kfree(*r);
  181. return -ENOMEM;
  182. }
  183. (*d)->dev.coherent_dma_mask = DMA_BIT_MASK(32);
  184. (*d)->num_resources = 2;
  185. (*d)->resource = *r;
  186. return 0;
  187. }
  188. static void __init alchemy_setup_usb(int ctype)
  189. {
  190. struct resource *res;
  191. struct platform_device *pdev;
  192. /* setup OHCI0. Every variant has one */
  193. if (_new_usbres(&res, &pdev))
  194. return;
  195. res[0].start = alchemy_ohci_data[ctype][0];
  196. res[0].end = res[0].start + 0x100 - 1;
  197. res[0].flags = IORESOURCE_MEM;
  198. res[1].start = alchemy_ohci_data[ctype][1];
  199. res[1].end = res[1].start;
  200. res[1].flags = IORESOURCE_IRQ;
  201. pdev->name = "ohci-platform";
  202. pdev->id = 0;
  203. pdev->dev.dma_mask = &alchemy_ohci_dmamask;
  204. pdev->dev.platform_data = &alchemy_ohci_pdata;
  205. if (platform_device_register(pdev))
  206. printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n");
  207. /* setup EHCI0: Au1200/Au1300 */
  208. if ((ctype == ALCHEMY_CPU_AU1200) || (ctype == ALCHEMY_CPU_AU1300)) {
  209. if (_new_usbres(&res, &pdev))
  210. return;
  211. res[0].start = alchemy_ehci_data[ctype][0];
  212. res[0].end = res[0].start + 0x100 - 1;
  213. res[0].flags = IORESOURCE_MEM;
  214. res[1].start = alchemy_ehci_data[ctype][1];
  215. res[1].end = res[1].start;
  216. res[1].flags = IORESOURCE_IRQ;
  217. pdev->name = "ehci-platform";
  218. pdev->id = 0;
  219. pdev->dev.dma_mask = &alchemy_ehci_dmamask;
  220. pdev->dev.platform_data = &alchemy_ehci_pdata;
  221. if (platform_device_register(pdev))
  222. printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n");
  223. }
  224. /* Au1300: OHCI1 */
  225. if (ctype == ALCHEMY_CPU_AU1300) {
  226. if (_new_usbres(&res, &pdev))
  227. return;
  228. res[0].start = AU1300_USB_OHCI1_PHYS_ADDR;
  229. res[0].end = res[0].start + 0x100 - 1;
  230. res[0].flags = IORESOURCE_MEM;
  231. res[1].start = AU1300_USB_INT;
  232. res[1].end = res[1].start;
  233. res[1].flags = IORESOURCE_IRQ;
  234. pdev->name = "ohci-platform";
  235. pdev->id = 1;
  236. pdev->dev.dma_mask = &alchemy_ohci_dmamask;
  237. pdev->dev.platform_data = &alchemy_ohci_pdata;
  238. if (platform_device_register(pdev))
  239. printk(KERN_INFO "Alchemy USB: cannot add OHCI1\n");
  240. }
  241. }
  242. /* Macro to help defining the Ethernet MAC resources */
  243. #define MAC_RES_COUNT 4 /* MAC regs, MAC en, MAC INT, MACDMA regs */
  244. #define MAC_RES(_base, _enable, _irq, _macdma) \
  245. { \
  246. .start = _base, \
  247. .end = _base + 0xffff, \
  248. .flags = IORESOURCE_MEM, \
  249. }, \
  250. { \
  251. .start = _enable, \
  252. .end = _enable + 0x3, \
  253. .flags = IORESOURCE_MEM, \
  254. }, \
  255. { \
  256. .start = _irq, \
  257. .end = _irq, \
  258. .flags = IORESOURCE_IRQ \
  259. }, \
  260. { \
  261. .start = _macdma, \
  262. .end = _macdma + 0x1ff, \
  263. .flags = IORESOURCE_MEM, \
  264. }
  265. static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = {
  266. [ALCHEMY_CPU_AU1000] = {
  267. MAC_RES(AU1000_MAC0_PHYS_ADDR,
  268. AU1000_MACEN_PHYS_ADDR,
  269. AU1000_MAC0_DMA_INT,
  270. AU1000_MACDMA0_PHYS_ADDR)
  271. },
  272. [ALCHEMY_CPU_AU1500] = {
  273. MAC_RES(AU1500_MAC0_PHYS_ADDR,
  274. AU1500_MACEN_PHYS_ADDR,
  275. AU1500_MAC0_DMA_INT,
  276. AU1000_MACDMA0_PHYS_ADDR)
  277. },
  278. [ALCHEMY_CPU_AU1100] = {
  279. MAC_RES(AU1000_MAC0_PHYS_ADDR,
  280. AU1000_MACEN_PHYS_ADDR,
  281. AU1100_MAC0_DMA_INT,
  282. AU1000_MACDMA0_PHYS_ADDR)
  283. },
  284. [ALCHEMY_CPU_AU1550] = {
  285. MAC_RES(AU1000_MAC0_PHYS_ADDR,
  286. AU1000_MACEN_PHYS_ADDR,
  287. AU1550_MAC0_DMA_INT,
  288. AU1000_MACDMA0_PHYS_ADDR)
  289. },
  290. };
  291. static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
  292. .phy1_search_mac0 = 1,
  293. };
  294. static struct platform_device au1xxx_eth0_device = {
  295. .name = "au1000-eth",
  296. .id = 0,
  297. .num_resources = MAC_RES_COUNT,
  298. .dev.platform_data = &au1xxx_eth0_platform_data,
  299. };
  300. static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = {
  301. [ALCHEMY_CPU_AU1000] = {
  302. MAC_RES(AU1000_MAC1_PHYS_ADDR,
  303. AU1000_MACEN_PHYS_ADDR + 4,
  304. AU1000_MAC1_DMA_INT,
  305. AU1000_MACDMA1_PHYS_ADDR)
  306. },
  307. [ALCHEMY_CPU_AU1500] = {
  308. MAC_RES(AU1500_MAC1_PHYS_ADDR,
  309. AU1500_MACEN_PHYS_ADDR + 4,
  310. AU1500_MAC1_DMA_INT,
  311. AU1000_MACDMA1_PHYS_ADDR)
  312. },
  313. [ALCHEMY_CPU_AU1550] = {
  314. MAC_RES(AU1000_MAC1_PHYS_ADDR,
  315. AU1000_MACEN_PHYS_ADDR + 4,
  316. AU1550_MAC1_DMA_INT,
  317. AU1000_MACDMA1_PHYS_ADDR)
  318. },
  319. };
  320. static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
  321. .phy1_search_mac0 = 1,
  322. };
  323. static struct platform_device au1xxx_eth1_device = {
  324. .name = "au1000-eth",
  325. .id = 1,
  326. .num_resources = MAC_RES_COUNT,
  327. .dev.platform_data = &au1xxx_eth1_platform_data,
  328. };
  329. void __init au1xxx_override_eth_cfg(unsigned int port,
  330. struct au1000_eth_platform_data *eth_data)
  331. {
  332. if (!eth_data || port > 1)
  333. return;
  334. if (port == 0)
  335. memcpy(&au1xxx_eth0_platform_data, eth_data,
  336. sizeof(struct au1000_eth_platform_data));
  337. else
  338. memcpy(&au1xxx_eth1_platform_data, eth_data,
  339. sizeof(struct au1000_eth_platform_data));
  340. }
  341. static void __init alchemy_setup_macs(int ctype)
  342. {
  343. int ret, i;
  344. unsigned char ethaddr[6];
  345. struct resource *macres;
  346. /* Handle 1st MAC */
  347. if (alchemy_get_macs(ctype) < 1)
  348. return;
  349. macres = kmemdup(au1xxx_eth0_resources[ctype],
  350. sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
  351. if (!macres) {
  352. printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n");
  353. return;
  354. }
  355. au1xxx_eth0_device.resource = macres;
  356. i = prom_get_ethernet_addr(ethaddr);
  357. if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
  358. memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
  359. ret = platform_device_register(&au1xxx_eth0_device);
  360. if (ret)
  361. printk(KERN_INFO "Alchemy: failed to register MAC0\n");
  362. /* Handle 2nd MAC */
  363. if (alchemy_get_macs(ctype) < 2)
  364. return;
  365. macres = kmemdup(au1xxx_eth1_resources[ctype],
  366. sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
  367. if (!macres) {
  368. printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n");
  369. return;
  370. }
  371. au1xxx_eth1_device.resource = macres;
  372. ethaddr[5] += 1; /* next addr for 2nd MAC */
  373. if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
  374. memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
  375. /* Register second MAC if enabled in pinfunc */
  376. if (!(alchemy_rdsys(AU1000_SYS_PINFUNC) & SYS_PF_NI2)) {
  377. ret = platform_device_register(&au1xxx_eth1_device);
  378. if (ret)
  379. printk(KERN_INFO "Alchemy: failed to register MAC1\n");
  380. }
  381. }
  382. static int __init au1xxx_platform_init(void)
  383. {
  384. int ctype = alchemy_get_cputype();
  385. alchemy_setup_uarts(ctype);
  386. alchemy_setup_macs(ctype);
  387. alchemy_setup_usb(ctype);
  388. return 0;
  389. }
  390. arch_initcall(au1xxx_platform_init);