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linux-libre
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arch
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blackfin
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mach-bf609
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include
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mach
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irq.h

irq.h 14 KB
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  1. /*
    2. 

  2.  * Copyright 2011 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the GPL-2 or later.
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _BF60x_IRQ_H_
    8. 

  8. #define _BF60x_IRQ_H_
    9. 

  9. 

  10. #include <mach-common/irq.h>
    11. 

  11. 

  12. #define NR_PERI_INTS		(5 * 32)
    13. 

  13. 

  14. #define IRQ_SEC_ERR		BFIN_IRQ(0)	/* SEC Error */
    15. 

  15. #define IRQ_CGU_EVT		BFIN_IRQ(1)	/* CGU Event */
    16. 

  16. #define IRQ_WATCH0		BFIN_IRQ(2)	/* Watchdog0 Interrupt */
    17. 

  17. #define IRQ_WATCH1		BFIN_IRQ(3)	/* Watchdog1 Interrupt */
    18. 

  18. #define IRQ_L2CTL0_ECC_ERR	BFIN_IRQ(4)	/* L2 ECC Error */
    19. 

  19. #define IRQ_L2CTL0_ECC_WARN	BFIN_IRQ(5)	/* L2 ECC Waring */
    20. 

  20. #define IRQ_C0_DBL_FAULT	BFIN_IRQ(6)	/* Core 0 Double Fault */
    21. 

  21. #define IRQ_C1_DBL_FAULT	BFIN_IRQ(7)	/* Core 1 Double Fault */
    22. 

  22. #define IRQ_C0_HW_ERR		BFIN_IRQ(8)	/* Core 0 Hardware Error */
    23. 

  23. #define IRQ_C1_HW_ERR		BFIN_IRQ(9)	/* Core 1 Hardware Error */
    24. 

  24. #define IRQ_C0_NMI_L1_PARITY_ERR	BFIN_IRQ(10)	/* Core 0 Unhandled NMI or L1 Memory Parity Error */
    25. 

  25. #define IRQ_C1_NMI_L1_PARITY_ERR	BFIN_IRQ(11)	/* Core 1 Unhandled NMI or L1 Memory Parity Error */
    26. 

  26. #define CORE_IRQS		(IRQ_C1_NMI_L1_PARITY_ERR + 1)
    27. 

  27. 

  28. #define IRQ_TIMER0		BFIN_IRQ(12)	/* Timer 0 Interrupt */
    29. 

  29. #define IRQ_TIMER1		BFIN_IRQ(13)	/* Timer 1 Interrupt */
    30. 

  30. #define IRQ_TIMER2		BFIN_IRQ(14)	/* Timer 2 Interrupt */
    31. 

  31. #define IRQ_TIMER3		BFIN_IRQ(15)	/* Timer 3 Interrupt */
    32. 

  32. #define IRQ_TIMER4		BFIN_IRQ(16)	/* Timer 4 Interrupt */
    33. 

  33. #define IRQ_TIMER5		BFIN_IRQ(17)	/* Timer 5 Interrupt */
    34. 

  34. #define IRQ_TIMER6		BFIN_IRQ(18)	/* Timer 6 Interrupt */
    35. 

  35. #define IRQ_TIMER7		BFIN_IRQ(19)	/* Timer 7 Interrupt */
    36. 

  36. #define IRQ_TIMER_STAT		BFIN_IRQ(20)	/* Timer Block Status */
    37. 

  37. #define IRQ_PINT0		BFIN_IRQ(21)	/* PINT0 Interrupt */
    38. 

  38. #define IRQ_PINT1		BFIN_IRQ(22)	/* PINT1 Interrupt */
    39. 

  39. #define IRQ_PINT2		BFIN_IRQ(23)	/* PINT2 Interrupt */
    40. 

  40. #define IRQ_PINT3		BFIN_IRQ(24)	/* PINT3 Interrupt */
    41. 

  41. #define IRQ_PINT4		BFIN_IRQ(25)	/* PINT4 Interrupt */
    42. 

  42. #define IRQ_PINT5		BFIN_IRQ(26)	/* PINT5 Interrupt */
    43. 

  43. #define IRQ_CNT			BFIN_IRQ(27)	/* CNT Interrupt */
    44. 

  44. #define IRQ_PWM0_TRIP		BFIN_IRQ(28)	/* PWM0 Trip Interrupt */
    45. 

  45. #define IRQ_PWM0_SYNC		BFIN_IRQ(29)	/* PWM0 Sync Interrupt */
    46. 

  46. #define IRQ_PWM1_TRIP		BFIN_IRQ(30)	/* PWM1 Trip Interrupt */
    47. 

  47. #define IRQ_PWM1_SYNC		BFIN_IRQ(31)	/* PWM1 Sync Interrupt */
    48. 

  48. #define IRQ_TWI0		BFIN_IRQ(32)	/* TWI0 Interrupt */
    49. 

  49. #define IRQ_TWI1		BFIN_IRQ(33)	/* TWI1 Interrupt */
    50. 

  50. #define IRQ_SOFT0		BFIN_IRQ(34)	/* Software-Driven Interrupt 0 */
    51. 

  51. #define IRQ_SOFT1		BFIN_IRQ(35)	/* Software-Driven Interrupt 1 */
    52. 

  52. #define IRQ_SOFT2		BFIN_IRQ(36)	/* Software-Driven Interrupt 2 */
    53. 

  53. #define IRQ_SOFT3		BFIN_IRQ(37)	/* Software-Driven Interrupt 3 */
    54. 

  54. #define IRQ_ACM_EVT_MISS	BFIN_IRQ(38)	/* ACM Event Miss */
    55. 

  55. #define IRQ_ACM_EVT_COMPLETE 	BFIN_IRQ(39)	/* ACM Event Complete */
    56. 

  56. #define IRQ_CAN0_RX		BFIN_IRQ(40)	/* CAN0 Receive Interrupt */
    57. 

  57. #define IRQ_CAN0_TX		BFIN_IRQ(41)	/* CAN0 Transmit Interrupt */
    58. 

  58. #define IRQ_CAN0_STAT		BFIN_IRQ(42)	/* CAN0 Status */
    59. 

  59. #define IRQ_SPORT0_TX		BFIN_IRQ(43)	/* SPORT0 TX Interrupt (DMA0) */
    60. 

  60. #define IRQ_SPORT0_TX_STAT	BFIN_IRQ(44)	/* SPORT0 TX Status Interrupt */
    61. 

  61. #define IRQ_SPORT0_RX		BFIN_IRQ(45)	/* SPORT0 RX Interrupt (DMA1) */
    62. 

  62. #define IRQ_SPORT0_RX_STAT	BFIN_IRQ(46)	/* SPORT0 RX Status Interrupt */
    63. 

  63. #define IRQ_SPORT1_TX		BFIN_IRQ(47)	/* SPORT1 TX Interrupt (DMA2) */
    64. 

  64. #define IRQ_SPORT1_TX_STAT	BFIN_IRQ(48)	/* SPORT1 TX Status Interrupt */
    65. 

  65. #define IRQ_SPORT1_RX		BFIN_IRQ(49)	/* SPORT1 RX Interrupt (DMA3) */
    66. 

  66. #define IRQ_SPORT1_RX_STAT	BFIN_IRQ(50)	/* SPORT1 RX Status Interrupt */
    67. 

  67. #define IRQ_SPORT2_TX		BFIN_IRQ(51)	/* SPORT2 TX Interrupt (DMA4) */
    68. 

  68. #define IRQ_SPORT2_TX_STAT	BFIN_IRQ(52)	/* SPORT2 TX Status Interrupt */
    69. 

  69. #define IRQ_SPORT2_RX		BFIN_IRQ(53)	/* SPORT2 RX Interrupt (DMA5) */
    70. 

  70. #define IRQ_SPORT2_RX_STAT	BFIN_IRQ(54)	/* SPORT2 RX Status Interrupt */
    71. 

  71. #define IRQ_SPI0_TX		BFIN_IRQ(55)	/* SPI0 TX Interrupt (DMA6) */
    72. 

  72. #define IRQ_SPI0_RX		BFIN_IRQ(56)	/* SPI0 RX Interrupt (DMA7) */
    73. 

  73. #define IRQ_SPI0_STAT		BFIN_IRQ(57)	/* SPI0 Status Interrupt */
    74. 

  74. #define IRQ_SPI1_TX		BFIN_IRQ(58)	/* SPI1 TX Interrupt (DMA8) */
    75. 

  75. #define IRQ_SPI1_RX		BFIN_IRQ(59)	/* SPI1 RX Interrupt (DMA9) */
    76. 

  76. #define IRQ_SPI1_STAT		BFIN_IRQ(60)	/* SPI1 Status Interrupt */
    77. 

  77. #define IRQ_RSI			BFIN_IRQ(61)	/* RSI (DMA10) Interrupt */
    78. 

  78. #define IRQ_RSI_INT0		BFIN_IRQ(62)	/* RSI Interrupt0 */
    79. 

  79. #define IRQ_RSI_INT1		BFIN_IRQ(63)	/* RSI Interrupt1 */
    80. 

  80. #define IRQ_SDU			BFIN_IRQ(64)	/* DMA11 Data (SDU) */
    81. 

  81. /*       -- RESERVED --             65		   DMA12 Data (Reserved) */
    82. 

  82. /*       -- RESERVED --             66		   Reserved */
    83. 

  83. /*       -- RESERVED --             67		   Reserved */
    84. 

  84. #define IRQ_EMAC0_STAT		BFIN_IRQ(68)	/* EMAC0 Status */
    85. 

  85. /*       -- RESERVED --             69		   EMAC0 Power (Reserved) */
    86. 

  86. #define IRQ_EMAC1_STAT		BFIN_IRQ(70)	/* EMAC1 Status */
    87. 

  87. /*       -- RESERVED --             71		   EMAC1 Power (Reserved) */
    88. 

  88. #define IRQ_LP0			BFIN_IRQ(72)	/* DMA13 Data (Link Port 0) */
    89. 

  89. #define IRQ_LP0_STAT		BFIN_IRQ(73)	/* Link Port 0 Status */
    90. 

  90. #define IRQ_LP1			BFIN_IRQ(74)	/* DMA14 Data (Link Port 1) */
    91. 

  91. #define IRQ_LP1_STAT		BFIN_IRQ(75)	/* Link Port 1 Status */
    92. 

  92. #define IRQ_LP2			BFIN_IRQ(76)	/* DMA15 Data (Link Port 2) */
    93. 

  93. #define IRQ_LP2_STAT		BFIN_IRQ(77)	/* Link Port 2 Status */
    94. 

  94. #define IRQ_LP3			BFIN_IRQ(78)	/* DMA16 Data(Link Port 3) */
    95. 

  95. #define IRQ_LP3_STAT		BFIN_IRQ(79)	/* Link Port 3 Status */
    96. 

  96. #define IRQ_UART0_TX		BFIN_IRQ(80)	/* UART0 TX Interrupt (DMA17) */
    97. 

  97. #define IRQ_UART0_RX		BFIN_IRQ(81)	/* UART0 RX Interrupt (DMA18) */
    98. 

  98. #define IRQ_UART0_STAT		BFIN_IRQ(82)	/* UART0 Status(Error) Interrupt */
    99. 

  99. #define IRQ_UART1_TX		BFIN_IRQ(83)	/* UART1 TX Interrupt (DMA19) */
    100. 

  100. #define IRQ_UART1_RX		BFIN_IRQ(84)	/* UART1 RX Interrupt (DMA20) */
    101. 

  101. #define IRQ_UART1_STAT		BFIN_IRQ(85)	/* UART1 Status(Error) Interrupt */
    102. 

  102. #define IRQ_MDMA0_SRC_CRC0	BFIN_IRQ(86)	/* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */
    103. 

  103. #define IRQ_MDMA0_DEST_CRC0	BFIN_IRQ(87)	/* DMA22 Data (MDMA Stream 0 Destination/CRC0 Output Channel) */
    104. 

  104. #define IRQ_MDMAS0		IRQ_MDMA0_DEST_CRC0
    105. 

  105. #define IRQ_CRC0_DCNTEXP	BFIN_IRQ(88)	/* CRC0 DATACOUNT Expiration */
    106. 

  106. #define IRQ_CRC0_ERR		BFIN_IRQ(89)	/* CRC0 Error */
    107. 

  107. #define IRQ_MDMA1_SRC_CRC1	BFIN_IRQ(90)	/* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */
    108. 

  108. #define IRQ_MDMA1_DEST_CRC1	BFIN_IRQ(91)	/* DMA24 Data (MDMA Stream 1 Destination/CRC1 Output Channel) */
    109. 

  109. #define IRQ_MDMAS1		IRQ_MDMA1_DEST_CRC1
    110. 

  110. #define IRQ_CRC1_DCNTEXP	BFIN_IRQ(92)	/* CRC1 DATACOUNT Expiration */
    111. 

  111. #define IRQ_CRC1_ERR		BFIN_IRQ(93)	/* CRC1 Error */
    112. 

  112. #define IRQ_MDMA2_SRC		BFIN_IRQ(94)	/* DMA25 Data (MDMA Stream 2 Source Channel) */
    113. 

  113. #define IRQ_MDMA2_DEST		BFIN_IRQ(95)	/* DMA26 Data (MDMA Stream 2 Destination Channel) */
    114. 

  114. #define IRQ_MDMAS2		IRQ_MDMA2_DEST
    115. 

  115. #define IRQ_MDMA3_SRC		BFIN_IRQ(96)	/* DMA27 Data (MDMA Stream 3 Source Channel) */
    116. 

  116. #define IRQ_MDMA3_DEST 		BFIN_IRQ(97)	/* DMA28 Data (MDMA Stream 3 Destination Channel) */
    117. 

  117. #define IRQ_MDMAS3		IRQ_MDMA3_DEST
    118. 

  118. #define IRQ_EPPI0_CH0 		BFIN_IRQ(98)	/* DMA29 Data (EPPI0 Channel 0) */
    119. 

  119. #define IRQ_EPPI0_CH1 		BFIN_IRQ(99)	/* DMA30 Data (EPPI0 Channel 1) */
    120. 

  120. #define IRQ_EPPI0_STAT		BFIN_IRQ(100)	/* EPPI0 Status */
    121. 

  121. #define IRQ_EPPI2_CH0		BFIN_IRQ(101)	/* DMA31 Data (EPPI2 Channel 0) */
    122. 

  122. #define IRQ_EPPI2_CH1		BFIN_IRQ(102)	/* DMA32 Data (EPPI2 Channel 1) */
    123. 

  123. #define IRQ_EPPI2_STAT		BFIN_IRQ(103)	/* EPPI2 Status */
    124. 

  124. #define IRQ_EPPI1_CH0		BFIN_IRQ(104)	/* DMA33 Data (EPPI1 Channel 0) */
    125. 

  125. #define IRQ_EPPI1_CH1		BFIN_IRQ(105)	/* DMA34 Data (EPPI1 Channel 1) */
    126. 

  126. #define IRQ_EPPI1_STAT		BFIN_IRQ(106)	/* EPPI1 Status */
    127. 

  127. #define IRQ_PIXC_CH0		BFIN_IRQ(107)	/* DMA35 Data (PIXC Channel 0) */
    128. 

  128. #define IRQ_PIXC_CH1		BFIN_IRQ(108)	/* DMA36 Data (PIXC Channel 1) */
    129. 

  129. #define IRQ_PIXC_CH2		BFIN_IRQ(109)	/* DMA37 Data (PIXC Channel 2) */
    130. 

  130. #define IRQ_PIXC_STAT		BFIN_IRQ(110)	/* PIXC Status */
    131. 

  131. #define IRQ_PVP_CPDOB		BFIN_IRQ(111)	/* DMA38 Data (PVP0 Camera Pipe Data Out B) */
    132. 

  132. #define IRQ_PVP_CPDOC		BFIN_IRQ(112)	/* DMA39 Data (PVP0 Camera Pipe Data Out C) */
    133. 

  133. #define IRQ_PVP_CPSTAT		BFIN_IRQ(113)	/* DMA40 Data (PVP0 Camera Pipe Status Out) */
    134. 

  134. #define IRQ_PVP_CPCI		BFIN_IRQ(114)	/* DMA41 Data (PVP0 Camera Pipe Control In) */
    135. 

  135. #define IRQ_PVP_STAT0		BFIN_IRQ(115)	/* PVP0 Status 0 */
    136. 

  136. #define IRQ_PVP_MPDO		BFIN_IRQ(116)	/* DMA42 Data (PVP0 Memory Pipe Data Out) */
    137. 

  137. #define IRQ_PVP_MPDI		BFIN_IRQ(117)	/* DMA43 Data (PVP0 Memory Pipe Data In) */
    138. 

  138. #define IRQ_PVP_MPSTAT		BFIN_IRQ(118)	/* DMA44 Data (PVP0 Memory Pipe Status Out) */
    139. 

  139. #define IRQ_PVP_MPCI		BFIN_IRQ(119)	/* DMA45 Data (PVP0 Memory Pipe Control In) */
    140. 

  140. #define IRQ_PVP_CPDOA		BFIN_IRQ(120)	/* DMA46 Data (PVP0 Camera Pipe Data Out A) */
    141. 

  141. #define IRQ_PVP_STAT1		BFIN_IRQ(121)	/* PVP0 Status 1 */
    142. 

  142. #define IRQ_USB_STAT		BFIN_IRQ(122)	/* USB Status Interrupt */
    143. 

  143. #define IRQ_USB_DMA		BFIN_IRQ(123)	/* USB DMA Interrupt */
    144. 

  144. #define IRQ_TRU_INT0		BFIN_IRQ(124)	/* TRU0 Interrupt 0 */
    145. 

  145. #define IRQ_TRU_INT1		BFIN_IRQ(125)	/* TRU0 Interrupt 1 */
    146. 

  146. #define IRQ_TRU_INT2		BFIN_IRQ(126)	/* TRU0 Interrupt 2 */
    147. 

  147. #define IRQ_TRU_INT3		BFIN_IRQ(127)	/* TRU0 Interrupt 3 */
    148. 

  148. #define IRQ_DMAC0_ERROR		BFIN_IRQ(128)	/* DMAC0 Status Interrupt */
    149. 

  149. #define IRQ_CGU0_ERROR		BFIN_IRQ(129)	/* CGU0 Error */
    150. 

  150. /*       -- RESERVED --             130		   Reserved */
    151. 

  151. #define IRQ_DPM			BFIN_IRQ(131)	/* DPM0 Event */
    152. 

  152. /*       -- RESERVED --             132		   Reserved */
    153. 

  153. #define IRQ_SWU0		BFIN_IRQ(133)	/* SWU0 */
    154. 

  154. #define IRQ_SWU1		BFIN_IRQ(134)	/* SWU1 */
    155. 

  155. #define IRQ_SWU2		BFIN_IRQ(135)	/* SWU2 */
    156. 

  156. #define IRQ_SWU3		BFIN_IRQ(136)	/* SWU3 */
    157. 

  157. #define IRQ_SWU4		BFIN_IRQ(137)	/* SWU4 */
    158. 

  158. #define IRQ_SWU5		BFIN_IRQ(138)	/* SWU5 */
    159. 

  159. #define IRQ_SWU6		BFIN_IRQ(139)	/* SWU6 */
    160. 

  160. 

  161. #define SYS_IRQS		IRQ_SWU6
    162. 

  162. 

  163. #define BFIN_PA_IRQ(x)		((x) + SYS_IRQS + 1)
    164. 

  164. #define IRQ_PA0			BFIN_PA_IRQ(0)
    165. 

  165. #define IRQ_PA1			BFIN_PA_IRQ(1)
    166. 

  166. #define IRQ_PA2			BFIN_PA_IRQ(2)
    167. 

  167. #define IRQ_PA3			BFIN_PA_IRQ(3)
    168. 

  168. #define IRQ_PA4			BFIN_PA_IRQ(4)
    169. 

  169. #define IRQ_PA5			BFIN_PA_IRQ(5)
    170. 

  170. #define IRQ_PA6			BFIN_PA_IRQ(6)
    171. 

  171. #define IRQ_PA7			BFIN_PA_IRQ(7)
    172. 

  172. #define IRQ_PA8			BFIN_PA_IRQ(8)
    173. 

  173. #define IRQ_PA9			BFIN_PA_IRQ(9)
    174. 

  174. #define IRQ_PA10		BFIN_PA_IRQ(10)
    175. 

  175. #define IRQ_PA11		BFIN_PA_IRQ(11)
    176. 

  176. #define IRQ_PA12		BFIN_PA_IRQ(12)
    177. 

  177. #define IRQ_PA13		BFIN_PA_IRQ(13)
    178. 

  178. #define IRQ_PA14		BFIN_PA_IRQ(14)
    179. 

  179. #define IRQ_PA15		BFIN_PA_IRQ(15)
    180. 

  180. 

  181. #define BFIN_PB_IRQ(x)		((x) + IRQ_PA15 + 1)
    182. 

  182. #define IRQ_PB0			BFIN_PB_IRQ(0)
    183. 

  183. #define IRQ_PB1			BFIN_PB_IRQ(1)
    184. 

  184. #define IRQ_PB2			BFIN_PB_IRQ(2)
    185. 

  185. #define IRQ_PB3			BFIN_PB_IRQ(3)
    186. 

  186. #define IRQ_PB4			BFIN_PB_IRQ(4)
    187. 

  187. #define IRQ_PB5			BFIN_PB_IRQ(5)
    188. 

  188. #define IRQ_PB6			BFIN_PB_IRQ(6)
    189. 

  189. #define IRQ_PB7			BFIN_PB_IRQ(7)
    190. 

  190. #define IRQ_PB8			BFIN_PB_IRQ(8)
    191. 

  191. #define IRQ_PB9			BFIN_PB_IRQ(9)
    192. 

  192. #define IRQ_PB10		BFIN_PB_IRQ(10)
    193. 

  193. #define IRQ_PB11		BFIN_PB_IRQ(11)
    194. 

  194. #define IRQ_PB12		BFIN_PB_IRQ(12)
    195. 

  195. #define IRQ_PB13		BFIN_PB_IRQ(13)
    196. 

  196. #define IRQ_PB14		BFIN_PB_IRQ(14)
    197. 

  197. #define IRQ_PB15		BFIN_PB_IRQ(15)		/* N/A */
    198. 

  198. 

  199. #define BFIN_PC_IRQ(x)		((x) + IRQ_PB15 + 1)
    200. 

  200. #define IRQ_PC0			BFIN_PC_IRQ(0)
    201. 

  201. #define IRQ_PC1			BFIN_PC_IRQ(1)
    202. 

  202. #define IRQ_PC2			BFIN_PC_IRQ(2)
    203. 

  203. #define IRQ_PC3			BFIN_PC_IRQ(3)
    204. 

  204. #define IRQ_PC4			BFIN_PC_IRQ(4)
    205. 

  205. #define IRQ_PC5			BFIN_PC_IRQ(5)
    206. 

  206. #define IRQ_PC6			BFIN_PC_IRQ(6)
    207. 

  207. #define IRQ_PC7			BFIN_PC_IRQ(7)
    208. 

  208. #define IRQ_PC8			BFIN_PC_IRQ(8)
    209. 

  209. #define IRQ_PC9			BFIN_PC_IRQ(9)
    210. 

  210. #define IRQ_PC10		BFIN_PC_IRQ(10)
    211. 

  211. #define IRQ_PC11		BFIN_PC_IRQ(11)
    212. 

  212. #define IRQ_PC12		BFIN_PC_IRQ(12)
    213. 

  213. #define IRQ_PC13		BFIN_PC_IRQ(13)
    214. 

  214. #define IRQ_PC14		BFIN_PC_IRQ(14)		/* N/A */
    215. 

  215. #define IRQ_PC15		BFIN_PC_IRQ(15)		/* N/A */
    216. 

  216. 

  217. #define BFIN_PD_IRQ(x)		((x) + IRQ_PC15 + 1)
    218. 

  218. #define IRQ_PD0			BFIN_PD_IRQ(0)
    219. 

  219. #define IRQ_PD1			BFIN_PD_IRQ(1)
    220. 

  220. #define IRQ_PD2			BFIN_PD_IRQ(2)
    221. 

  221. #define IRQ_PD3			BFIN_PD_IRQ(3)
    222. 

  222. #define IRQ_PD4			BFIN_PD_IRQ(4)
    223. 

  223. #define IRQ_PD5			BFIN_PD_IRQ(5)
    224. 

  224. #define IRQ_PD6			BFIN_PD_IRQ(6)
    225. 

  225. #define IRQ_PD7			BFIN_PD_IRQ(7)
    226. 

  226. #define IRQ_PD8			BFIN_PD_IRQ(8)
    227. 

  227. #define IRQ_PD9			BFIN_PD_IRQ(9)
    228. 

  228. #define IRQ_PD10		BFIN_PD_IRQ(10)
    229. 

  229. #define IRQ_PD11		BFIN_PD_IRQ(11)
    230. 

  230. #define IRQ_PD12		BFIN_PD_IRQ(12)
    231. 

  231. #define IRQ_PD13		BFIN_PD_IRQ(13)
    232. 

  232. #define IRQ_PD14		BFIN_PD_IRQ(14)
    233. 

  233. #define IRQ_PD15		BFIN_PD_IRQ(15)
    234. 

  234. 

  235. #define BFIN_PE_IRQ(x)		((x) + IRQ_PD15 + 1)
    236. 

  236. #define IRQ_PE0			BFIN_PE_IRQ(0)
    237. 

  237. #define IRQ_PE1			BFIN_PE_IRQ(1)
    238. 

  238. #define IRQ_PE2			BFIN_PE_IRQ(2)
    239. 

  239. #define IRQ_PE3			BFIN_PE_IRQ(3)
    240. 

  240. #define IRQ_PE4			BFIN_PE_IRQ(4)
    241. 

  241. #define IRQ_PE5			BFIN_PE_IRQ(5)
    242. 

  242. #define IRQ_PE6			BFIN_PE_IRQ(6)
    243. 

  243. #define IRQ_PE7			BFIN_PE_IRQ(7)
    244. 

  244. #define IRQ_PE8			BFIN_PE_IRQ(8)
    245. 

  245. #define IRQ_PE9			BFIN_PE_IRQ(9)
    246. 

  246. #define IRQ_PE10		BFIN_PE_IRQ(10)
    247. 

  247. #define IRQ_PE11		BFIN_PE_IRQ(11)
    248. 

  248. #define IRQ_PE12		BFIN_PE_IRQ(12)
    249. 

  249. #define IRQ_PE13		BFIN_PE_IRQ(13)
    250. 

  250. #define IRQ_PE14		BFIN_PE_IRQ(14)
    251. 

  251. #define IRQ_PE15		BFIN_PE_IRQ(15)
    252. 

  252. 

  253. #define BFIN_PF_IRQ(x)		((x) + IRQ_PE15 + 1)
    254. 

  254. #define IRQ_PF0			BFIN_PF_IRQ(0)
    255. 

  255. #define IRQ_PF1			BFIN_PF_IRQ(1)
    256. 

  256. #define IRQ_PF2			BFIN_PF_IRQ(2)
    257. 

  257. #define IRQ_PF3			BFIN_PF_IRQ(3)
    258. 

  258. #define IRQ_PF4			BFIN_PF_IRQ(4)
    259. 

  259. #define IRQ_PF5			BFIN_PF_IRQ(5)
    260. 

  260. #define IRQ_PF6			BFIN_PF_IRQ(6)
    261. 

  261. #define IRQ_PF7			BFIN_PF_IRQ(7)
    262. 

  262. #define IRQ_PF8			BFIN_PF_IRQ(8)
    263. 

  263. #define IRQ_PF9			BFIN_PF_IRQ(9)
    264. 

  264. #define IRQ_PF10		BFIN_PF_IRQ(10)
    265. 

  265. #define IRQ_PF11		BFIN_PF_IRQ(11)
    266. 

  266. #define IRQ_PF12		BFIN_PF_IRQ(12)
    267. 

  267. #define IRQ_PF13		BFIN_PF_IRQ(13)
    268. 

  268. #define IRQ_PF14		BFIN_PF_IRQ(14)
    269. 

  269. #define IRQ_PF15		BFIN_PF_IRQ(15)
    270. 

  270. 

  271. #define BFIN_PG_IRQ(x)		((x) + IRQ_PF15 + 1)
    272. 

  272. #define IRQ_PG0			BFIN_PG_IRQ(0)
    273. 

  273. #define IRQ_PG1			BFIN_PG_IRQ(1)
    274. 

  274. #define IRQ_PG2			BFIN_PG_IRQ(2)
    275. 

  275. #define IRQ_PG3			BFIN_PG_IRQ(3)
    276. 

  276. #define IRQ_PG4			BFIN_PG_IRQ(4)
    277. 

  277. #define IRQ_PG5			BFIN_PG_IRQ(5)
    278. 

  278. #define IRQ_PG6			BFIN_PG_IRQ(6)
    279. 

  279. #define IRQ_PG7			BFIN_PG_IRQ(7)
    280. 

  280. #define IRQ_PG8			BFIN_PG_IRQ(8)
    281. 

  281. #define IRQ_PG9			BFIN_PG_IRQ(9)
    282. 

  282. #define IRQ_PG10		BFIN_PG_IRQ(10)
    283. 

  283. #define IRQ_PG11		BFIN_PG_IRQ(11)
    284. 

  284. #define IRQ_PG12		BFIN_PG_IRQ(12)
    285. 

  285. #define IRQ_PG13		BFIN_PG_IRQ(13)
    286. 

  286. #define IRQ_PG14		BFIN_PG_IRQ(14)
    287. 

  287. #define IRQ_PG15		BFIN_PG_IRQ(15)
    288. 

  288. 

  289. #define GPIO_IRQ_BASE		IRQ_PA0
    290. 

  290. 

  291. #define NR_MACH_IRQS		(IRQ_PG15 + 1)
    292. 

  292. 

  293. #define SEC_SCTL_PRIO_OFFSET	8
    294. 

  294. 

  295. #ifndef __ASSEMBLY__
    296. 

  296. #include <linux/types.h>
    297. 

  297. 

  298. extern u8 sec_int_priority[];
    299. 

  299. 

  300. /*
    301. 

  301.  * gpio pint registers layout
    302. 

  302.  */
    303. 

  303. struct bfin_pint_regs {
    304. 

  304. 	u32 mask_set;
    305. 

  305. 	u32 mask_clear;
    306. 

  306. 	u32 request;
    307. 

  307. 	u32 assign;
    308. 

  308. 	u32 edge_set;
    309. 

  309. 	u32 edge_clear;
    310. 

  310. 	u32 invert_set;
    311. 

  311. 	u32 invert_clear;
    312. 

  312. 	u32 pinstate;
    313. 

  313. 	u32 latch;
    314. 

  314. 	u32 __pad0[2];
    315. 

  315. };
    316. 

  316. 

  317. #endif
    318. 

  318. 

  319. #endif
    320. 

  320.