pv-fixup-asm.S 2.0 KB

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  1. /*
  2. * Copyright (C) 2015 Russell King
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * This assembly is required to safely remap the physical address space
  9. * for Keystone 2
  10. */
  11. #include <linux/linkage.h>
  12. #include <asm/asm-offsets.h>
  13. #include <asm/cp15.h>
  14. #include <asm/memory.h>
  15. #include <asm/pgtable.h>
  16. .section ".idmap.text", "ax"
  17. #define L1_ORDER 3
  18. #define L2_ORDER 3
  19. ENTRY(lpae_pgtables_remap_asm)
  20. stmfd sp!, {r4-r8, lr}
  21. mrc p15, 0, r8, c1, c0, 0 @ read control reg
  22. bic ip, r8, #CR_M @ disable caches and MMU
  23. mcr p15, 0, ip, c1, c0, 0
  24. dsb
  25. isb
  26. /* Update level 2 entries covering the kernel */
  27. ldr r6, =(_end - 1)
  28. add r7, r2, #0x1000
  29. add r6, r7, r6, lsr #SECTION_SHIFT - L2_ORDER
  30. add r7, r7, #PAGE_OFFSET >> (SECTION_SHIFT - L2_ORDER)
  31. 1: ldrd r4, [r7]
  32. adds r4, r4, r0
  33. adc r5, r5, r1
  34. strd r4, [r7], #1 << L2_ORDER
  35. cmp r7, r6
  36. bls 1b
  37. /* Update level 2 entries for the boot data */
  38. add r7, r2, #0x1000
  39. add r7, r7, r3, lsr #SECTION_SHIFT - L2_ORDER
  40. bic r7, r7, #(1 << L2_ORDER) - 1
  41. ldrd r4, [r7]
  42. adds r4, r4, r0
  43. adc r5, r5, r1
  44. strd r4, [r7], #1 << L2_ORDER
  45. ldrd r4, [r7]
  46. adds r4, r4, r0
  47. adc r5, r5, r1
  48. strd r4, [r7]
  49. /* Update level 1 entries */
  50. mov r6, #4
  51. mov r7, r2
  52. 2: ldrd r4, [r7]
  53. adds r4, r4, r0
  54. adc r5, r5, r1
  55. strd r4, [r7], #1 << L1_ORDER
  56. subs r6, r6, #1
  57. bne 2b
  58. mrrc p15, 0, r4, r5, c2 @ read TTBR0
  59. adds r4, r4, r0 @ update physical address
  60. adc r5, r5, r1
  61. mcrr p15, 0, r4, r5, c2 @ write back TTBR0
  62. mrrc p15, 1, r4, r5, c2 @ read TTBR1
  63. adds r4, r4, r0 @ update physical address
  64. adc r5, r5, r1
  65. mcrr p15, 1, r4, r5, c2 @ write back TTBR1
  66. dsb
  67. mov ip, #0
  68. mcr p15, 0, ip, c7, c5, 0 @ I+BTB cache invalidate
  69. mcr p15, 0, ip, c8, c7, 0 @ local_flush_tlb_all()
  70. dsb
  71. isb
  72. mcr p15, 0, r8, c1, c0, 0 @ re-enable MMU
  73. dsb
  74. isb
  75. ldmfd sp!, {r4-r8, pc}
  76. ENDPROC(lpae_pgtables_remap_asm)