sleep.S 2.2 KB

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  1. /* linux/arch/arm/plat-s3c24xx/sleep.S
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 Power Manager (Suspend-To-RAM) support
  7. *
  8. * Based on PXA/SA1100 sleep code by:
  9. * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
  10. * Cliff Brake, (c) 2001
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  25. */
  26. #include <linux/linkage.h>
  27. #include <linux/serial_s3c.h>
  28. #include <asm/assembler.h>
  29. #include <mach/hardware.h>
  30. #include <mach/map.h>
  31. #include <mach/regs-gpio.h>
  32. #include <mach/regs-clock.h>
  33. /* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
  34. * reset the UART configuration, only enable if you really need this!
  35. */
  36. //#define CONFIG_DEBUG_RESUME
  37. .text
  38. /* sleep magic, to allow the bootloader to check for an valid
  39. * image to resume to. Must be the first word before the
  40. * s3c_cpu_resume entry.
  41. */
  42. .word 0x2bedf00d
  43. /* s3c_cpu_resume
  44. *
  45. * resume code entry for bootloader to call
  46. */
  47. ENTRY(s3c_cpu_resume)
  48. mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
  49. msr cpsr_c, r0
  50. @@ load UART to allow us to print the two characters for
  51. @@ resume debug
  52. mov r2, #S3C24XX_PA_UART & 0xff000000
  53. orr r2, r2, #S3C24XX_PA_UART & 0xff000
  54. #if 0
  55. /* SMDK2440 LED set */
  56. mov r14, #S3C24XX_PA_GPIO
  57. ldr r12, [ r14, #0x54 ]
  58. bic r12, r12, #3<<4
  59. orr r12, r12, #1<<7
  60. str r12, [ r14, #0x54 ]
  61. #endif
  62. #ifdef CONFIG_DEBUG_RESUME
  63. mov r3, #'L'
  64. strb r3, [ r2, #S3C2410_UTXH ]
  65. 1001:
  66. ldrb r14, [ r3, #S3C2410_UTRSTAT ]
  67. tst r14, #S3C2410_UTRSTAT_TXE
  68. beq 1001b
  69. #endif /* CONFIG_DEBUG_RESUME */
  70. b cpu_resume