Startsida Utforska Hjälp
Logga in
phreedom2600net
/
linux-libre
Bevaka 2
Stjärnmärk 0
Fork 0
Filer Ärenden 0 Pull-förfrågningar 0 Wiki
Gren: audiocape
Grenar Taggar
linux-libre
/
arch
/
arm
/
mach-omap2
/
cm1_7xx.h

cm1_7xx.h 19 KB
Permalänk Historik Rå

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323 
  1. /*
    2. 

  2.  * DRA7xx CM1 instance offset macros
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
    5. 

  5.  *
    6. 

  6.  * Generated by code originally written by:
    7. 

  7.  * Paul Walmsley (paul@pwsan.com)
    8. 

  8.  * Rajendra Nayak (rnayak@ti.com)
    9. 

  9.  * Benoit Cousson (b-cousson@ti.com)
    10. 

  10.  *
    11. 

  11.  * This file is automatically generated from the OMAP hardware databases.
    12. 

  12.  * We respectfully ask that any modifications to this file be coordinated
    13. 

  13.  * with the public linux-omap@vger.kernel.org mailing list and the
    14. 

  14.  * authors above to ensure that the autogeneration scripts are kept
    15. 

  15.  * up-to-date with the file contents.
    16. 

  16.  *
    17. 

  17.  * This program is free software; you can redistribute it and/or modify
    18. 

  18.  * it under the terms of the GNU General Public License version 2 as
    19. 

  19.  * published by the Free Software Foundation.
    20. 

  20.  *
    21. 

  21.  */
    22. 

  22. 

  23. #ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
    24. 

  24. #define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
    25. 

  25. 

  26. /* CM1 base address */
    27. 

  27. #define DRA7XX_CM_CORE_AON_BASE		0x4a005000
    28. 

  28. 

  29. #define DRA7XX_CM_CORE_AON_REGADDR(inst, reg)				\
    30. 

  30. 	OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
    31. 

  31. 

  32. /* CM_CORE_AON instances */
    33. 

  33. #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST	0x0000
    34. 

  34. #define DRA7XX_CM_CORE_AON_CKGEN_INST		0x0100
    35. 

  35. #define DRA7XX_CM_CORE_AON_MPU_INST		0x0300
    36. 

  36. #define DRA7XX_CM_CORE_AON_DSP1_INST		0x0400
    37. 

  37. #define DRA7XX_CM_CORE_AON_IPU_INST		0x0500
    38. 

  38. #define DRA7XX_CM_CORE_AON_DSP2_INST		0x0600
    39. 

  39. #define DRA7XX_CM_CORE_AON_EVE1_INST		0x0640
    40. 

  40. #define DRA7XX_CM_CORE_AON_EVE2_INST		0x0680
    41. 

  41. #define DRA7XX_CM_CORE_AON_EVE3_INST		0x06c0
    42. 

  42. #define DRA7XX_CM_CORE_AON_EVE4_INST		0x0700
    43. 

  43. #define DRA7XX_CM_CORE_AON_RTC_INST		0x0740
    44. 

  44. #define DRA7XX_CM_CORE_AON_VPE_INST		0x0760
    45. 

  45. #define DRA7XX_CM_CORE_AON_RESTORE_INST		0x0e00
    46. 

  46. #define DRA7XX_CM_CORE_AON_INSTR_INST		0x0f00
    47. 

  47. 

  48. /* CM_CORE_AON clockdomain register offsets (from instance start) */
    49. 

  49. #define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS	0x0000
    50. 

  50. #define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS	0x0000
    51. 

  51. #define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS	0x0000
    52. 

  52. #define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS	0x0040
    53. 

  53. #define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS	0x0000
    54. 

  54. #define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS	0x0000
    55. 

  55. #define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS	0x0000
    56. 

  56. #define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS	0x0000
    57. 

  57. #define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS	0x0000
    58. 

  58. #define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS	0x0000
    59. 

  59. #define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS	0x0000
    60. 

  60. 

  61. /* CM_CORE_AON */
    62. 

  62. 

  63. /* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
    64. 

  64. #define DRA7XX_REVISION_CM_CORE_AON_OFFSET		0x0000
    65. 

  65. #define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET	0x0040
    66. 

  66. #define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL		DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
    67. 

  67. #define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET		0x00ec
    68. 

  68. #define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET		0x00f0
    69. 

  69. #define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET		0x00f4
    70. 

  70. #define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET		0x00f8
    71. 

  71. #define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET		0x00fc
    72. 

  72. 

  73. /* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
    74. 

  74. #define DRA7XX_CM_CLKSEL_CORE_OFFSET			0x0000
    75. 

  75. #define DRA7XX_CM_CLKSEL_CORE				DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000)
    76. 

  76. #define DRA7XX_CM_CLKSEL_ABE_OFFSET			0x0008
    77. 

  77. #define DRA7XX_CM_CLKSEL_ABE				DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008)
    78. 

  78. #define DRA7XX_CM_DLL_CTRL_OFFSET			0x0010
    79. 

  79. #define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET		0x0020
    80. 

  80. #define DRA7XX_CM_CLKMODE_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020)
    81. 

  81. #define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET		0x0024
    82. 

  82. #define DRA7XX_CM_IDLEST_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024)
    83. 

  83. #define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET		0x0028
    84. 

  84. #define DRA7XX_CM_AUTOIDLE_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028)
    85. 

  85. #define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET		0x002c
    86. 

  86. #define DRA7XX_CM_CLKSEL_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c)
    87. 

  87. #define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET		0x0030
    88. 

  88. #define DRA7XX_CM_DIV_M2_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030)
    89. 

  89. #define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET		0x0034
    90. 

  90. #define DRA7XX_CM_DIV_M3_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034)
    91. 

  91. #define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET		0x0038
    92. 

  92. #define DRA7XX_CM_DIV_H11_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038)
    93. 

  93. #define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET		0x003c
    94. 

  94. #define DRA7XX_CM_DIV_H12_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c)
    95. 

  95. #define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET		0x0040
    96. 

  96. #define DRA7XX_CM_DIV_H13_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040)
    97. 

  97. #define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET		0x0044
    98. 

  98. #define DRA7XX_CM_DIV_H14_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044)
    99. 

  99. #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET	0x0048
    100. 

  100. #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET	0x004c
    101. 

  101. #define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET		0x0050
    102. 

  102. #define DRA7XX_CM_DIV_H21_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050)
    103. 

  103. #define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET		0x0054
    104. 

  104. #define DRA7XX_CM_DIV_H22_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054)
    105. 

  105. #define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET		0x0058
    106. 

  106. #define DRA7XX_CM_DIV_H23_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058)
    107. 

  107. #define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET		0x005c
    108. 

  108. #define DRA7XX_CM_DIV_H24_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c)
    109. 

  109. #define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET		0x0060
    110. 

  110. #define DRA7XX_CM_CLKMODE_DPLL_MPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060)
    111. 

  111. #define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET		0x0064
    112. 

  112. #define DRA7XX_CM_IDLEST_DPLL_MPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064)
    113. 

  113. #define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET		0x0068
    114. 

  114. #define DRA7XX_CM_AUTOIDLE_DPLL_MPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068)
    115. 

  115. #define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET		0x006c
    116. 

  116. #define DRA7XX_CM_CLKSEL_DPLL_MPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c)
    117. 

  117. #define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET		0x0070
    118. 

  118. #define DRA7XX_CM_DIV_M2_DPLL_MPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070)
    119. 

  119. #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET	0x0088
    120. 

  120. #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET	0x008c
    121. 

  121. #define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET		0x009c
    122. 

  122. #define DRA7XX_CM_BYPCLK_DPLL_MPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c)
    123. 

  123. #define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET		0x00a0
    124. 

  124. #define DRA7XX_CM_CLKMODE_DPLL_IVA			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
    125. 

  125. #define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET		0x00a4
    126. 

  126. #define DRA7XX_CM_IDLEST_DPLL_IVA			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
    127. 

  127. #define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET		0x00a8
    128. 

  128. #define DRA7XX_CM_AUTOIDLE_DPLL_IVA			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
    129. 

  129. #define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET		0x00ac
    130. 

  130. #define DRA7XX_CM_CLKSEL_DPLL_IVA			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
    131. 

  131. #define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET		0x00b0
    132. 

  132. #define DRA7XX_CM_DIV_M2_DPLL_IVA			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0)
    133. 

  133. #define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET		0x00b4
    134. 

  134. #define DRA7XX_CM_DIV_M3_DPLL_IVA			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4)
    135. 

  135. #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET	0x00c8
    136. 

  136. #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET	0x00cc
    137. 

  137. #define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET		0x00dc
    138. 

  138. #define DRA7XX_CM_BYPCLK_DPLL_IVA			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
    139. 

  139. #define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET		0x00e0
    140. 

  140. #define DRA7XX_CM_CLKMODE_DPLL_ABE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
    141. 

  141. #define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET		0x00e4
    142. 

  142. #define DRA7XX_CM_IDLEST_DPLL_ABE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
    143. 

  143. #define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET		0x00e8
    144. 

  144. #define DRA7XX_CM_AUTOIDLE_DPLL_ABE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
    145. 

  145. #define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET		0x00ec
    146. 

  146. #define DRA7XX_CM_CLKSEL_DPLL_ABE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
    147. 

  147. #define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET		0x00f0
    148. 

  148. #define DRA7XX_CM_DIV_M2_DPLL_ABE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
    149. 

  149. #define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET		0x00f4
    150. 

  150. #define DRA7XX_CM_DIV_M3_DPLL_ABE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
    151. 

  151. #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET	0x0108
    152. 

  152. #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET	0x010c
    153. 

  153. #define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET		0x0110
    154. 

  154. #define DRA7XX_CM_CLKMODE_DPLL_DDR			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110)
    155. 

  155. #define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET		0x0114
    156. 

  156. #define DRA7XX_CM_IDLEST_DPLL_DDR			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114)
    157. 

  157. #define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET		0x0118
    158. 

  158. #define DRA7XX_CM_AUTOIDLE_DPLL_DDR			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118)
    159. 

  159. #define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET		0x011c
    160. 

  160. #define DRA7XX_CM_CLKSEL_DPLL_DDR			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c)
    161. 

  161. #define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET		0x0120
    162. 

  162. #define DRA7XX_CM_DIV_M2_DPLL_DDR			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120)
    163. 

  163. #define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET		0x0124
    164. 

  164. #define DRA7XX_CM_DIV_M3_DPLL_DDR			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124)
    165. 

  165. #define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET		0x0128
    166. 

  166. #define DRA7XX_CM_DIV_H11_DPLL_DDR			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128)
    167. 

  167. #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET	0x012c
    168. 

  168. #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET	0x0130
    169. 

  169. #define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET		0x0134
    170. 

  170. #define DRA7XX_CM_CLKMODE_DPLL_DSP			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134)
    171. 

  171. #define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET		0x0138
    172. 

  172. #define DRA7XX_CM_IDLEST_DPLL_DSP			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138)
    173. 

  173. #define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET		0x013c
    174. 

  174. #define DRA7XX_CM_AUTOIDLE_DPLL_DSP			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c)
    175. 

  175. #define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET		0x0140
    176. 

  176. #define DRA7XX_CM_CLKSEL_DPLL_DSP			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140)
    177. 

  177. #define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET		0x0144
    178. 

  178. #define DRA7XX_CM_DIV_M2_DPLL_DSP			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144)
    179. 

  179. #define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET		0x0148
    180. 

  180. #define DRA7XX_CM_DIV_M3_DPLL_DSP			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148)
    181. 

  181. #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET	0x014c
    182. 

  182. #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET	0x0150
    183. 

  183. #define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET		0x0154
    184. 

  184. #define DRA7XX_CM_BYPCLK_DPLL_DSP			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154)
    185. 

  185. #define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET		0x0160
    186. 

  186. #define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET		0x0164
    187. 

  187. #define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET		0x0170
    188. 

  188. #define DRA7XX_CM_RESTORE_ST_OFFSET			0x0180
    189. 

  189. #define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET		0x0184
    190. 

  190. #define DRA7XX_CM_CLKMODE_DPLL_EVE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184)
    191. 

  191. #define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET		0x0188
    192. 

  192. #define DRA7XX_CM_IDLEST_DPLL_EVE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188)
    193. 

  193. #define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET		0x018c
    194. 

  194. #define DRA7XX_CM_AUTOIDLE_DPLL_EVE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c)
    195. 

  195. #define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET		0x0190
    196. 

  196. #define DRA7XX_CM_CLKSEL_DPLL_EVE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190)
    197. 

  197. #define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET		0x0194
    198. 

  198. #define DRA7XX_CM_DIV_M2_DPLL_EVE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194)
    199. 

  199. #define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET		0x0198
    200. 

  200. #define DRA7XX_CM_DIV_M3_DPLL_EVE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198)
    201. 

  201. #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET	0x019c
    202. 

  202. #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET	0x01a0
    203. 

  203. #define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET		0x01a4
    204. 

  204. #define DRA7XX_CM_BYPCLK_DPLL_EVE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4)
    205. 

  205. #define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET		0x01a8
    206. 

  206. #define DRA7XX_CM_CLKMODE_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8)
    207. 

  207. #define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET		0x01ac
    208. 

  208. #define DRA7XX_CM_IDLEST_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac)
    209. 

  209. #define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET		0x01b0
    210. 

  210. #define DRA7XX_CM_AUTOIDLE_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0)
    211. 

  211. #define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET		0x01b4
    212. 

  212. #define DRA7XX_CM_CLKSEL_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4)
    213. 

  213. #define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET		0x01b8
    214. 

  214. #define DRA7XX_CM_DIV_M2_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8)
    215. 

  215. #define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET		0x01bc
    216. 

  216. #define DRA7XX_CM_DIV_M3_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc)
    217. 

  217. #define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET		0x01c0
    218. 

  218. #define DRA7XX_CM_DIV_H11_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0)
    219. 

  219. #define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET		0x01c4
    220. 

  220. #define DRA7XX_CM_DIV_H12_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4)
    221. 

  221. #define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET		0x01c8
    222. 

  222. #define DRA7XX_CM_DIV_H13_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8)
    223. 

  223. #define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET		0x01cc
    224. 

  224. #define DRA7XX_CM_DIV_H14_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc)
    225. 

  225. #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET	0x01d0
    226. 

  226. #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET	0x01d4
    227. 

  227. #define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET		0x01d8
    228. 

  228. #define DRA7XX_CM_CLKMODE_DPLL_GPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8)
    229. 

  229. #define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET		0x01dc
    230. 

  230. #define DRA7XX_CM_IDLEST_DPLL_GPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc)
    231. 

  231. #define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET		0x01e0
    232. 

  232. #define DRA7XX_CM_AUTOIDLE_DPLL_GPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0)
    233. 

  233. #define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET		0x01e4
    234. 

  234. #define DRA7XX_CM_CLKSEL_DPLL_GPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4)
    235. 

  235. #define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET		0x01e8
    236. 

  236. #define DRA7XX_CM_DIV_M2_DPLL_GPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8)
    237. 

  237. #define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET		0x01ec
    238. 

  238. #define DRA7XX_CM_DIV_M3_DPLL_GPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec)
    239. 

  239. #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET	0x01f0
    240. 

  240. #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET	0x01f4
    241. 

  241. 

  242. /* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
    243. 

  243. #define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET			0x0000
    244. 

  244. #define DRA7XX_CM_MPU_STATICDEP_OFFSET			0x0004
    245. 

  245. #define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET			0x0008
    246. 

  246. #define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET		0x0020
    247. 

  247. #define DRA7XX_CM_MPU_MPU_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020)
    248. 

  248. #define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET	0x0028
    249. 

  249. #define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL		DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028)
    250. 

  250. 

  251. /* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */
    252. 

  252. #define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET			0x0000
    253. 

  253. #define DRA7XX_CM_DSP1_STATICDEP_OFFSET			0x0004
    254. 

  254. #define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET		0x0008
    255. 

  255. #define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET		0x0020
    256. 

  256. #define DRA7XX_CM_DSP1_DSP1_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020)
    257. 

  257. 

  258. /* CM_CORE_AON.IPU_CM_CORE_AON register offsets */
    259. 

  259. #define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET			0x0000
    260. 

  260. #define DRA7XX_CM_IPU1_STATICDEP_OFFSET			0x0004
    261. 

  261. #define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET		0x0008
    262. 

  262. #define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET		0x0020
    263. 

  263. #define DRA7XX_CM_IPU1_IPU1_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020)
    264. 

  264. #define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET			0x0040
    265. 

  265. #define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET		0x0050
    266. 

  266. #define DRA7XX_CM_IPU_MCASP1_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050)
    267. 

  267. #define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET		0x0058
    268. 

  268. #define DRA7XX_CM_IPU_TIMER5_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058)
    269. 

  269. #define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET		0x0060
    270. 

  270. #define DRA7XX_CM_IPU_TIMER6_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060)
    271. 

  271. #define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET		0x0068
    272. 

  272. #define DRA7XX_CM_IPU_TIMER7_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068)
    273. 

  273. #define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET		0x0070
    274. 

  274. #define DRA7XX_CM_IPU_TIMER8_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070)
    275. 

  275. #define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET		0x0078
    276. 

  276. #define DRA7XX_CM_IPU_I2C5_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078)
    277. 

  277. #define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET		0x0080
    278. 

  278. #define DRA7XX_CM_IPU_UART6_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080)
    279. 

  279. 

  280. /* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */
    281. 

  281. #define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET			0x0000
    282. 

  282. #define DRA7XX_CM_DSP2_STATICDEP_OFFSET			0x0004
    283. 

  283. #define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET		0x0008
    284. 

  284. #define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET		0x0020
    285. 

  285. #define DRA7XX_CM_DSP2_DSP2_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020)
    286. 

  286. 

  287. /* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */
    288. 

  288. #define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET			0x0000
    289. 

  289. #define DRA7XX_CM_EVE1_STATICDEP_OFFSET			0x0004
    290. 

  290. #define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET		0x0020
    291. 

  291. #define DRA7XX_CM_EVE1_EVE1_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020)
    292. 

  292. 

  293. /* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */
    294. 

  294. #define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET			0x0000
    295. 

  295. #define DRA7XX_CM_EVE2_STATICDEP_OFFSET			0x0004
    296. 

  296. #define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET		0x0020
    297. 

  297. #define DRA7XX_CM_EVE2_EVE2_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020)
    298. 

  298. 

  299. /* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */
    300. 

  300. #define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET			0x0000
    301. 

  301. #define DRA7XX_CM_EVE3_STATICDEP_OFFSET			0x0004
    302. 

  302. #define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET		0x0020
    303. 

  303. #define DRA7XX_CM_EVE3_EVE3_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020)
    304. 

  304. 

  305. /* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */
    306. 

  306. #define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET			0x0000
    307. 

  307. #define DRA7XX_CM_EVE4_STATICDEP_OFFSET			0x0004
    308. 

  308. #define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET		0x0020
    309. 

  309. #define DRA7XX_CM_EVE4_EVE4_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020)
    310. 

  310. 

  311. /* CM_CORE_AON.RTC_CM_CORE_AON register offsets */
    312. 

  312. #define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET			0x0000
    313. 

  313. #define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET		0x0004
    314. 

  314. #define DRA7XX_CM_RTC_RTCSS_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004)
    315. 

  315. 

  316. /* CM_CORE_AON.VPE_CM_CORE_AON register offsets */
    317. 

  317. #define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET			0x0000
    318. 

  318. #define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET		0x0004
    319. 

  319. #define DRA7XX_CM_VPE_VPE_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004)
    320. 

  320. #define DRA7XX_CM_VPE_STATICDEP_OFFSET			0x0008
    321. 

  321. 

  322. #endif
    323. 

  323.