devices.c 8.2 KB

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  1. /*
  2. * linux/arch/arm/mach-mmp/devices.c
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/init.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/delay.h>
  12. #include <asm/irq.h>
  13. #include "irqs.h"
  14. #include "devices.h"
  15. #include "cputype.h"
  16. #include "regs-usb.h"
  17. int __init pxa_register_device(struct pxa_device_desc *desc,
  18. void *data, size_t size)
  19. {
  20. struct platform_device *pdev;
  21. struct resource res[2 + MAX_RESOURCE_DMA];
  22. int i, ret = 0, nres = 0;
  23. pdev = platform_device_alloc(desc->drv_name, desc->id);
  24. if (pdev == NULL)
  25. return -ENOMEM;
  26. pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
  27. memset(res, 0, sizeof(res));
  28. if (desc->start != -1ul && desc->size > 0) {
  29. res[nres].start = desc->start;
  30. res[nres].end = desc->start + desc->size - 1;
  31. res[nres].flags = IORESOURCE_MEM;
  32. nres++;
  33. }
  34. if (desc->irq != NO_IRQ) {
  35. res[nres].start = desc->irq;
  36. res[nres].end = desc->irq;
  37. res[nres].flags = IORESOURCE_IRQ;
  38. nres++;
  39. }
  40. for (i = 0; i < MAX_RESOURCE_DMA; i++, nres++) {
  41. if (desc->dma[i] == 0)
  42. break;
  43. res[nres].start = desc->dma[i];
  44. res[nres].end = desc->dma[i];
  45. res[nres].flags = IORESOURCE_DMA;
  46. }
  47. ret = platform_device_add_resources(pdev, res, nres);
  48. if (ret) {
  49. platform_device_put(pdev);
  50. return ret;
  51. }
  52. if (data && size) {
  53. ret = platform_device_add_data(pdev, data, size);
  54. if (ret) {
  55. platform_device_put(pdev);
  56. return ret;
  57. }
  58. }
  59. return platform_device_add(pdev);
  60. }
  61. #if IS_ENABLED(CONFIG_USB) || IS_ENABLED(CONFIG_USB_GADGET)
  62. #if IS_ENABLED(CONFIG_USB_MV_UDC) || IS_ENABLED(CONFIG_USB_EHCI_MV)
  63. #if IS_ENABLED(CONFIG_CPU_PXA910) || IS_ENABLED(CONFIG_CPU_PXA168)
  64. /*****************************************************************************
  65. * The registers read/write routines
  66. *****************************************************************************/
  67. static unsigned int u2o_get(void __iomem *base, unsigned int offset)
  68. {
  69. return readl_relaxed(base + offset);
  70. }
  71. static void u2o_set(void __iomem *base, unsigned int offset,
  72. unsigned int value)
  73. {
  74. u32 reg;
  75. reg = readl_relaxed(base + offset);
  76. reg |= value;
  77. writel_relaxed(reg, base + offset);
  78. readl_relaxed(base + offset);
  79. }
  80. static void u2o_clear(void __iomem *base, unsigned int offset,
  81. unsigned int value)
  82. {
  83. u32 reg;
  84. reg = readl_relaxed(base + offset);
  85. reg &= ~value;
  86. writel_relaxed(reg, base + offset);
  87. readl_relaxed(base + offset);
  88. }
  89. static void u2o_write(void __iomem *base, unsigned int offset,
  90. unsigned int value)
  91. {
  92. writel_relaxed(value, base + offset);
  93. readl_relaxed(base + offset);
  94. }
  95. static DEFINE_MUTEX(phy_lock);
  96. static int phy_init_cnt;
  97. static int usb_phy_init_internal(void __iomem *base)
  98. {
  99. int loops;
  100. pr_info("Init usb phy!!!\n");
  101. /* Initialize the USB PHY power */
  102. if (cpu_is_pxa910()) {
  103. u2o_set(base, UTMI_CTRL, (1<<UTMI_CTRL_INPKT_DELAY_SOF_SHIFT)
  104. | (1<<UTMI_CTRL_PU_REF_SHIFT));
  105. }
  106. u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
  107. u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
  108. /* UTMI_PLL settings */
  109. u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK
  110. | UTMI_PLL_PLLVDD12_MASK | UTMI_PLL_PLLCALI12_MASK
  111. | UTMI_PLL_FBDIV_MASK | UTMI_PLL_REFDIV_MASK
  112. | UTMI_PLL_ICP_MASK | UTMI_PLL_KVCO_MASK);
  113. u2o_set(base, UTMI_PLL, 0xee<<UTMI_PLL_FBDIV_SHIFT
  114. | 0xb<<UTMI_PLL_REFDIV_SHIFT | 3<<UTMI_PLL_PLLVDD18_SHIFT
  115. | 3<<UTMI_PLL_PLLVDD12_SHIFT | 3<<UTMI_PLL_PLLCALI12_SHIFT
  116. | 1<<UTMI_PLL_ICP_SHIFT | 3<<UTMI_PLL_KVCO_SHIFT);
  117. /* UTMI_TX */
  118. u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK
  119. | UTMI_TX_TXVDD12_MASK | UTMI_TX_CK60_PHSEL_MASK
  120. | UTMI_TX_IMPCAL_VTH_MASK | UTMI_TX_REG_EXT_FS_RCAL_MASK
  121. | UTMI_TX_AMP_MASK);
  122. u2o_set(base, UTMI_TX, 3<<UTMI_TX_TXVDD12_SHIFT
  123. | 4<<UTMI_TX_CK60_PHSEL_SHIFT | 4<<UTMI_TX_IMPCAL_VTH_SHIFT
  124. | 8<<UTMI_TX_REG_EXT_FS_RCAL_SHIFT | 3<<UTMI_TX_AMP_SHIFT);
  125. /* UTMI_RX */
  126. u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK
  127. | UTMI_REG_SQ_LENGTH_MASK);
  128. u2o_set(base, UTMI_RX, 7<<UTMI_RX_SQ_THRESH_SHIFT
  129. | 2<<UTMI_REG_SQ_LENGTH_SHIFT);
  130. /* UTMI_IVREF */
  131. if (cpu_is_pxa168())
  132. /* fixing Microsoft Altair board interface with NEC hub issue -
  133. * Set UTMI_IVREF from 0x4a3 to 0x4bf */
  134. u2o_write(base, UTMI_IVREF, 0x4bf);
  135. /* toggle VCOCAL_START bit of UTMI_PLL */
  136. udelay(200);
  137. u2o_set(base, UTMI_PLL, VCOCAL_START);
  138. udelay(40);
  139. u2o_clear(base, UTMI_PLL, VCOCAL_START);
  140. /* toggle REG_RCAL_START bit of UTMI_TX */
  141. udelay(400);
  142. u2o_set(base, UTMI_TX, REG_RCAL_START);
  143. udelay(40);
  144. u2o_clear(base, UTMI_TX, REG_RCAL_START);
  145. udelay(400);
  146. /* Make sure PHY PLL is ready */
  147. loops = 0;
  148. while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) {
  149. mdelay(1);
  150. loops++;
  151. if (loops > 100) {
  152. printk(KERN_WARNING "calibrate timeout, UTMI_PLL %x\n",
  153. u2o_get(base, UTMI_PLL));
  154. break;
  155. }
  156. }
  157. if (cpu_is_pxa168()) {
  158. u2o_set(base, UTMI_RESERVE, 1 << 5);
  159. /* Turn on UTMI PHY OTG extension */
  160. u2o_write(base, UTMI_OTG_ADDON, 1);
  161. }
  162. return 0;
  163. }
  164. static int usb_phy_deinit_internal(void __iomem *base)
  165. {
  166. pr_info("Deinit usb phy!!!\n");
  167. if (cpu_is_pxa168())
  168. u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON);
  169. u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN);
  170. u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN);
  171. u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN);
  172. u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
  173. u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
  174. return 0;
  175. }
  176. int pxa_usb_phy_init(void __iomem *phy_reg)
  177. {
  178. mutex_lock(&phy_lock);
  179. if (phy_init_cnt++ == 0)
  180. usb_phy_init_internal(phy_reg);
  181. mutex_unlock(&phy_lock);
  182. return 0;
  183. }
  184. void pxa_usb_phy_deinit(void __iomem *phy_reg)
  185. {
  186. WARN_ON(phy_init_cnt == 0);
  187. mutex_lock(&phy_lock);
  188. if (--phy_init_cnt == 0)
  189. usb_phy_deinit_internal(phy_reg);
  190. mutex_unlock(&phy_lock);
  191. }
  192. #endif
  193. #endif
  194. #endif
  195. #if IS_ENABLED(CONFIG_USB_SUPPORT)
  196. static u64 usb_dma_mask = ~(u32)0;
  197. #if IS_ENABLED(CONFIG_USB_MV_UDC)
  198. struct resource pxa168_u2o_resources[] = {
  199. /* regbase */
  200. [0] = {
  201. .start = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
  202. .end = PXA168_U2O_REGBASE + USB_REG_RANGE,
  203. .flags = IORESOURCE_MEM,
  204. .name = "capregs",
  205. },
  206. /* phybase */
  207. [1] = {
  208. .start = PXA168_U2O_PHYBASE,
  209. .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
  210. .flags = IORESOURCE_MEM,
  211. .name = "phyregs",
  212. },
  213. [2] = {
  214. .start = IRQ_PXA168_USB1,
  215. .end = IRQ_PXA168_USB1,
  216. .flags = IORESOURCE_IRQ,
  217. },
  218. };
  219. struct platform_device pxa168_device_u2o = {
  220. .name = "mv-udc",
  221. .id = -1,
  222. .resource = pxa168_u2o_resources,
  223. .num_resources = ARRAY_SIZE(pxa168_u2o_resources),
  224. .dev = {
  225. .dma_mask = &usb_dma_mask,
  226. .coherent_dma_mask = 0xffffffff,
  227. }
  228. };
  229. #endif /* CONFIG_USB_MV_UDC */
  230. #if IS_ENABLED(CONFIG_USB_EHCI_MV_U2O)
  231. struct resource pxa168_u2oehci_resources[] = {
  232. /* regbase */
  233. [0] = {
  234. .start = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
  235. .end = PXA168_U2O_REGBASE + USB_REG_RANGE,
  236. .flags = IORESOURCE_MEM,
  237. .name = "capregs",
  238. },
  239. /* phybase */
  240. [1] = {
  241. .start = PXA168_U2O_PHYBASE,
  242. .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
  243. .flags = IORESOURCE_MEM,
  244. .name = "phyregs",
  245. },
  246. [2] = {
  247. .start = IRQ_PXA168_USB1,
  248. .end = IRQ_PXA168_USB1,
  249. .flags = IORESOURCE_IRQ,
  250. },
  251. };
  252. struct platform_device pxa168_device_u2oehci = {
  253. .name = "pxa-u2oehci",
  254. .id = -1,
  255. .dev = {
  256. .dma_mask = &usb_dma_mask,
  257. .coherent_dma_mask = 0xffffffff,
  258. },
  259. .num_resources = ARRAY_SIZE(pxa168_u2oehci_resources),
  260. .resource = pxa168_u2oehci_resources,
  261. };
  262. #endif
  263. #if IS_ENABLED(CONFIG_USB_MV_OTG)
  264. struct resource pxa168_u2ootg_resources[] = {
  265. /* regbase */
  266. [0] = {
  267. .start = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
  268. .end = PXA168_U2O_REGBASE + USB_REG_RANGE,
  269. .flags = IORESOURCE_MEM,
  270. .name = "capregs",
  271. },
  272. /* phybase */
  273. [1] = {
  274. .start = PXA168_U2O_PHYBASE,
  275. .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
  276. .flags = IORESOURCE_MEM,
  277. .name = "phyregs",
  278. },
  279. [2] = {
  280. .start = IRQ_PXA168_USB1,
  281. .end = IRQ_PXA168_USB1,
  282. .flags = IORESOURCE_IRQ,
  283. },
  284. };
  285. struct platform_device pxa168_device_u2ootg = {
  286. .name = "mv-otg",
  287. .id = -1,
  288. .dev = {
  289. .dma_mask = &usb_dma_mask,
  290. .coherent_dma_mask = 0xffffffff,
  291. },
  292. .num_resources = ARRAY_SIZE(pxa168_u2ootg_resources),
  293. .resource = pxa168_u2ootg_resources,
  294. };
  295. #endif /* CONFIG_USB_MV_OTG */
  296. #endif