zynq-zc706.dts 5.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316
  1. /*
  2. * Copyright (C) 2011 - 2014 Xilinx
  3. * Copyright (C) 2012 National Instruments Corp.
  4. *
  5. * This software is licensed under the terms of the GNU General Public
  6. * License version 2, as published by the Free Software Foundation, and
  7. * may be copied, distributed, and modified under those terms.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. /dts-v1/;
  15. /include/ "zynq-7000.dtsi"
  16. / {
  17. model = "Zynq ZC706 Development Board";
  18. compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
  19. aliases {
  20. ethernet0 = &gem0;
  21. i2c0 = &i2c0;
  22. serial0 = &uart1;
  23. };
  24. memory {
  25. device_type = "memory";
  26. reg = <0x0 0x40000000>;
  27. };
  28. chosen {
  29. bootargs = "earlycon";
  30. stdout-path = "serial0:115200n8";
  31. };
  32. usb_phy0: phy0 {
  33. compatible = "usb-nop-xceiv";
  34. #phy-cells = <0>;
  35. };
  36. };
  37. &clkc {
  38. ps-clk-frequency = <33333333>;
  39. };
  40. &gem0 {
  41. status = "okay";
  42. phy-mode = "rgmii-id";
  43. phy-handle = <&ethernet_phy>;
  44. pinctrl-names = "default";
  45. pinctrl-0 = <&pinctrl_gem0_default>;
  46. ethernet_phy: ethernet-phy@7 {
  47. reg = <7>;
  48. };
  49. };
  50. &gpio0 {
  51. pinctrl-names = "default";
  52. pinctrl-0 = <&pinctrl_gpio0_default>;
  53. };
  54. &i2c0 {
  55. status = "okay";
  56. clock-frequency = <400000>;
  57. pinctrl-names = "default";
  58. pinctrl-0 = <&pinctrl_i2c0_default>;
  59. i2cswitch@74 {
  60. compatible = "nxp,pca9548";
  61. #address-cells = <1>;
  62. #size-cells = <0>;
  63. reg = <0x74>;
  64. i2c@0 {
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. reg = <0>;
  68. si570: clock-generator@5d {
  69. #clock-cells = <0>;
  70. compatible = "silabs,si570";
  71. temperature-stability = <50>;
  72. reg = <0x5d>;
  73. factory-fout = <156250000>;
  74. clock-frequency = <148500000>;
  75. };
  76. };
  77. i2c@2 {
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. reg = <2>;
  81. eeprom@54 {
  82. compatible = "at,24c08";
  83. reg = <0x54>;
  84. };
  85. };
  86. i2c@3 {
  87. #address-cells = <1>;
  88. #size-cells = <0>;
  89. reg = <3>;
  90. gpio@21 {
  91. compatible = "ti,tca6416";
  92. reg = <0x21>;
  93. gpio-controller;
  94. #gpio-cells = <2>;
  95. };
  96. };
  97. i2c@4 {
  98. #address-cells = <1>;
  99. #size-cells = <0>;
  100. reg = <4>;
  101. rtc@51 {
  102. compatible = "nxp,pcf8563";
  103. reg = <0x51>;
  104. };
  105. };
  106. i2c@7 {
  107. #address-cells = <1>;
  108. #size-cells = <0>;
  109. reg = <7>;
  110. ucd90120@65 {
  111. compatible = "ti,ucd90120";
  112. reg = <0x65>;
  113. };
  114. };
  115. };
  116. };
  117. &pinctrl0 {
  118. pinctrl_gem0_default: gem0-default {
  119. mux {
  120. function = "ethernet0";
  121. groups = "ethernet0_0_grp";
  122. };
  123. conf {
  124. groups = "ethernet0_0_grp";
  125. slew-rate = <0>;
  126. io-standard = <4>;
  127. };
  128. conf-rx {
  129. pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
  130. bias-high-impedance;
  131. low-power-disable;
  132. };
  133. conf-tx {
  134. pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
  135. low-power-enable;
  136. bias-disable;
  137. };
  138. mux-mdio {
  139. function = "mdio0";
  140. groups = "mdio0_0_grp";
  141. };
  142. conf-mdio {
  143. groups = "mdio0_0_grp";
  144. slew-rate = <0>;
  145. io-standard = <1>;
  146. bias-disable;
  147. };
  148. };
  149. pinctrl_gpio0_default: gpio0-default {
  150. mux {
  151. function = "gpio0";
  152. groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
  153. };
  154. conf {
  155. groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
  156. slew-rate = <0>;
  157. io-standard = <1>;
  158. };
  159. conf-pull-up {
  160. pins = "MIO46", "MIO47";
  161. bias-pull-up;
  162. };
  163. conf-pull-none {
  164. pins = "MIO7";
  165. bias-disable;
  166. };
  167. };
  168. pinctrl_i2c0_default: i2c0-default {
  169. mux {
  170. groups = "i2c0_10_grp";
  171. function = "i2c0";
  172. };
  173. conf {
  174. groups = "i2c0_10_grp";
  175. bias-pull-up;
  176. slew-rate = <0>;
  177. io-standard = <1>;
  178. };
  179. };
  180. pinctrl_sdhci0_default: sdhci0-default {
  181. mux {
  182. groups = "sdio0_2_grp";
  183. function = "sdio0";
  184. };
  185. conf {
  186. groups = "sdio0_2_grp";
  187. slew-rate = <0>;
  188. io-standard = <1>;
  189. bias-disable;
  190. };
  191. mux-cd {
  192. groups = "gpio0_14_grp";
  193. function = "sdio0_cd";
  194. };
  195. conf-cd {
  196. groups = "gpio0_14_grp";
  197. bias-high-impedance;
  198. bias-pull-up;
  199. slew-rate = <0>;
  200. io-standard = <1>;
  201. };
  202. mux-wp {
  203. groups = "gpio0_15_grp";
  204. function = "sdio0_wp";
  205. };
  206. conf-wp {
  207. groups = "gpio0_15_grp";
  208. bias-high-impedance;
  209. bias-pull-up;
  210. slew-rate = <0>;
  211. io-standard = <1>;
  212. };
  213. };
  214. pinctrl_uart1_default: uart1-default {
  215. mux {
  216. groups = "uart1_10_grp";
  217. function = "uart1";
  218. };
  219. conf {
  220. groups = "uart1_10_grp";
  221. slew-rate = <0>;
  222. io-standard = <1>;
  223. };
  224. conf-rx {
  225. pins = "MIO49";
  226. bias-high-impedance;
  227. };
  228. conf-tx {
  229. pins = "MIO48";
  230. bias-disable;
  231. };
  232. };
  233. pinctrl_usb0_default: usb0-default {
  234. mux {
  235. groups = "usb0_0_grp";
  236. function = "usb0";
  237. };
  238. conf {
  239. groups = "usb0_0_grp";
  240. slew-rate = <0>;
  241. io-standard = <1>;
  242. };
  243. conf-rx {
  244. pins = "MIO29", "MIO31", "MIO36";
  245. bias-high-impedance;
  246. };
  247. conf-tx {
  248. pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
  249. "MIO35", "MIO37", "MIO38", "MIO39";
  250. bias-disable;
  251. };
  252. };
  253. };
  254. &sdhci0 {
  255. status = "okay";
  256. pinctrl-names = "default";
  257. pinctrl-0 = <&pinctrl_sdhci0_default>;
  258. };
  259. &uart1 {
  260. status = "okay";
  261. pinctrl-names = "default";
  262. pinctrl-0 = <&pinctrl_uart1_default>;
  263. };
  264. &usb0 {
  265. status = "okay";
  266. dr_mode = "host";
  267. usb-phy = <&usb_phy0>;
  268. pinctrl-names = "default";
  269. pinctrl-0 = <&pinctrl_usb0_default>;
  270. };