vf-colibri.dtsi 8.6 KB

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  1. /*
  2. * Copyright 2014 Toradex AG
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * version 2 as published by the Free Software Foundation.
  12. *
  13. * This file is distributed in the hope that it will be useful
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * Or, alternatively
  19. *
  20. * b) Permission is hereby granted, free of charge, to any person
  21. * obtaining a copy of this software and associated documentation
  22. * files (the "Software"), to deal in the Software without
  23. * restriction, including without limitation the rights to use
  24. * copy, modify, merge, publish, distribute, sublicense, and/or
  25. * sell copies of the Software, and to permit persons to whom the
  26. * Software is furnished to do so, subject to the following
  27. * conditions:
  28. *
  29. * The above copyright notice and this permission notice shall be
  30. * included in all copies or substantial portions of the Software.
  31. *
  32. * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  33. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  37. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39. * OTHER DEALINGS IN THE SOFTWARE.
  40. */
  41. / {
  42. aliases {
  43. ethernet0 = &fec1;
  44. ethernet1 = &fec0;
  45. };
  46. bl: backlight {
  47. compatible = "pwm-backlight";
  48. pinctrl-names = "default";
  49. pinctrl-0 = <&pinctrl_gpio_bl_on>;
  50. pwms = <&pwm0 0 5000000 0>;
  51. enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  52. status = "disabled";
  53. };
  54. reg_module_3v3: regulator-module-3v3 {
  55. compatible = "regulator-fixed";
  56. regulator-name = "+V3.3";
  57. regulator-min-microvolt = <3300000>;
  58. regulator-max-microvolt = <3300000>;
  59. };
  60. reg_module_3v3_avdd: regulator-module-3v3-avdd {
  61. compatible = "regulator-fixed";
  62. regulator-name = "+V3.3_AVDD_AUDIO";
  63. regulator-min-microvolt = <3300000>;
  64. regulator-max-microvolt = <3300000>;
  65. };
  66. };
  67. &adc0 {
  68. status = "okay";
  69. vref-supply = <&reg_module_3v3_avdd>;
  70. };
  71. &adc1 {
  72. status = "okay";
  73. vref-supply = <&reg_module_3v3_avdd>;
  74. };
  75. &can0 {
  76. pinctrl-names = "default";
  77. pinctrl-0 = <&pinctrl_flexcan0>;
  78. status = "disabled";
  79. };
  80. &can1 {
  81. pinctrl-names = "default";
  82. pinctrl-0 = <&pinctrl_flexcan1>;
  83. status = "disabled";
  84. };
  85. &clks {
  86. assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
  87. <&clks VF610_CLK_ENET_TS_SEL>;
  88. assigned-clock-parents = <&clks VF610_CLK_ENET_50M>,
  89. <&clks VF610_CLK_ENET_50M>;
  90. };
  91. &dspi1 {
  92. bus-num = <1>;
  93. pinctrl-names = "default";
  94. pinctrl-0 = <&pinctrl_dspi1>;
  95. };
  96. &edma0 {
  97. status = "okay";
  98. };
  99. &esdhc1 {
  100. pinctrl-names = "default";
  101. pinctrl-0 = <&pinctrl_esdhc1>;
  102. bus-width = <4>;
  103. cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
  104. disable-wp;
  105. };
  106. &fec1 {
  107. phy-mode = "rmii";
  108. phy-supply = <&reg_module_3v3>;
  109. pinctrl-names = "default";
  110. pinctrl-0 = <&pinctrl_fec1>;
  111. };
  112. &i2c0 {
  113. clock-frequency = <400000>;
  114. pinctrl-names = "default";
  115. pinctrl-0 = <&pinctrl_i2c0>;
  116. };
  117. &nfc {
  118. pinctrl-names = "default";
  119. pinctrl-0 = <&pinctrl_nfc>;
  120. status = "okay";
  121. nand@0 {
  122. compatible = "fsl,vf610-nfc-nandcs";
  123. reg = <0>;
  124. #address-cells = <1>;
  125. #size-cells = <1>;
  126. nand-bus-width = <8>;
  127. nand-ecc-mode = "hw";
  128. nand-ecc-strength = <32>;
  129. nand-ecc-step-size = <2048>;
  130. nand-on-flash-bbt;
  131. };
  132. };
  133. &pwm0 {
  134. pinctrl-names = "default";
  135. pinctrl-0 = <&pinctrl_pwm0>;
  136. };
  137. &pwm1 {
  138. pinctrl-names = "default";
  139. pinctrl-0 = <&pinctrl_pwm1>;
  140. };
  141. &uart0 {
  142. pinctrl-names = "default";
  143. pinctrl-0 = <&pinctrl_uart0>;
  144. };
  145. &uart1 {
  146. pinctrl-names = "default";
  147. pinctrl-0 = <&pinctrl_uart1>;
  148. };
  149. &uart2 {
  150. pinctrl-names = "default";
  151. pinctrl-0 = <&pinctrl_uart2>;
  152. };
  153. &usbdev0 {
  154. disable-over-current;
  155. status = "okay";
  156. };
  157. &usbh1 {
  158. disable-over-current;
  159. status = "okay";
  160. };
  161. &usbmisc0 {
  162. status = "okay";
  163. };
  164. &usbmisc1 {
  165. status = "okay";
  166. };
  167. &usbphy0 {
  168. status = "okay";
  169. };
  170. &usbphy1 {
  171. status = "okay";
  172. };
  173. &iomuxc {
  174. vf610-colibri {
  175. pinctrl_flexcan0: can0grp {
  176. fsl,pins = <
  177. VF610_PAD_PTB14__CAN0_RX 0x31F1
  178. VF610_PAD_PTB15__CAN0_TX 0x31F2
  179. >;
  180. };
  181. pinctrl_flexcan1: can1grp {
  182. fsl,pins = <
  183. VF610_PAD_PTB16__CAN1_RX 0x31F1
  184. VF610_PAD_PTB17__CAN1_TX 0x31F2
  185. >;
  186. };
  187. pinctrl_gpio_ext: gpio_ext {
  188. fsl,pins = <
  189. VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */
  190. VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */
  191. VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */
  192. >;
  193. };
  194. pinctrl_dcu0_1: dcu0grp_1 {
  195. fsl,pins = <
  196. VF610_PAD_PTE0__DCU0_HSYNC 0x1902
  197. VF610_PAD_PTE1__DCU0_VSYNC 0x1902
  198. VF610_PAD_PTE2__DCU0_PCLK 0x1902
  199. VF610_PAD_PTE4__DCU0_DE 0x1902
  200. VF610_PAD_PTE5__DCU0_R0 0x1902
  201. VF610_PAD_PTE6__DCU0_R1 0x1902
  202. VF610_PAD_PTE7__DCU0_R2 0x1902
  203. VF610_PAD_PTE8__DCU0_R3 0x1902
  204. VF610_PAD_PTE9__DCU0_R4 0x1902
  205. VF610_PAD_PTE10__DCU0_R5 0x1902
  206. VF610_PAD_PTE11__DCU0_R6 0x1902
  207. VF610_PAD_PTE12__DCU0_R7 0x1902
  208. VF610_PAD_PTE13__DCU0_G0 0x1902
  209. VF610_PAD_PTE14__DCU0_G1 0x1902
  210. VF610_PAD_PTE15__DCU0_G2 0x1902
  211. VF610_PAD_PTE16__DCU0_G3 0x1902
  212. VF610_PAD_PTE17__DCU0_G4 0x1902
  213. VF610_PAD_PTE18__DCU0_G5 0x1902
  214. VF610_PAD_PTE19__DCU0_G6 0x1902
  215. VF610_PAD_PTE20__DCU0_G7 0x1902
  216. VF610_PAD_PTE21__DCU0_B0 0x1902
  217. VF610_PAD_PTE22__DCU0_B1 0x1902
  218. VF610_PAD_PTE23__DCU0_B2 0x1902
  219. VF610_PAD_PTE24__DCU0_B3 0x1902
  220. VF610_PAD_PTE25__DCU0_B4 0x1902
  221. VF610_PAD_PTE26__DCU0_B5 0x1902
  222. VF610_PAD_PTE27__DCU0_B6 0x1902
  223. VF610_PAD_PTE28__DCU0_B7 0x1902
  224. >;
  225. };
  226. pinctrl_dspi1: dspi1grp {
  227. fsl,pins = <
  228. VF610_PAD_PTD5__DSPI1_CS0 0x33e2
  229. VF610_PAD_PTD6__DSPI1_SIN 0x33e1
  230. VF610_PAD_PTD7__DSPI1_SOUT 0x33e2
  231. VF610_PAD_PTD8__DSPI1_SCK 0x33e2
  232. >;
  233. };
  234. pinctrl_esdhc1: esdhc1grp {
  235. fsl,pins = <
  236. VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
  237. VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
  238. VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
  239. VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
  240. VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
  241. VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
  242. VF610_PAD_PTB20__GPIO_42 0x219d
  243. >;
  244. };
  245. pinctrl_fec1: fec1grp {
  246. fsl,pins = <
  247. VF610_PAD_PTA6__RMII_CLKOUT 0x30d2
  248. VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
  249. VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
  250. VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
  251. VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
  252. VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
  253. VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
  254. VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
  255. VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
  256. VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
  257. >;
  258. };
  259. pinctrl_gpio_bl_on: gpio_bl_on {
  260. fsl,pins = <
  261. VF610_PAD_PTC0__GPIO_45 0x22ef
  262. >;
  263. };
  264. pinctrl_i2c0: i2c0grp {
  265. fsl,pins = <
  266. VF610_PAD_PTB14__I2C0_SCL 0x37ff
  267. VF610_PAD_PTB15__I2C0_SDA 0x37ff
  268. >;
  269. };
  270. pinctrl_nfc: nfcgrp {
  271. fsl,pins = <
  272. VF610_PAD_PTD23__NF_IO7 0x28df
  273. VF610_PAD_PTD22__NF_IO6 0x28df
  274. VF610_PAD_PTD21__NF_IO5 0x28df
  275. VF610_PAD_PTD20__NF_IO4 0x28df
  276. VF610_PAD_PTD19__NF_IO3 0x28df
  277. VF610_PAD_PTD18__NF_IO2 0x28df
  278. VF610_PAD_PTD17__NF_IO1 0x28df
  279. VF610_PAD_PTD16__NF_IO0 0x28df
  280. VF610_PAD_PTB24__NF_WE_B 0x28c2
  281. VF610_PAD_PTB25__NF_CE0_B 0x28c2
  282. VF610_PAD_PTB27__NF_RE_B 0x28c2
  283. VF610_PAD_PTC26__NF_RB_B 0x283d
  284. VF610_PAD_PTC27__NF_ALE 0x28c2
  285. VF610_PAD_PTC28__NF_CLE 0x28c2
  286. >;
  287. };
  288. pinctrl_pwm0: pwm0grp {
  289. fsl,pins = <
  290. VF610_PAD_PTB0__FTM0_CH0 0x1182
  291. VF610_PAD_PTB1__FTM0_CH1 0x1182
  292. >;
  293. };
  294. pinctrl_pwm1: pwm1grp {
  295. fsl,pins = <
  296. VF610_PAD_PTB8__FTM1_CH0 0x1182
  297. VF610_PAD_PTB9__FTM1_CH1 0x1182
  298. >;
  299. };
  300. pinctrl_uart0: uart0grp {
  301. fsl,pins = <
  302. VF610_PAD_PTB10__UART0_TX 0x21a2
  303. VF610_PAD_PTB11__UART0_RX 0x21a1
  304. VF610_PAD_PTB12__UART0_RTS 0x21a2
  305. VF610_PAD_PTB13__UART0_CTS 0x21a1
  306. >;
  307. };
  308. pinctrl_uart1: uart1grp {
  309. fsl,pins = <
  310. VF610_PAD_PTB4__UART1_TX 0x21a2
  311. VF610_PAD_PTB5__UART1_RX 0x21a1
  312. >;
  313. };
  314. pinctrl_uart2: uart2grp {
  315. fsl,pins = <
  316. VF610_PAD_PTD0__UART2_TX 0x21a2
  317. VF610_PAD_PTD1__UART2_RX 0x21a1
  318. VF610_PAD_PTD2__UART2_RTS 0x21a2
  319. VF610_PAD_PTD3__UART2_CTS 0x21a1
  320. >;
  321. };
  322. pinctrl_usbh1_reg: gpio_usb_vbus {
  323. fsl,pins = <
  324. VF610_PAD_PTD4__GPIO_83 0x22ed
  325. >;
  326. };
  327. };
  328. };