tegra30-cardhu.dtsi 15 KB

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  1. #include <dt-bindings/input/input.h>
  2. #include "tegra30.dtsi"
  3. /**
  4. * This file contains common DT entry for all fab version of Cardhu.
  5. * There is multiple fab version of Cardhu starting from A01 to A07.
  6. * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
  7. * A02 will have different sets of GPIOs for fixed regulator compare to
  8. * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
  9. * compatible with fab version A04. Based on Cardhu fab version, the
  10. * related dts file need to be chosen like for Cardhu fab version A02,
  11. * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
  12. * tegra30-cardhu-a04.dts.
  13. * The identification of board is done in two ways, by looking the sticker
  14. * on PCB and by reading board id eeprom.
  15. * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
  16. * number is the fab version like here it is 002 and hence fab version A02.
  17. * The (downstream internal) U-Boot of Cardhu display the board-id as
  18. * follows:
  19. * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
  20. * In this Fab version is 02 i.e. A02.
  21. * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
  22. * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
  23. * wide.
  24. */
  25. / {
  26. model = "NVIDIA Tegra30 Cardhu evaluation board";
  27. compatible = "nvidia,cardhu", "nvidia,tegra30";
  28. aliases {
  29. rtc0 = "/i2c@7000d000/tps65911@2d";
  30. rtc1 = "/rtc@7000e000";
  31. serial0 = &uarta;
  32. serial1 = &uartc;
  33. };
  34. chosen {
  35. stdout-path = "serial0:115200n8";
  36. };
  37. memory {
  38. reg = <0x80000000 0x40000000>;
  39. };
  40. pcie-controller@00003000 {
  41. status = "okay";
  42. /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
  43. avdd-pexb-supply = <&ldo1_reg>;
  44. vdd-pexb-supply = <&ldo1_reg>;
  45. avdd-pex-pll-supply = <&ldo1_reg>;
  46. hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
  47. vddio-pex-ctl-supply = <&sys_3v3_reg>;
  48. avdd-plle-supply = <&ldo2_reg>;
  49. pci@1,0 {
  50. nvidia,num-lanes = <4>;
  51. };
  52. pci@2,0 {
  53. nvidia,num-lanes = <1>;
  54. };
  55. pci@3,0 {
  56. status = "okay";
  57. nvidia,num-lanes = <1>;
  58. };
  59. };
  60. host1x@50000000 {
  61. dc@54200000 {
  62. rgb {
  63. status = "okay";
  64. nvidia,panel = <&panel>;
  65. };
  66. };
  67. };
  68. pinmux@70000868 {
  69. pinctrl-names = "default";
  70. pinctrl-0 = <&state_default>;
  71. state_default: pinmux {
  72. sdmmc1_clk_pz0 {
  73. nvidia,pins = "sdmmc1_clk_pz0";
  74. nvidia,function = "sdmmc1";
  75. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  76. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  77. };
  78. sdmmc1_cmd_pz1 {
  79. nvidia,pins = "sdmmc1_cmd_pz1",
  80. "sdmmc1_dat0_py7",
  81. "sdmmc1_dat1_py6",
  82. "sdmmc1_dat2_py5",
  83. "sdmmc1_dat3_py4";
  84. nvidia,function = "sdmmc1";
  85. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  86. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  87. };
  88. sdmmc3_clk_pa6 {
  89. nvidia,pins = "sdmmc3_clk_pa6";
  90. nvidia,function = "sdmmc3";
  91. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  92. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  93. };
  94. sdmmc3_cmd_pa7 {
  95. nvidia,pins = "sdmmc3_cmd_pa7",
  96. "sdmmc3_dat0_pb7",
  97. "sdmmc3_dat1_pb6",
  98. "sdmmc3_dat2_pb5",
  99. "sdmmc3_dat3_pb4";
  100. nvidia,function = "sdmmc3";
  101. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  102. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  103. };
  104. sdmmc4_clk_pcc4 {
  105. nvidia,pins = "sdmmc4_clk_pcc4",
  106. "sdmmc4_rst_n_pcc3";
  107. nvidia,function = "sdmmc4";
  108. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  109. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  110. };
  111. sdmmc4_dat0_paa0 {
  112. nvidia,pins = "sdmmc4_dat0_paa0",
  113. "sdmmc4_dat1_paa1",
  114. "sdmmc4_dat2_paa2",
  115. "sdmmc4_dat3_paa3",
  116. "sdmmc4_dat4_paa4",
  117. "sdmmc4_dat5_paa5",
  118. "sdmmc4_dat6_paa6",
  119. "sdmmc4_dat7_paa7";
  120. nvidia,function = "sdmmc4";
  121. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  122. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  123. };
  124. dap2_fs_pa2 {
  125. nvidia,pins = "dap2_fs_pa2",
  126. "dap2_sclk_pa3",
  127. "dap2_din_pa4",
  128. "dap2_dout_pa5";
  129. nvidia,function = "i2s1";
  130. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  131. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  132. };
  133. sdio3 {
  134. nvidia,pins = "drive_sdio3";
  135. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  136. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  137. nvidia,pull-down-strength = <46>;
  138. nvidia,pull-up-strength = <42>;
  139. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
  140. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
  141. };
  142. uart3_txd_pw6 {
  143. nvidia,pins = "uart3_txd_pw6",
  144. "uart3_cts_n_pa1",
  145. "uart3_rts_n_pc0",
  146. "uart3_rxd_pw7";
  147. nvidia,function = "uartc";
  148. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  149. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  150. };
  151. };
  152. };
  153. serial@70006000 {
  154. status = "okay";
  155. };
  156. serial@70006200 {
  157. compatible = "nvidia,tegra30-hsuart";
  158. status = "okay";
  159. };
  160. pwm@7000a000 {
  161. status = "okay";
  162. };
  163. panelddc: i2c@7000c000 {
  164. status = "okay";
  165. clock-frequency = <100000>;
  166. };
  167. i2c@7000c400 {
  168. status = "okay";
  169. clock-frequency = <100000>;
  170. };
  171. i2c@7000c500 {
  172. status = "okay";
  173. clock-frequency = <100000>;
  174. /* ALS and Proximity sensor */
  175. isl29028@44 {
  176. compatible = "isil,isl29028";
  177. reg = <0x44>;
  178. interrupt-parent = <&gpio>;
  179. interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
  180. };
  181. i2cmux@70 {
  182. compatible = "nxp,pca9546";
  183. #address-cells = <1>;
  184. #size-cells = <0>;
  185. reg = <0x70>;
  186. };
  187. };
  188. i2c@7000c700 {
  189. status = "okay";
  190. clock-frequency = <100000>;
  191. };
  192. i2c@7000d000 {
  193. status = "okay";
  194. clock-frequency = <100000>;
  195. wm8903: wm8903@1a {
  196. compatible = "wlf,wm8903";
  197. reg = <0x1a>;
  198. interrupt-parent = <&gpio>;
  199. interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
  200. gpio-controller;
  201. #gpio-cells = <2>;
  202. micdet-cfg = <0>;
  203. micdet-delay = <100>;
  204. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  205. };
  206. pmic: tps65911@2d {
  207. compatible = "ti,tps65911";
  208. reg = <0x2d>;
  209. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  210. #interrupt-cells = <2>;
  211. interrupt-controller;
  212. ti,system-power-controller;
  213. #gpio-cells = <2>;
  214. gpio-controller;
  215. vcc1-supply = <&vdd_ac_bat_reg>;
  216. vcc2-supply = <&vdd_ac_bat_reg>;
  217. vcc3-supply = <&vio_reg>;
  218. vcc4-supply = <&vdd_5v0_reg>;
  219. vcc5-supply = <&vdd_ac_bat_reg>;
  220. vcc6-supply = <&vdd2_reg>;
  221. vcc7-supply = <&vdd_ac_bat_reg>;
  222. vccio-supply = <&vdd_ac_bat_reg>;
  223. regulators {
  224. vdd1_reg: vdd1 {
  225. regulator-name = "vddio_ddr_1v2";
  226. regulator-min-microvolt = <1200000>;
  227. regulator-max-microvolt = <1200000>;
  228. regulator-always-on;
  229. };
  230. vdd2_reg: vdd2 {
  231. regulator-name = "vdd_1v5_gen";
  232. regulator-min-microvolt = <1500000>;
  233. regulator-max-microvolt = <1500000>;
  234. regulator-always-on;
  235. };
  236. vddctrl_reg: vddctrl {
  237. regulator-name = "vdd_cpu,vdd_sys";
  238. regulator-min-microvolt = <1000000>;
  239. regulator-max-microvolt = <1000000>;
  240. regulator-always-on;
  241. };
  242. vio_reg: vio {
  243. regulator-name = "vdd_1v8_gen";
  244. regulator-min-microvolt = <1800000>;
  245. regulator-max-microvolt = <1800000>;
  246. regulator-always-on;
  247. };
  248. ldo1_reg: ldo1 {
  249. regulator-name = "vdd_pexa,vdd_pexb";
  250. regulator-min-microvolt = <1050000>;
  251. regulator-max-microvolt = <1050000>;
  252. };
  253. ldo2_reg: ldo2 {
  254. regulator-name = "vdd_sata,avdd_plle";
  255. regulator-min-microvolt = <1050000>;
  256. regulator-max-microvolt = <1050000>;
  257. };
  258. /* LDO3 is not connected to anything */
  259. ldo4_reg: ldo4 {
  260. regulator-name = "vdd_rtc";
  261. regulator-min-microvolt = <1200000>;
  262. regulator-max-microvolt = <1200000>;
  263. regulator-always-on;
  264. };
  265. ldo5_reg: ldo5 {
  266. regulator-name = "vddio_sdmmc,avdd_vdac";
  267. regulator-min-microvolt = <3300000>;
  268. regulator-max-microvolt = <3300000>;
  269. regulator-always-on;
  270. };
  271. ldo6_reg: ldo6 {
  272. regulator-name = "avdd_dsi_csi,pwrdet_mipi";
  273. regulator-min-microvolt = <1200000>;
  274. regulator-max-microvolt = <1200000>;
  275. };
  276. ldo7_reg: ldo7 {
  277. regulator-name = "vdd_pllm,x,u,a_p_c_s";
  278. regulator-min-microvolt = <1200000>;
  279. regulator-max-microvolt = <1200000>;
  280. regulator-always-on;
  281. };
  282. ldo8_reg: ldo8 {
  283. regulator-name = "vdd_ddr_hs";
  284. regulator-min-microvolt = <1000000>;
  285. regulator-max-microvolt = <1000000>;
  286. regulator-always-on;
  287. };
  288. };
  289. };
  290. temperature-sensor@4c {
  291. compatible = "onnn,nct1008";
  292. reg = <0x4c>;
  293. vcc-supply = <&sys_3v3_reg>;
  294. interrupt-parent = <&gpio>;
  295. interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
  296. };
  297. tps62361@60 {
  298. compatible = "ti,tps62361";
  299. reg = <0x60>;
  300. regulator-name = "tps62361-vout";
  301. regulator-min-microvolt = <500000>;
  302. regulator-max-microvolt = <1500000>;
  303. regulator-boot-on;
  304. regulator-always-on;
  305. ti,vsel0-state-high;
  306. ti,vsel1-state-high;
  307. };
  308. };
  309. spi@7000da00 {
  310. status = "okay";
  311. spi-max-frequency = <25000000>;
  312. spi-flash@1 {
  313. compatible = "winbond,w25q32";
  314. reg = <1>;
  315. spi-max-frequency = <20000000>;
  316. };
  317. };
  318. pmc@7000e400 {
  319. status = "okay";
  320. nvidia,invert-interrupt;
  321. nvidia,suspend-mode = <1>;
  322. nvidia,cpu-pwr-good-time = <2000>;
  323. nvidia,cpu-pwr-off-time = <200>;
  324. nvidia,core-pwr-good-time = <3845 3845>;
  325. nvidia,core-pwr-off-time = <0>;
  326. nvidia,core-power-req-active-high;
  327. nvidia,sys-clock-req-active-high;
  328. };
  329. ahub@70080000 {
  330. i2s@70080400 {
  331. status = "okay";
  332. };
  333. };
  334. sdhci@78000000 {
  335. status = "okay";
  336. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  337. wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
  338. power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
  339. bus-width = <4>;
  340. };
  341. sdhci@78000600 {
  342. status = "okay";
  343. bus-width = <8>;
  344. non-removable;
  345. };
  346. usb@7d008000 {
  347. status = "okay";
  348. };
  349. usb-phy@7d008000 {
  350. vbus-supply = <&usb3_vbus_reg>;
  351. status = "okay";
  352. };
  353. backlight: backlight {
  354. compatible = "pwm-backlight";
  355. enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  356. power-supply = <&vdd_bl_reg>;
  357. pwms = <&pwm 0 5000000>;
  358. brightness-levels = <0 4 8 16 32 64 128 255>;
  359. default-brightness-level = <6>;
  360. };
  361. clocks {
  362. compatible = "simple-bus";
  363. #address-cells = <1>;
  364. #size-cells = <0>;
  365. clk32k_in: clock@0 {
  366. compatible = "fixed-clock";
  367. reg = <0>;
  368. #clock-cells = <0>;
  369. clock-frequency = <32768>;
  370. };
  371. };
  372. panel: panel {
  373. compatible = "chunghwa,claa101wb01", "simple-panel";
  374. ddc-i2c-bus = <&panelddc>;
  375. power-supply = <&vdd_pnl1_reg>;
  376. enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
  377. backlight = <&backlight>;
  378. };
  379. regulators {
  380. compatible = "simple-bus";
  381. #address-cells = <1>;
  382. #size-cells = <0>;
  383. vdd_ac_bat_reg: regulator@0 {
  384. compatible = "regulator-fixed";
  385. reg = <0>;
  386. regulator-name = "vdd_ac_bat";
  387. regulator-min-microvolt = <5000000>;
  388. regulator-max-microvolt = <5000000>;
  389. regulator-always-on;
  390. };
  391. cam_1v8_reg: regulator@1 {
  392. compatible = "regulator-fixed";
  393. reg = <1>;
  394. regulator-name = "cam_1v8";
  395. regulator-min-microvolt = <1800000>;
  396. regulator-max-microvolt = <1800000>;
  397. enable-active-high;
  398. gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
  399. vin-supply = <&vio_reg>;
  400. };
  401. cp_5v_reg: regulator@2 {
  402. compatible = "regulator-fixed";
  403. reg = <2>;
  404. regulator-name = "cp_5v";
  405. regulator-min-microvolt = <5000000>;
  406. regulator-max-microvolt = <5000000>;
  407. regulator-boot-on;
  408. regulator-always-on;
  409. enable-active-high;
  410. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  411. };
  412. emmc_3v3_reg: regulator@3 {
  413. compatible = "regulator-fixed";
  414. reg = <3>;
  415. regulator-name = "emmc_3v3";
  416. regulator-min-microvolt = <3300000>;
  417. regulator-max-microvolt = <3300000>;
  418. regulator-always-on;
  419. regulator-boot-on;
  420. enable-active-high;
  421. gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
  422. vin-supply = <&sys_3v3_reg>;
  423. };
  424. modem_3v3_reg: regulator@4 {
  425. compatible = "regulator-fixed";
  426. reg = <4>;
  427. regulator-name = "modem_3v3";
  428. regulator-min-microvolt = <3300000>;
  429. regulator-max-microvolt = <3300000>;
  430. enable-active-high;
  431. gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
  432. };
  433. pex_hvdd_3v3_reg: regulator@5 {
  434. compatible = "regulator-fixed";
  435. reg = <5>;
  436. regulator-name = "pex_hvdd_3v3";
  437. regulator-min-microvolt = <3300000>;
  438. regulator-max-microvolt = <3300000>;
  439. enable-active-high;
  440. gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
  441. vin-supply = <&sys_3v3_reg>;
  442. };
  443. vdd_cam1_ldo_reg: regulator@6 {
  444. compatible = "regulator-fixed";
  445. reg = <6>;
  446. regulator-name = "vdd_cam1_ldo";
  447. regulator-min-microvolt = <2800000>;
  448. regulator-max-microvolt = <2800000>;
  449. enable-active-high;
  450. gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
  451. vin-supply = <&sys_3v3_reg>;
  452. };
  453. vdd_cam2_ldo_reg: regulator@7 {
  454. compatible = "regulator-fixed";
  455. reg = <7>;
  456. regulator-name = "vdd_cam2_ldo";
  457. regulator-min-microvolt = <2800000>;
  458. regulator-max-microvolt = <2800000>;
  459. enable-active-high;
  460. gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
  461. vin-supply = <&sys_3v3_reg>;
  462. };
  463. vdd_cam3_ldo_reg: regulator@8 {
  464. compatible = "regulator-fixed";
  465. reg = <8>;
  466. regulator-name = "vdd_cam3_ldo";
  467. regulator-min-microvolt = <3300000>;
  468. regulator-max-microvolt = <3300000>;
  469. enable-active-high;
  470. gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
  471. vin-supply = <&sys_3v3_reg>;
  472. };
  473. vdd_com_reg: regulator@9 {
  474. compatible = "regulator-fixed";
  475. reg = <9>;
  476. regulator-name = "vdd_com";
  477. regulator-min-microvolt = <3300000>;
  478. regulator-max-microvolt = <3300000>;
  479. regulator-always-on;
  480. regulator-boot-on;
  481. enable-active-high;
  482. gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
  483. vin-supply = <&sys_3v3_reg>;
  484. };
  485. vdd_fuse_3v3_reg: regulator@10 {
  486. compatible = "regulator-fixed";
  487. reg = <10>;
  488. regulator-name = "vdd_fuse_3v3";
  489. regulator-min-microvolt = <3300000>;
  490. regulator-max-microvolt = <3300000>;
  491. enable-active-high;
  492. gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
  493. vin-supply = <&sys_3v3_reg>;
  494. };
  495. vdd_pnl1_reg: regulator@11 {
  496. compatible = "regulator-fixed";
  497. reg = <11>;
  498. regulator-name = "vdd_pnl1";
  499. regulator-min-microvolt = <3300000>;
  500. regulator-max-microvolt = <3300000>;
  501. regulator-always-on;
  502. regulator-boot-on;
  503. enable-active-high;
  504. gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
  505. vin-supply = <&sys_3v3_reg>;
  506. };
  507. vdd_vid_reg: regulator@12 {
  508. compatible = "regulator-fixed";
  509. reg = <12>;
  510. regulator-name = "vddio_vid";
  511. regulator-min-microvolt = <5000000>;
  512. regulator-max-microvolt = <5000000>;
  513. enable-active-high;
  514. gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
  515. gpio-open-drain;
  516. vin-supply = <&vdd_5v0_reg>;
  517. };
  518. };
  519. sound {
  520. compatible = "nvidia,tegra-audio-wm8903-cardhu",
  521. "nvidia,tegra-audio-wm8903";
  522. nvidia,model = "NVIDIA Tegra Cardhu";
  523. nvidia,audio-routing =
  524. "Headphone Jack", "HPOUTR",
  525. "Headphone Jack", "HPOUTL",
  526. "Int Spk", "ROP",
  527. "Int Spk", "RON",
  528. "Int Spk", "LOP",
  529. "Int Spk", "LON",
  530. "Mic Jack", "MICBIAS",
  531. "IN1L", "Mic Jack";
  532. nvidia,i2s-controller = <&tegra_i2s1>;
  533. nvidia,audio-codec = <&wm8903>;
  534. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  535. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
  536. GPIO_ACTIVE_HIGH>;
  537. clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
  538. <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
  539. <&tegra_car TEGRA30_CLK_EXTERN1>;
  540. clock-names = "pll_a", "pll_a_out0", "mclk";
  541. };
  542. gpio-keys {
  543. compatible = "gpio-keys";
  544. power {
  545. label = "Power";
  546. interrupt-parent = <&pmic>;
  547. interrupts = <2 0>;
  548. linux,code = <KEY_POWER>;
  549. debounce-interval = <100>;
  550. wakeup-source;
  551. };
  552. volume-down {
  553. label = "Volume Down";
  554. gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
  555. linux,code = <KEY_VOLUMEDOWN>;
  556. debounce-interval = <10>;
  557. };
  558. volume-up {
  559. label = "Volume Up";
  560. gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
  561. linux,code = <KEY_VOLUMEUP>;
  562. debounce-interval = <10>;
  563. };
  564. };
  565. };