tegra20-trimslice.dts 9.8 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra20.dtsi"
  4. / {
  5. model = "Compulab TrimSlice board";
  6. compatible = "compulab,trimslice", "nvidia,tegra20";
  7. aliases {
  8. rtc0 = "/i2c@7000c500/rtc@56";
  9. rtc1 = "/rtc@7000e000";
  10. serial0 = &uarta;
  11. };
  12. chosen {
  13. stdout-path = "serial0:115200n8";
  14. };
  15. memory {
  16. reg = <0x00000000 0x40000000>;
  17. };
  18. host1x@50000000 {
  19. hdmi@54280000 {
  20. status = "okay";
  21. vdd-supply = <&hdmi_vdd_reg>;
  22. pll-supply = <&hdmi_pll_reg>;
  23. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  24. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  25. GPIO_ACTIVE_HIGH>;
  26. };
  27. };
  28. pinmux@70000014 {
  29. pinctrl-names = "default";
  30. pinctrl-0 = <&state_default>;
  31. state_default: pinmux {
  32. ata {
  33. nvidia,pins = "ata";
  34. nvidia,function = "ide";
  35. };
  36. atb {
  37. nvidia,pins = "atb", "gma";
  38. nvidia,function = "sdio4";
  39. };
  40. atc {
  41. nvidia,pins = "atc", "gmb";
  42. nvidia,function = "nand";
  43. };
  44. atd {
  45. nvidia,pins = "atd", "ate", "gme", "pta";
  46. nvidia,function = "gmi";
  47. };
  48. cdev1 {
  49. nvidia,pins = "cdev1";
  50. nvidia,function = "plla_out";
  51. };
  52. cdev2 {
  53. nvidia,pins = "cdev2";
  54. nvidia,function = "pllp_out4";
  55. };
  56. crtp {
  57. nvidia,pins = "crtp";
  58. nvidia,function = "crt";
  59. };
  60. csus {
  61. nvidia,pins = "csus";
  62. nvidia,function = "vi_sensor_clk";
  63. };
  64. dap1 {
  65. nvidia,pins = "dap1";
  66. nvidia,function = "dap1";
  67. };
  68. dap2 {
  69. nvidia,pins = "dap2";
  70. nvidia,function = "dap2";
  71. };
  72. dap3 {
  73. nvidia,pins = "dap3";
  74. nvidia,function = "dap3";
  75. };
  76. dap4 {
  77. nvidia,pins = "dap4";
  78. nvidia,function = "dap4";
  79. };
  80. ddc {
  81. nvidia,pins = "ddc";
  82. nvidia,function = "i2c2";
  83. };
  84. dta {
  85. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  86. nvidia,function = "vi";
  87. };
  88. dtf {
  89. nvidia,pins = "dtf";
  90. nvidia,function = "i2c3";
  91. };
  92. gmc {
  93. nvidia,pins = "gmc", "gmd";
  94. nvidia,function = "sflash";
  95. };
  96. gpu {
  97. nvidia,pins = "gpu";
  98. nvidia,function = "uarta";
  99. };
  100. gpu7 {
  101. nvidia,pins = "gpu7";
  102. nvidia,function = "rtck";
  103. };
  104. gpv {
  105. nvidia,pins = "gpv", "slxa", "slxk";
  106. nvidia,function = "pcie";
  107. };
  108. hdint {
  109. nvidia,pins = "hdint";
  110. nvidia,function = "hdmi";
  111. };
  112. i2cp {
  113. nvidia,pins = "i2cp";
  114. nvidia,function = "i2cp";
  115. };
  116. irrx {
  117. nvidia,pins = "irrx", "irtx";
  118. nvidia,function = "uartb";
  119. };
  120. kbca {
  121. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  122. "kbce", "kbcf";
  123. nvidia,function = "kbc";
  124. };
  125. lcsn {
  126. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  127. "ld3", "ld4", "ld5", "ld6", "ld7",
  128. "ld8", "ld9", "ld10", "ld11", "ld12",
  129. "ld13", "ld14", "ld15", "ld16", "ld17",
  130. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  131. "lhs", "lm0", "lm1", "lpp", "lpw0",
  132. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  133. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  134. "lvs";
  135. nvidia,function = "displaya";
  136. };
  137. owc {
  138. nvidia,pins = "owc", "uac";
  139. nvidia,function = "rsvd2";
  140. };
  141. pmc {
  142. nvidia,pins = "pmc";
  143. nvidia,function = "pwr_on";
  144. };
  145. rm {
  146. nvidia,pins = "rm";
  147. nvidia,function = "i2c1";
  148. };
  149. sdb {
  150. nvidia,pins = "sdb", "sdc", "sdd";
  151. nvidia,function = "pwm";
  152. };
  153. sdio1 {
  154. nvidia,pins = "sdio1";
  155. nvidia,function = "sdio1";
  156. };
  157. slxc {
  158. nvidia,pins = "slxc", "slxd";
  159. nvidia,function = "sdio3";
  160. };
  161. spdi {
  162. nvidia,pins = "spdi", "spdo";
  163. nvidia,function = "spdif";
  164. };
  165. spia {
  166. nvidia,pins = "spia", "spib", "spic";
  167. nvidia,function = "spi2";
  168. };
  169. spid {
  170. nvidia,pins = "spid", "spie", "spif";
  171. nvidia,function = "spi1";
  172. };
  173. spig {
  174. nvidia,pins = "spig", "spih";
  175. nvidia,function = "spi2_alt";
  176. };
  177. uaa {
  178. nvidia,pins = "uaa", "uab", "uda";
  179. nvidia,function = "ulpi";
  180. };
  181. uad {
  182. nvidia,pins = "uad";
  183. nvidia,function = "irda";
  184. };
  185. uca {
  186. nvidia,pins = "uca", "ucb";
  187. nvidia,function = "uartc";
  188. };
  189. conf_ata {
  190. nvidia,pins = "ata", "atc", "atd", "ate",
  191. "crtp", "dap2", "dap3", "dap4", "dta",
  192. "dtb", "dtc", "dtd", "dte", "gmb",
  193. "gme", "i2cp", "pta", "slxc", "slxd",
  194. "spdi", "spdo", "uda";
  195. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  196. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  197. };
  198. conf_atb {
  199. nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
  200. "gma", "gmc", "gmd", "gpu", "gpu7",
  201. "gpv", "sdio1", "slxa", "slxk", "uac";
  202. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  203. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  204. };
  205. conf_ck32 {
  206. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  207. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  208. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  209. };
  210. conf_csus {
  211. nvidia,pins = "csus", "spia", "spib",
  212. "spid", "spif";
  213. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  214. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  215. };
  216. conf_ddc {
  217. nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
  218. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  219. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  220. };
  221. conf_hdint {
  222. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  223. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  224. "lvp0", "pmc";
  225. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  226. };
  227. conf_irrx {
  228. nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
  229. "kbcc", "kbcd", "kbce", "kbcf", "owc",
  230. "spic", "spie", "spig", "spih", "uaa",
  231. "uab", "uad", "uca", "ucb";
  232. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  233. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  234. };
  235. conf_lc {
  236. nvidia,pins = "lc", "ls";
  237. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  238. };
  239. conf_ld0 {
  240. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  241. "ld5", "ld6", "ld7", "ld8", "ld9",
  242. "ld10", "ld11", "ld12", "ld13", "ld14",
  243. "ld15", "ld16", "ld17", "ldi", "lhp0",
  244. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  245. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  246. "lvs", "sdb";
  247. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  248. };
  249. conf_ld17_0 {
  250. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  251. "ld23_22";
  252. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  253. };
  254. conf_spif {
  255. nvidia,pins = "spif";
  256. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  257. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  258. };
  259. };
  260. };
  261. i2s@70002800 {
  262. status = "okay";
  263. };
  264. serial@70006000 {
  265. status = "okay";
  266. };
  267. dvi_ddc: i2c@7000c000 {
  268. status = "okay";
  269. clock-frequency = <100000>;
  270. };
  271. spi@7000c380 {
  272. status = "okay";
  273. spi-max-frequency = <48000000>;
  274. spi-flash@0 {
  275. compatible = "winbond,w25q80bl";
  276. reg = <0>;
  277. spi-max-frequency = <48000000>;
  278. };
  279. };
  280. hdmi_ddc: i2c@7000c400 {
  281. status = "okay";
  282. clock-frequency = <100000>;
  283. };
  284. i2c@7000c500 {
  285. status = "okay";
  286. clock-frequency = <400000>;
  287. codec: codec@1a {
  288. compatible = "ti,tlv320aic23";
  289. reg = <0x1a>;
  290. };
  291. rtc@56 {
  292. compatible = "emmicro,em3027";
  293. reg = <0x56>;
  294. };
  295. };
  296. pmc@7000e400 {
  297. nvidia,suspend-mode = <1>;
  298. nvidia,cpu-pwr-good-time = <5000>;
  299. nvidia,cpu-pwr-off-time = <5000>;
  300. nvidia,core-pwr-good-time = <3845 3845>;
  301. nvidia,core-pwr-off-time = <3875>;
  302. nvidia,sys-clock-req-active-high;
  303. };
  304. pcie-controller@80003000 {
  305. status = "okay";
  306. avdd-pex-supply = <&pci_vdd_reg>;
  307. vdd-pex-supply = <&pci_vdd_reg>;
  308. avdd-pex-pll-supply = <&pci_vdd_reg>;
  309. avdd-plle-supply = <&pci_vdd_reg>;
  310. vddio-pex-clk-supply = <&pci_clk_reg>;
  311. pci@1,0 {
  312. status = "okay";
  313. };
  314. };
  315. usb@c5000000 {
  316. status = "okay";
  317. };
  318. usb-phy@c5000000 {
  319. status = "okay";
  320. vbus-supply = <&vbus_reg>;
  321. };
  322. usb@c5004000 {
  323. status = "okay";
  324. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  325. GPIO_ACTIVE_LOW>;
  326. };
  327. usb-phy@c5004000 {
  328. status = "okay";
  329. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  330. GPIO_ACTIVE_LOW>;
  331. };
  332. usb@c5008000 {
  333. status = "okay";
  334. };
  335. usb-phy@c5008000 {
  336. status = "okay";
  337. };
  338. sdhci@c8000000 {
  339. status = "okay";
  340. bus-width = <4>;
  341. };
  342. sdhci@c8000600 {
  343. status = "okay";
  344. cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
  345. wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
  346. bus-width = <4>;
  347. };
  348. clocks {
  349. compatible = "simple-bus";
  350. #address-cells = <1>;
  351. #size-cells = <0>;
  352. clk32k_in: clock@0 {
  353. compatible = "fixed-clock";
  354. reg = <0>;
  355. #clock-cells = <0>;
  356. clock-frequency = <32768>;
  357. };
  358. };
  359. gpio-keys {
  360. compatible = "gpio-keys";
  361. power {
  362. label = "Power";
  363. gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
  364. linux,code = <KEY_POWER>;
  365. wakeup-source;
  366. };
  367. };
  368. poweroff {
  369. compatible = "gpio-poweroff";
  370. gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
  371. };
  372. regulators {
  373. compatible = "simple-bus";
  374. #address-cells = <1>;
  375. #size-cells = <0>;
  376. hdmi_vdd_reg: regulator@0 {
  377. compatible = "regulator-fixed";
  378. reg = <0>;
  379. regulator-name = "avdd_hdmi";
  380. regulator-min-microvolt = <3300000>;
  381. regulator-max-microvolt = <3300000>;
  382. regulator-always-on;
  383. };
  384. hdmi_pll_reg: regulator@1 {
  385. compatible = "regulator-fixed";
  386. reg = <1>;
  387. regulator-name = "avdd_hdmi_pll";
  388. regulator-min-microvolt = <1800000>;
  389. regulator-max-microvolt = <1800000>;
  390. regulator-always-on;
  391. };
  392. vbus_reg: regulator@2 {
  393. compatible = "regulator-fixed";
  394. reg = <2>;
  395. regulator-name = "usb1_vbus";
  396. regulator-min-microvolt = <5000000>;
  397. regulator-max-microvolt = <5000000>;
  398. enable-active-high;
  399. gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
  400. regulator-always-on;
  401. regulator-boot-on;
  402. };
  403. pci_clk_reg: regulator@3 {
  404. compatible = "regulator-fixed";
  405. reg = <3>;
  406. regulator-name = "pci_clk";
  407. regulator-min-microvolt = <3300000>;
  408. regulator-max-microvolt = <3300000>;
  409. regulator-always-on;
  410. };
  411. pci_vdd_reg: regulator@4 {
  412. compatible = "regulator-fixed";
  413. reg = <4>;
  414. regulator-name = "pci_vdd";
  415. regulator-min-microvolt = <1050000>;
  416. regulator-max-microvolt = <1050000>;
  417. regulator-always-on;
  418. };
  419. };
  420. sound {
  421. compatible = "nvidia,tegra-audio-trimslice";
  422. nvidia,i2s-controller = <&tegra_i2s1>;
  423. nvidia,audio-codec = <&codec>;
  424. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  425. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  426. <&tegra_car TEGRA20_CLK_CDEV1>;
  427. clock-names = "pll_a", "pll_a_out0", "mclk";
  428. };
  429. };