tegra20-seaboard.dts 22 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra20.dtsi"
  4. / {
  5. model = "NVIDIA Seaboard";
  6. compatible = "nvidia,seaboard", "nvidia,tegra20";
  7. aliases {
  8. rtc0 = "/i2c@7000d000/tps6586x@34";
  9. rtc1 = "/rtc@7000e000";
  10. serial0 = &uartd;
  11. };
  12. chosen {
  13. stdout-path = "serial0:115200n8";
  14. };
  15. memory {
  16. reg = <0x00000000 0x40000000>;
  17. };
  18. host1x@50000000 {
  19. dc@54200000 {
  20. rgb {
  21. status = "okay";
  22. nvidia,panel = <&panel>;
  23. };
  24. };
  25. hdmi@54280000 {
  26. status = "okay";
  27. vdd-supply = <&hdmi_vdd_reg>;
  28. pll-supply = <&hdmi_pll_reg>;
  29. hdmi-supply = <&vdd_hdmi>;
  30. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  31. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  32. GPIO_ACTIVE_HIGH>;
  33. };
  34. };
  35. pinmux@70000014 {
  36. pinctrl-names = "default";
  37. pinctrl-0 = <&state_default>;
  38. state_default: pinmux {
  39. ata {
  40. nvidia,pins = "ata";
  41. nvidia,function = "ide";
  42. };
  43. atb {
  44. nvidia,pins = "atb", "gma", "gme";
  45. nvidia,function = "sdio4";
  46. };
  47. atc {
  48. nvidia,pins = "atc";
  49. nvidia,function = "nand";
  50. };
  51. atd {
  52. nvidia,pins = "atd", "ate", "gmb", "spia",
  53. "spib", "spic";
  54. nvidia,function = "gmi";
  55. };
  56. cdev1 {
  57. nvidia,pins = "cdev1";
  58. nvidia,function = "plla_out";
  59. };
  60. cdev2 {
  61. nvidia,pins = "cdev2";
  62. nvidia,function = "pllp_out4";
  63. };
  64. crtp {
  65. nvidia,pins = "crtp", "lm1";
  66. nvidia,function = "crt";
  67. };
  68. csus {
  69. nvidia,pins = "csus";
  70. nvidia,function = "vi_sensor_clk";
  71. };
  72. dap1 {
  73. nvidia,pins = "dap1";
  74. nvidia,function = "dap1";
  75. };
  76. dap2 {
  77. nvidia,pins = "dap2";
  78. nvidia,function = "dap2";
  79. };
  80. dap3 {
  81. nvidia,pins = "dap3";
  82. nvidia,function = "dap3";
  83. };
  84. dap4 {
  85. nvidia,pins = "dap4";
  86. nvidia,function = "dap4";
  87. };
  88. dta {
  89. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  90. nvidia,function = "vi";
  91. };
  92. dtf {
  93. nvidia,pins = "dtf";
  94. nvidia,function = "i2c3";
  95. };
  96. gmc {
  97. nvidia,pins = "gmc";
  98. nvidia,function = "uartd";
  99. };
  100. gmd {
  101. nvidia,pins = "gmd";
  102. nvidia,function = "sflash";
  103. };
  104. gpu {
  105. nvidia,pins = "gpu";
  106. nvidia,function = "pwm";
  107. };
  108. gpu7 {
  109. nvidia,pins = "gpu7";
  110. nvidia,function = "rtck";
  111. };
  112. gpv {
  113. nvidia,pins = "gpv", "slxa", "slxk";
  114. nvidia,function = "pcie";
  115. };
  116. hdint {
  117. nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
  118. "lsck", "lsda";
  119. nvidia,function = "hdmi";
  120. };
  121. i2cp {
  122. nvidia,pins = "i2cp";
  123. nvidia,function = "i2cp";
  124. };
  125. irrx {
  126. nvidia,pins = "irrx", "irtx";
  127. nvidia,function = "uartb";
  128. };
  129. kbca {
  130. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  131. "kbce", "kbcf";
  132. nvidia,function = "kbc";
  133. };
  134. lcsn {
  135. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  136. "lsdi", "lvp0";
  137. nvidia,function = "rsvd4";
  138. };
  139. ld0 {
  140. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  141. "ld5", "ld6", "ld7", "ld8", "ld9",
  142. "ld10", "ld11", "ld12", "ld13", "ld14",
  143. "ld15", "ld16", "ld17", "ldi", "lhp0",
  144. "lhp1", "lhp2", "lhs", "lpp", "lsc0",
  145. "lspi", "lvp1", "lvs";
  146. nvidia,function = "displaya";
  147. };
  148. owc {
  149. nvidia,pins = "owc", "spdi", "spdo", "uac";
  150. nvidia,function = "rsvd2";
  151. };
  152. pmc {
  153. nvidia,pins = "pmc";
  154. nvidia,function = "pwr_on";
  155. };
  156. rm {
  157. nvidia,pins = "rm";
  158. nvidia,function = "i2c1";
  159. };
  160. sdb {
  161. nvidia,pins = "sdb", "sdc", "sdd";
  162. nvidia,function = "sdio3";
  163. };
  164. sdio1 {
  165. nvidia,pins = "sdio1";
  166. nvidia,function = "sdio1";
  167. };
  168. slxc {
  169. nvidia,pins = "slxc", "slxd";
  170. nvidia,function = "spdif";
  171. };
  172. spid {
  173. nvidia,pins = "spid", "spie", "spif";
  174. nvidia,function = "spi1";
  175. };
  176. spig {
  177. nvidia,pins = "spig", "spih";
  178. nvidia,function = "spi2_alt";
  179. };
  180. uaa {
  181. nvidia,pins = "uaa", "uab", "uda";
  182. nvidia,function = "ulpi";
  183. };
  184. uad {
  185. nvidia,pins = "uad";
  186. nvidia,function = "irda";
  187. };
  188. uca {
  189. nvidia,pins = "uca", "ucb";
  190. nvidia,function = "uartc";
  191. };
  192. conf_ata {
  193. nvidia,pins = "ata", "atb", "atc", "atd",
  194. "cdev1", "cdev2", "dap1", "dap2",
  195. "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
  196. "gme", "gpu", "gpu7", "i2cp", "irrx",
  197. "irtx", "pta", "rm", "sdc", "sdd",
  198. "slxd", "slxk", "spdi", "spdo", "uac",
  199. "uad", "uca", "ucb", "uda";
  200. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  201. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  202. };
  203. conf_ate {
  204. nvidia,pins = "ate", "csus", "dap3",
  205. "gpv", "owc", "slxc", "spib", "spid",
  206. "spie";
  207. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  208. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  209. };
  210. conf_ck32 {
  211. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  212. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  213. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  214. };
  215. conf_crtp {
  216. nvidia,pins = "crtp", "gmb", "slxa", "spia",
  217. "spig", "spih";
  218. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  219. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  220. };
  221. conf_dta {
  222. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  223. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  224. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  225. };
  226. conf_dte {
  227. nvidia,pins = "dte", "spif";
  228. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  229. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  230. };
  231. conf_hdint {
  232. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  233. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  234. "lvp0";
  235. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  236. };
  237. conf_kbca {
  238. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  239. "kbce", "kbcf", "sdio1", "spic", "uaa",
  240. "uab";
  241. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  242. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  243. };
  244. conf_lc {
  245. nvidia,pins = "lc", "ls";
  246. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  247. };
  248. conf_ld0 {
  249. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  250. "ld5", "ld6", "ld7", "ld8", "ld9",
  251. "ld10", "ld11", "ld12", "ld13", "ld14",
  252. "ld15", "ld16", "ld17", "ldi", "lhp0",
  253. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  254. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  255. "lvs", "pmc", "sdb";
  256. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  257. };
  258. conf_ld17_0 {
  259. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  260. "ld23_22";
  261. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  262. };
  263. drive_sdio1 {
  264. nvidia,pins = "drive_sdio1";
  265. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  266. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  267. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  268. nvidia,pull-down-strength = <31>;
  269. nvidia,pull-up-strength = <31>;
  270. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  271. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  272. };
  273. };
  274. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  275. ddc {
  276. nvidia,pins = "ddc";
  277. nvidia,function = "i2c2";
  278. };
  279. pta {
  280. nvidia,pins = "pta";
  281. nvidia,function = "rsvd4";
  282. };
  283. };
  284. state_i2cmux_pta: pinmux_i2cmux_pta {
  285. ddc {
  286. nvidia,pins = "ddc";
  287. nvidia,function = "rsvd4";
  288. };
  289. pta {
  290. nvidia,pins = "pta";
  291. nvidia,function = "i2c2";
  292. };
  293. };
  294. state_i2cmux_idle: pinmux_i2cmux_idle {
  295. ddc {
  296. nvidia,pins = "ddc";
  297. nvidia,function = "rsvd4";
  298. };
  299. pta {
  300. nvidia,pins = "pta";
  301. nvidia,function = "rsvd4";
  302. };
  303. };
  304. };
  305. i2s@70002800 {
  306. status = "okay";
  307. };
  308. serial@70006300 {
  309. status = "okay";
  310. };
  311. pwm: pwm@7000a000 {
  312. status = "okay";
  313. };
  314. i2c@7000c000 {
  315. status = "okay";
  316. clock-frequency = <400000>;
  317. wm8903: wm8903@1a {
  318. compatible = "wlf,wm8903";
  319. reg = <0x1a>;
  320. interrupt-parent = <&gpio>;
  321. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
  322. gpio-controller;
  323. #gpio-cells = <2>;
  324. micdet-cfg = <0>;
  325. micdet-delay = <100>;
  326. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  327. };
  328. /* ALS and proximity sensor */
  329. isl29018@44 {
  330. compatible = "isil,isl29018";
  331. reg = <0x44>;
  332. interrupt-parent = <&gpio>;
  333. interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
  334. };
  335. gyrometer@68 {
  336. compatible = "invn,mpu3050";
  337. reg = <0x68>;
  338. interrupt-parent = <&gpio>;
  339. interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
  340. };
  341. };
  342. i2c@7000c400 {
  343. status = "okay";
  344. clock-frequency = <100000>;
  345. };
  346. i2cmux {
  347. compatible = "i2c-mux-pinctrl";
  348. #address-cells = <1>;
  349. #size-cells = <0>;
  350. i2c-parent = <&{/i2c@7000c400}>;
  351. pinctrl-names = "ddc", "pta", "idle";
  352. pinctrl-0 = <&state_i2cmux_ddc>;
  353. pinctrl-1 = <&state_i2cmux_pta>;
  354. pinctrl-2 = <&state_i2cmux_idle>;
  355. hdmi_ddc: i2c@0 {
  356. reg = <0>;
  357. #address-cells = <1>;
  358. #size-cells = <0>;
  359. };
  360. lvds_ddc: i2c@1 {
  361. reg = <1>;
  362. #address-cells = <1>;
  363. #size-cells = <0>;
  364. smart-battery@b {
  365. compatible = "ti,bq20z75", "smart-battery-1.1";
  366. reg = <0xb>;
  367. ti,i2c-retry-count = <2>;
  368. ti,poll-retry-count = <10>;
  369. };
  370. };
  371. };
  372. i2c@7000c500 {
  373. status = "okay";
  374. clock-frequency = <400000>;
  375. };
  376. i2c@7000d000 {
  377. status = "okay";
  378. clock-frequency = <400000>;
  379. magnetometer@c {
  380. compatible = "asahi-kasei,ak8975";
  381. reg = <0xc>;
  382. interrupt-parent = <&gpio>;
  383. interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
  384. };
  385. pmic: tps6586x@34 {
  386. compatible = "ti,tps6586x";
  387. reg = <0x34>;
  388. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  389. ti,system-power-controller;
  390. #gpio-cells = <2>;
  391. gpio-controller;
  392. sys-supply = <&vdd_5v0_reg>;
  393. vin-sm0-supply = <&sys_reg>;
  394. vin-sm1-supply = <&sys_reg>;
  395. vin-sm2-supply = <&sys_reg>;
  396. vinldo01-supply = <&sm2_reg>;
  397. vinldo23-supply = <&sm2_reg>;
  398. vinldo4-supply = <&sm2_reg>;
  399. vinldo678-supply = <&sm2_reg>;
  400. vinldo9-supply = <&sm2_reg>;
  401. regulators {
  402. sys_reg: sys {
  403. regulator-name = "vdd_sys";
  404. regulator-always-on;
  405. };
  406. sm0 {
  407. regulator-name = "vdd_sm0,vdd_core";
  408. regulator-min-microvolt = <1300000>;
  409. regulator-max-microvolt = <1300000>;
  410. regulator-always-on;
  411. };
  412. sm1 {
  413. regulator-name = "vdd_sm1,vdd_cpu";
  414. regulator-min-microvolt = <1125000>;
  415. regulator-max-microvolt = <1125000>;
  416. regulator-always-on;
  417. };
  418. sm2_reg: sm2 {
  419. regulator-name = "vdd_sm2,vin_ldo*";
  420. regulator-min-microvolt = <3700000>;
  421. regulator-max-microvolt = <3700000>;
  422. regulator-always-on;
  423. };
  424. /* LDO0 is not connected to anything */
  425. ldo1 {
  426. regulator-name = "vdd_ldo1,avdd_pll*";
  427. regulator-min-microvolt = <1100000>;
  428. regulator-max-microvolt = <1100000>;
  429. regulator-always-on;
  430. };
  431. ldo2 {
  432. regulator-name = "vdd_ldo2,vdd_rtc";
  433. regulator-min-microvolt = <1200000>;
  434. regulator-max-microvolt = <1200000>;
  435. };
  436. ldo3 {
  437. regulator-name = "vdd_ldo3,avdd_usb*";
  438. regulator-min-microvolt = <3300000>;
  439. regulator-max-microvolt = <3300000>;
  440. regulator-always-on;
  441. };
  442. ldo4 {
  443. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  444. regulator-min-microvolt = <1800000>;
  445. regulator-max-microvolt = <1800000>;
  446. regulator-always-on;
  447. };
  448. ldo5 {
  449. regulator-name = "vdd_ldo5,vcore_mmc";
  450. regulator-min-microvolt = <2850000>;
  451. regulator-max-microvolt = <2850000>;
  452. regulator-always-on;
  453. };
  454. ldo6 {
  455. regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
  456. regulator-min-microvolt = <1800000>;
  457. regulator-max-microvolt = <1800000>;
  458. };
  459. hdmi_vdd_reg: ldo7 {
  460. regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
  461. regulator-min-microvolt = <3300000>;
  462. regulator-max-microvolt = <3300000>;
  463. };
  464. hdmi_pll_reg: ldo8 {
  465. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  466. regulator-min-microvolt = <1800000>;
  467. regulator-max-microvolt = <1800000>;
  468. };
  469. ldo9 {
  470. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  471. regulator-min-microvolt = <2850000>;
  472. regulator-max-microvolt = <2850000>;
  473. regulator-always-on;
  474. };
  475. ldo_rtc {
  476. regulator-name = "vdd_rtc_out,vdd_cell";
  477. regulator-min-microvolt = <3300000>;
  478. regulator-max-microvolt = <3300000>;
  479. regulator-always-on;
  480. };
  481. };
  482. };
  483. temperature-sensor@4c {
  484. compatible = "onnn,nct1008";
  485. reg = <0x4c>;
  486. };
  487. };
  488. kbc@7000e200 {
  489. status = "okay";
  490. nvidia,debounce-delay-ms = <32>;
  491. nvidia,repeat-delay-ms = <160>;
  492. nvidia,ghost-filter;
  493. nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  494. nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
  495. linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
  496. MATRIX_KEY(0x00, 0x03, KEY_S)
  497. MATRIX_KEY(0x00, 0x04, KEY_A)
  498. MATRIX_KEY(0x00, 0x05, KEY_Z)
  499. MATRIX_KEY(0x00, 0x07, KEY_FN)
  500. MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA)
  501. MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT)
  502. MATRIX_KEY(0x02, 0x07, KEY_LEFTALT)
  503. MATRIX_KEY(0x03, 0x00, KEY_5)
  504. MATRIX_KEY(0x03, 0x01, KEY_4)
  505. MATRIX_KEY(0x03, 0x02, KEY_R)
  506. MATRIX_KEY(0x03, 0x03, KEY_E)
  507. MATRIX_KEY(0x03, 0x04, KEY_F)
  508. MATRIX_KEY(0x03, 0x05, KEY_D)
  509. MATRIX_KEY(0x03, 0x06, KEY_X)
  510. MATRIX_KEY(0x04, 0x00, KEY_7)
  511. MATRIX_KEY(0x04, 0x01, KEY_6)
  512. MATRIX_KEY(0x04, 0x02, KEY_T)
  513. MATRIX_KEY(0x04, 0x03, KEY_H)
  514. MATRIX_KEY(0x04, 0x04, KEY_G)
  515. MATRIX_KEY(0x04, 0x05, KEY_V)
  516. MATRIX_KEY(0x04, 0x06, KEY_C)
  517. MATRIX_KEY(0x04, 0x07, KEY_SPACE)
  518. MATRIX_KEY(0x05, 0x00, KEY_9)
  519. MATRIX_KEY(0x05, 0x01, KEY_8)
  520. MATRIX_KEY(0x05, 0x02, KEY_U)
  521. MATRIX_KEY(0x05, 0x03, KEY_Y)
  522. MATRIX_KEY(0x05, 0x04, KEY_J)
  523. MATRIX_KEY(0x05, 0x05, KEY_N)
  524. MATRIX_KEY(0x05, 0x06, KEY_B)
  525. MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
  526. MATRIX_KEY(0x06, 0x00, KEY_MINUS)
  527. MATRIX_KEY(0x06, 0x01, KEY_0)
  528. MATRIX_KEY(0x06, 0x02, KEY_O)
  529. MATRIX_KEY(0x06, 0x03, KEY_I)
  530. MATRIX_KEY(0x06, 0x04, KEY_L)
  531. MATRIX_KEY(0x06, 0x05, KEY_K)
  532. MATRIX_KEY(0x06, 0x06, KEY_COMMA)
  533. MATRIX_KEY(0x06, 0x07, KEY_M)
  534. MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
  535. MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
  536. MATRIX_KEY(0x07, 0x03, KEY_ENTER)
  537. MATRIX_KEY(0x07, 0x07, KEY_MENU)
  538. MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
  539. MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
  540. MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL)
  541. MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL)
  542. MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
  543. MATRIX_KEY(0x0B, 0x01, KEY_P)
  544. MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
  545. MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
  546. MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
  547. MATRIX_KEY(0x0B, 0x05, KEY_DOT)
  548. MATRIX_KEY(0x0C, 0x00, KEY_F10)
  549. MATRIX_KEY(0x0C, 0x01, KEY_F9)
  550. MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
  551. MATRIX_KEY(0x0C, 0x03, KEY_3)
  552. MATRIX_KEY(0x0C, 0x04, KEY_2)
  553. MATRIX_KEY(0x0C, 0x05, KEY_UP)
  554. MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
  555. MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
  556. MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
  557. MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
  558. MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
  559. MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
  560. MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
  561. MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
  562. MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
  563. MATRIX_KEY(0x0E, 0x00, KEY_F11)
  564. MATRIX_KEY(0x0E, 0x01, KEY_F12)
  565. MATRIX_KEY(0x0E, 0x02, KEY_F8)
  566. MATRIX_KEY(0x0E, 0x03, KEY_Q)
  567. MATRIX_KEY(0x0E, 0x04, KEY_F4)
  568. MATRIX_KEY(0x0E, 0x05, KEY_F3)
  569. MATRIX_KEY(0x0E, 0x06, KEY_1)
  570. MATRIX_KEY(0x0E, 0x07, KEY_F7)
  571. MATRIX_KEY(0x0F, 0x00, KEY_ESC)
  572. MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
  573. MATRIX_KEY(0x0F, 0x02, KEY_F5)
  574. MATRIX_KEY(0x0F, 0x03, KEY_TAB)
  575. MATRIX_KEY(0x0F, 0x04, KEY_F1)
  576. MATRIX_KEY(0x0F, 0x05, KEY_F2)
  577. MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
  578. MATRIX_KEY(0x0F, 0x07, KEY_F6)
  579. /* Software Handled Function Keys */
  580. MATRIX_KEY(0x14, 0x00, KEY_KP7)
  581. MATRIX_KEY(0x15, 0x00, KEY_KP9)
  582. MATRIX_KEY(0x15, 0x01, KEY_KP8)
  583. MATRIX_KEY(0x15, 0x02, KEY_KP4)
  584. MATRIX_KEY(0x15, 0x04, KEY_KP1)
  585. MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
  586. MATRIX_KEY(0x16, 0x02, KEY_KP6)
  587. MATRIX_KEY(0x16, 0x03, KEY_KP5)
  588. MATRIX_KEY(0x16, 0x04, KEY_KP3)
  589. MATRIX_KEY(0x16, 0x05, KEY_KP2)
  590. MATRIX_KEY(0x16, 0x07, KEY_KP0)
  591. MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
  592. MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
  593. MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
  594. MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
  595. MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
  596. MATRIX_KEY(0x1D, 0x03, KEY_HOME)
  597. MATRIX_KEY(0x1D, 0x04, KEY_END)
  598. MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN)
  599. MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
  600. MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP)
  601. MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
  602. MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
  603. MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
  604. MATRIX_KEY(0x1F, 0x04, KEY_HELP)>;
  605. };
  606. pmc@7000e400 {
  607. nvidia,invert-interrupt;
  608. nvidia,suspend-mode = <1>;
  609. nvidia,cpu-pwr-good-time = <5000>;
  610. nvidia,cpu-pwr-off-time = <5000>;
  611. nvidia,core-pwr-good-time = <3845 3845>;
  612. nvidia,core-pwr-off-time = <3875>;
  613. nvidia,sys-clock-req-active-high;
  614. };
  615. memory-controller@7000f400 {
  616. emc-table@190000 {
  617. reg = <190000>;
  618. compatible = "nvidia,tegra20-emc-table";
  619. clock-frequency = <190000>;
  620. nvidia,emc-registers = <0x0000000c 0x00000026
  621. 0x00000009 0x00000003 0x00000004 0x00000004
  622. 0x00000002 0x0000000c 0x00000003 0x00000003
  623. 0x00000002 0x00000001 0x00000004 0x00000005
  624. 0x00000004 0x00000009 0x0000000d 0x0000059f
  625. 0x00000000 0x00000003 0x00000003 0x00000003
  626. 0x00000003 0x00000001 0x0000000b 0x000000c8
  627. 0x00000003 0x00000007 0x00000004 0x0000000f
  628. 0x00000002 0x00000000 0x00000000 0x00000002
  629. 0x00000000 0x00000000 0x00000083 0xa06204ae
  630. 0x007dc010 0x00000000 0x00000000 0x00000000
  631. 0x00000000 0x00000000 0x00000000 0x00000000>;
  632. };
  633. emc-table@380000 {
  634. reg = <380000>;
  635. compatible = "nvidia,tegra20-emc-table";
  636. clock-frequency = <380000>;
  637. nvidia,emc-registers = <0x00000017 0x0000004b
  638. 0x00000012 0x00000006 0x00000004 0x00000005
  639. 0x00000003 0x0000000c 0x00000006 0x00000006
  640. 0x00000003 0x00000001 0x00000004 0x00000005
  641. 0x00000004 0x00000009 0x0000000d 0x00000b5f
  642. 0x00000000 0x00000003 0x00000003 0x00000006
  643. 0x00000006 0x00000001 0x00000011 0x000000c8
  644. 0x00000003 0x0000000e 0x00000007 0x0000000f
  645. 0x00000002 0x00000000 0x00000000 0x00000002
  646. 0x00000000 0x00000000 0x00000083 0xe044048b
  647. 0x007d8010 0x00000000 0x00000000 0x00000000
  648. 0x00000000 0x00000000 0x00000000 0x00000000>;
  649. };
  650. };
  651. usb@c5000000 {
  652. status = "okay";
  653. dr_mode = "otg";
  654. };
  655. usb-phy@c5000000 {
  656. status = "okay";
  657. vbus-supply = <&vbus_reg>;
  658. dr_mode = "otg";
  659. };
  660. usb@c5004000 {
  661. status = "okay";
  662. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  663. GPIO_ACTIVE_LOW>;
  664. };
  665. usb-phy@c5004000 {
  666. status = "okay";
  667. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  668. GPIO_ACTIVE_LOW>;
  669. };
  670. usb@c5008000 {
  671. status = "okay";
  672. };
  673. usb-phy@c5008000 {
  674. status = "okay";
  675. };
  676. sdhci@c8000000 {
  677. status = "okay";
  678. power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  679. bus-width = <4>;
  680. keep-power-in-suspend;
  681. };
  682. sdhci@c8000400 {
  683. status = "okay";
  684. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  685. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  686. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  687. bus-width = <4>;
  688. };
  689. sdhci@c8000600 {
  690. status = "okay";
  691. bus-width = <8>;
  692. non-removable;
  693. };
  694. backlight: backlight {
  695. compatible = "pwm-backlight";
  696. enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
  697. power-supply = <&vdd_bl_reg>;
  698. pwms = <&pwm 2 5000000>;
  699. brightness-levels = <0 4 8 16 32 64 128 255>;
  700. default-brightness-level = <6>;
  701. };
  702. clocks {
  703. compatible = "simple-bus";
  704. #address-cells = <1>;
  705. #size-cells = <0>;
  706. clk32k_in: clock@0 {
  707. compatible = "fixed-clock";
  708. reg = <0>;
  709. #clock-cells = <0>;
  710. clock-frequency = <32768>;
  711. };
  712. };
  713. gpio-keys {
  714. compatible = "gpio-keys";
  715. power {
  716. label = "Power";
  717. gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  718. linux,code = <KEY_POWER>;
  719. wakeup-source;
  720. };
  721. lid {
  722. label = "Lid";
  723. gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
  724. linux,input-type = <5>; /* EV_SW */
  725. linux,code = <0>; /* SW_LID */
  726. debounce-interval = <1>;
  727. wakeup-source;
  728. };
  729. };
  730. panel: panel {
  731. compatible = "chunghwa,claa101wa01a", "simple-panel";
  732. power-supply = <&vdd_pnl_reg>;
  733. enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
  734. backlight = <&backlight>;
  735. ddc-i2c-bus = <&lvds_ddc>;
  736. };
  737. regulators {
  738. compatible = "simple-bus";
  739. #address-cells = <1>;
  740. #size-cells = <0>;
  741. vdd_5v0_reg: regulator@0 {
  742. compatible = "regulator-fixed";
  743. reg = <0>;
  744. regulator-name = "vdd_5v0";
  745. regulator-min-microvolt = <5000000>;
  746. regulator-max-microvolt = <5000000>;
  747. regulator-always-on;
  748. };
  749. regulator@1 {
  750. compatible = "regulator-fixed";
  751. reg = <1>;
  752. regulator-name = "vdd_1v5";
  753. regulator-min-microvolt = <1500000>;
  754. regulator-max-microvolt = <1500000>;
  755. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  756. };
  757. regulator@2 {
  758. compatible = "regulator-fixed";
  759. reg = <2>;
  760. regulator-name = "vdd_1v2";
  761. regulator-min-microvolt = <1200000>;
  762. regulator-max-microvolt = <1200000>;
  763. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  764. enable-active-high;
  765. };
  766. vbus_reg: regulator@3 {
  767. compatible = "regulator-fixed";
  768. reg = <3>;
  769. regulator-name = "vdd_vbus_wup1";
  770. regulator-min-microvolt = <5000000>;
  771. regulator-max-microvolt = <5000000>;
  772. enable-active-high;
  773. gpio = <&gpio TEGRA_GPIO(D, 0) 0>;
  774. regulator-always-on;
  775. regulator-boot-on;
  776. };
  777. vdd_pnl_reg: regulator@4 {
  778. compatible = "regulator-fixed";
  779. reg = <4>;
  780. regulator-name = "vdd_pnl";
  781. regulator-min-microvolt = <2800000>;
  782. regulator-max-microvolt = <2800000>;
  783. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  784. enable-active-high;
  785. };
  786. vdd_bl_reg: regulator@5 {
  787. compatible = "regulator-fixed";
  788. reg = <5>;
  789. regulator-name = "vdd_bl";
  790. regulator-min-microvolt = <2800000>;
  791. regulator-max-microvolt = <2800000>;
  792. gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
  793. enable-active-high;
  794. };
  795. vdd_hdmi: regulator@6 {
  796. compatible = "regulator-fixed";
  797. reg = <6>;
  798. regulator-name = "VDDIO_HDMI";
  799. regulator-min-microvolt = <5000000>;
  800. regulator-max-microvolt = <5000000>;
  801. gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
  802. enable-active-high;
  803. vin-supply = <&vdd_5v0_reg>;
  804. };
  805. };
  806. sound {
  807. compatible = "nvidia,tegra-audio-wm8903-seaboard",
  808. "nvidia,tegra-audio-wm8903";
  809. nvidia,model = "NVIDIA Tegra Seaboard";
  810. nvidia,audio-routing =
  811. "Headphone Jack", "HPOUTR",
  812. "Headphone Jack", "HPOUTL",
  813. "Int Spk", "ROP",
  814. "Int Spk", "RON",
  815. "Int Spk", "LOP",
  816. "Int Spk", "LON",
  817. "Mic Jack", "MICBIAS",
  818. "IN1R", "Mic Jack";
  819. nvidia,i2s-controller = <&tegra_i2s1>;
  820. nvidia,audio-codec = <&wm8903>;
  821. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  822. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
  823. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  824. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  825. <&tegra_car TEGRA20_CLK_CDEV1>;
  826. clock-names = "pll_a", "pll_a_out0", "mclk";
  827. };
  828. };