tegra124-jetson-tk1.dts 55 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra124.dtsi"
  4. #include "tegra124-jetson-tk1-emc.dtsi"
  5. / {
  6. model = "NVIDIA Tegra124 Jetson TK1";
  7. compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
  8. aliases {
  9. rtc0 = "/i2c@7000d000/pmic@40";
  10. rtc1 = "/rtc@7000e000";
  11. /* This order keeps the mapping DB9 connector <-> ttyS0 */
  12. serial0 = &uartd;
  13. serial1 = &uarta;
  14. serial2 = &uartb;
  15. };
  16. chosen {
  17. stdout-path = "serial0:115200n8";
  18. };
  19. memory {
  20. reg = <0x0 0x80000000 0x0 0x80000000>;
  21. };
  22. pcie-controller@01003000 {
  23. status = "okay";
  24. avddio-pex-supply = <&vdd_1v05_run>;
  25. dvddio-pex-supply = <&vdd_1v05_run>;
  26. avdd-pex-pll-supply = <&vdd_1v05_run>;
  27. hvdd-pex-supply = <&vdd_3v3_lp0>;
  28. hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
  29. vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
  30. avdd-pll-erefe-supply = <&avdd_1v05_run>;
  31. /* Mini PCIe */
  32. pci@1,0 {
  33. phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
  34. phy-names = "pcie-0";
  35. status = "okay";
  36. };
  37. /* Gigabit Ethernet */
  38. pci@2,0 {
  39. phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
  40. phy-names = "pcie-0";
  41. status = "okay";
  42. };
  43. };
  44. host1x@50000000 {
  45. hdmi@54280000 {
  46. status = "okay";
  47. hdmi-supply = <&vdd_5v0_hdmi>;
  48. pll-supply = <&vdd_hdmi_pll>;
  49. vdd-supply = <&vdd_3v3_hdmi>;
  50. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  51. nvidia,hpd-gpio =
  52. <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  53. };
  54. };
  55. gpu@0,57000000 {
  56. /*
  57. * Node left disabled on purpose - the bootloader will enable
  58. * it after having set the VPR up
  59. */
  60. vdd-supply = <&vdd_gpu>;
  61. };
  62. pinmux: pinmux@70000868 {
  63. pinctrl-names = "boot";
  64. pinctrl-0 = <&state_boot>;
  65. state_boot: pinmux {
  66. clk_32k_out_pa0 {
  67. nvidia,pins = "clk_32k_out_pa0";
  68. nvidia,function = "soc";
  69. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  70. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  71. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  72. };
  73. uart3_cts_n_pa1 {
  74. nvidia,pins = "uart3_cts_n_pa1";
  75. nvidia,function = "gmi";
  76. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  77. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  78. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  79. };
  80. dap2_fs_pa2 {
  81. nvidia,pins = "dap2_fs_pa2";
  82. nvidia,function = "i2s1";
  83. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  84. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  85. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  86. };
  87. dap2_sclk_pa3 {
  88. nvidia,pins = "dap2_sclk_pa3";
  89. nvidia,function = "i2s1";
  90. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  91. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  92. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  93. };
  94. dap2_din_pa4 {
  95. nvidia,pins = "dap2_din_pa4";
  96. nvidia,function = "i2s1";
  97. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  98. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  99. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  100. };
  101. dap2_dout_pa5 {
  102. nvidia,pins = "dap2_dout_pa5";
  103. nvidia,function = "i2s1";
  104. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  105. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  106. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  107. };
  108. sdmmc3_clk_pa6 {
  109. nvidia,pins = "sdmmc3_clk_pa6";
  110. nvidia,function = "sdmmc3";
  111. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  112. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  113. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  114. };
  115. sdmmc3_cmd_pa7 {
  116. nvidia,pins = "sdmmc3_cmd_pa7";
  117. nvidia,function = "sdmmc3";
  118. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  119. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  120. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  121. };
  122. pb0 {
  123. nvidia,pins = "pb0";
  124. nvidia,function = "uartd";
  125. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  126. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  127. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  128. };
  129. pb1 {
  130. nvidia,pins = "pb1";
  131. nvidia,function = "uartd";
  132. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  133. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  134. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  135. };
  136. sdmmc3_dat3_pb4 {
  137. nvidia,pins = "sdmmc3_dat3_pb4";
  138. nvidia,function = "sdmmc3";
  139. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  140. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  141. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  142. };
  143. sdmmc3_dat2_pb5 {
  144. nvidia,pins = "sdmmc3_dat2_pb5";
  145. nvidia,function = "sdmmc3";
  146. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  147. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  148. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  149. };
  150. sdmmc3_dat1_pb6 {
  151. nvidia,pins = "sdmmc3_dat1_pb6";
  152. nvidia,function = "sdmmc3";
  153. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  154. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  155. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  156. };
  157. sdmmc3_dat0_pb7 {
  158. nvidia,pins = "sdmmc3_dat0_pb7";
  159. nvidia,function = "sdmmc3";
  160. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  161. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  162. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  163. };
  164. uart3_rts_n_pc0 {
  165. nvidia,pins = "uart3_rts_n_pc0";
  166. nvidia,function = "gmi";
  167. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  168. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  169. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  170. };
  171. uart2_txd_pc2 {
  172. nvidia,pins = "uart2_txd_pc2";
  173. nvidia,function = "irda";
  174. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  175. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  176. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  177. };
  178. uart2_rxd_pc3 {
  179. nvidia,pins = "uart2_rxd_pc3";
  180. nvidia,function = "irda";
  181. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  182. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  183. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  184. };
  185. gen1_i2c_scl_pc4 {
  186. nvidia,pins = "gen1_i2c_scl_pc4";
  187. nvidia,function = "i2c1";
  188. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  189. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  190. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  191. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  192. };
  193. gen1_i2c_sda_pc5 {
  194. nvidia,pins = "gen1_i2c_sda_pc5";
  195. nvidia,function = "i2c1";
  196. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  197. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  198. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  199. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  200. };
  201. pc7 {
  202. nvidia,pins = "pc7";
  203. nvidia,function = "rsvd1";
  204. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  205. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  206. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  207. };
  208. pg0 {
  209. nvidia,pins = "pg0";
  210. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  211. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  212. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  213. };
  214. pg1 {
  215. nvidia,pins = "pg1";
  216. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  217. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  218. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  219. };
  220. pg2 {
  221. nvidia,pins = "pg2";
  222. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  223. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  224. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  225. };
  226. pg3 {
  227. nvidia,pins = "pg3";
  228. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  229. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  230. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  231. };
  232. pg4 {
  233. nvidia,pins = "pg4";
  234. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  235. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  236. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  237. };
  238. pg5 {
  239. nvidia,pins = "pg5";
  240. nvidia,function = "spi4";
  241. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  242. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  243. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  244. };
  245. pg6 {
  246. nvidia,pins = "pg6";
  247. nvidia,function = "spi4";
  248. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  249. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  250. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  251. };
  252. pg7 {
  253. nvidia,pins = "pg7";
  254. nvidia,function = "spi4";
  255. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  256. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  257. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  258. };
  259. ph0 {
  260. nvidia,pins = "ph0";
  261. nvidia,function = "gmi";
  262. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  263. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  264. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  265. };
  266. ph1 {
  267. nvidia,pins = "ph1";
  268. nvidia,function = "pwm1";
  269. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  270. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  271. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  272. };
  273. ph2 {
  274. nvidia,pins = "ph2";
  275. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  276. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  277. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  278. };
  279. ph3 {
  280. nvidia,pins = "ph3";
  281. nvidia,function = "gmi";
  282. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  283. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  284. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  285. };
  286. ph4 {
  287. nvidia,pins = "ph4";
  288. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  289. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  290. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  291. };
  292. ph5 {
  293. nvidia,pins = "ph5";
  294. nvidia,function = "rsvd2";
  295. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  296. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  297. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  298. };
  299. ph6 {
  300. nvidia,pins = "ph6";
  301. nvidia,function = "gmi";
  302. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  303. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  304. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  305. };
  306. ph7 {
  307. nvidia,pins = "ph7";
  308. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  309. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  310. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  311. };
  312. pi0 {
  313. nvidia,pins = "pi0";
  314. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  315. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  316. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  317. };
  318. pi1 {
  319. nvidia,pins = "pi1";
  320. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  321. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  322. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  323. };
  324. pi2 {
  325. nvidia,pins = "pi2";
  326. nvidia,function = "rsvd4";
  327. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  328. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  329. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  330. };
  331. pi3 {
  332. nvidia,pins = "pi3";
  333. nvidia,function = "spi4";
  334. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  335. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  336. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  337. };
  338. pi4 {
  339. nvidia,pins = "pi4";
  340. nvidia,function = "gmi";
  341. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  342. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  343. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  344. };
  345. pi5 {
  346. nvidia,pins = "pi5";
  347. nvidia,function = "rsvd2";
  348. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  349. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  350. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  351. };
  352. pi6 {
  353. nvidia,pins = "pi6";
  354. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  355. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  356. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  357. };
  358. pi7 {
  359. nvidia,pins = "pi7";
  360. nvidia,function = "rsvd1";
  361. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  362. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  363. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  364. };
  365. pj0 {
  366. nvidia,pins = "pj0";
  367. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  368. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  369. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  370. };
  371. pj2 {
  372. nvidia,pins = "pj2";
  373. nvidia,function = "rsvd1";
  374. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  375. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  376. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  377. };
  378. uart2_cts_n_pj5 {
  379. nvidia,pins = "uart2_cts_n_pj5";
  380. nvidia,function = "uartb";
  381. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  382. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  383. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  384. };
  385. uart2_rts_n_pj6 {
  386. nvidia,pins = "uart2_rts_n_pj6";
  387. nvidia,function = "uartb";
  388. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  389. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  390. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  391. };
  392. pj7 {
  393. nvidia,pins = "pj7";
  394. nvidia,function = "uartd";
  395. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  396. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  397. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  398. };
  399. pk0 {
  400. nvidia,pins = "pk0";
  401. nvidia,function = "rsvd1";
  402. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  403. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  404. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  405. };
  406. pk1 {
  407. nvidia,pins = "pk1";
  408. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  409. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  410. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  411. };
  412. pk2 {
  413. nvidia,pins = "pk2";
  414. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  415. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  416. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  417. };
  418. pk3 {
  419. nvidia,pins = "pk3";
  420. nvidia,function = "gmi";
  421. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  422. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  423. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  424. };
  425. pk4 {
  426. nvidia,pins = "pk4";
  427. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  428. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  429. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  430. };
  431. spdif_out_pk5 {
  432. nvidia,pins = "spdif_out_pk5";
  433. nvidia,function = "rsvd2";
  434. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  435. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  436. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  437. };
  438. spdif_in_pk6 {
  439. nvidia,pins = "spdif_in_pk6";
  440. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  441. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  442. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  443. };
  444. pk7 {
  445. nvidia,pins = "pk7";
  446. nvidia,function = "uartd";
  447. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  448. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  449. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  450. };
  451. dap1_fs_pn0 {
  452. nvidia,pins = "dap1_fs_pn0";
  453. nvidia,function = "rsvd4";
  454. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  455. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  456. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  457. };
  458. dap1_din_pn1 {
  459. nvidia,pins = "dap1_din_pn1";
  460. nvidia,function = "rsvd4";
  461. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  462. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  463. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  464. };
  465. dap1_dout_pn2 {
  466. nvidia,pins = "dap1_dout_pn2";
  467. nvidia,function = "sata";
  468. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  469. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  470. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  471. };
  472. dap1_sclk_pn3 {
  473. nvidia,pins = "dap1_sclk_pn3";
  474. nvidia,function = "rsvd4";
  475. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  476. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  477. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  478. };
  479. usb_vbus_en0_pn4 {
  480. nvidia,pins = "usb_vbus_en0_pn4";
  481. nvidia,function = "usb";
  482. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  483. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  484. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  485. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  486. };
  487. usb_vbus_en1_pn5 {
  488. nvidia,pins = "usb_vbus_en1_pn5";
  489. nvidia,function = "usb";
  490. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  491. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  492. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  493. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  494. };
  495. hdmi_int_pn7 {
  496. nvidia,pins = "hdmi_int_pn7";
  497. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  498. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  499. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  500. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  501. };
  502. ulpi_data7_po0 {
  503. nvidia,pins = "ulpi_data7_po0";
  504. nvidia,function = "ulpi";
  505. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  506. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  507. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  508. };
  509. ulpi_data0_po1 {
  510. nvidia,pins = "ulpi_data0_po1";
  511. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  512. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  513. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  514. };
  515. ulpi_data1_po2 {
  516. nvidia,pins = "ulpi_data1_po2";
  517. nvidia,function = "ulpi";
  518. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  519. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  520. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  521. };
  522. ulpi_data2_po3 {
  523. nvidia,pins = "ulpi_data2_po3";
  524. nvidia,function = "ulpi";
  525. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  526. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  527. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  528. };
  529. ulpi_data3_po4 {
  530. nvidia,pins = "ulpi_data3_po4";
  531. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  532. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  533. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  534. };
  535. ulpi_data4_po5 {
  536. nvidia,pins = "ulpi_data4_po5";
  537. nvidia,function = "ulpi";
  538. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  539. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  540. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  541. };
  542. ulpi_data5_po6 {
  543. nvidia,pins = "ulpi_data5_po6";
  544. nvidia,function = "ulpi";
  545. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  546. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  547. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  548. };
  549. ulpi_data6_po7 {
  550. nvidia,pins = "ulpi_data6_po7";
  551. nvidia,function = "ulpi";
  552. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  553. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  554. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  555. };
  556. dap3_fs_pp0 {
  557. nvidia,pins = "dap3_fs_pp0";
  558. nvidia,function = "i2s2";
  559. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  560. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  561. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  562. };
  563. dap3_din_pp1 {
  564. nvidia,pins = "dap3_din_pp1";
  565. nvidia,function = "i2s2";
  566. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  567. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  568. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  569. };
  570. dap3_dout_pp2 {
  571. nvidia,pins = "dap3_dout_pp2";
  572. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  573. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  574. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  575. };
  576. dap3_sclk_pp3 {
  577. nvidia,pins = "dap3_sclk_pp3";
  578. nvidia,function = "rsvd3";
  579. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  580. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  581. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  582. };
  583. dap4_fs_pp4 {
  584. nvidia,pins = "dap4_fs_pp4";
  585. nvidia,function = "rsvd4";
  586. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  587. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  588. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  589. };
  590. dap4_din_pp5 {
  591. nvidia,pins = "dap4_din_pp5";
  592. nvidia,function = "rsvd3";
  593. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  594. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  595. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  596. };
  597. dap4_dout_pp6 {
  598. nvidia,pins = "dap4_dout_pp6";
  599. nvidia,function = "rsvd4";
  600. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  601. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  602. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  603. };
  604. dap4_sclk_pp7 {
  605. nvidia,pins = "dap4_sclk_pp7";
  606. nvidia,function = "rsvd3";
  607. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  608. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  609. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  610. };
  611. kb_col0_pq0 {
  612. nvidia,pins = "kb_col0_pq0";
  613. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  614. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  615. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  616. };
  617. kb_col1_pq1 {
  618. nvidia,pins = "kb_col1_pq1";
  619. nvidia,function = "rsvd2";
  620. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  621. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  622. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  623. };
  624. kb_col2_pq2 {
  625. nvidia,pins = "kb_col2_pq2";
  626. nvidia,function = "rsvd2";
  627. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  628. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  629. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  630. };
  631. kb_col3_pq3 {
  632. nvidia,pins = "kb_col3_pq3";
  633. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  634. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  635. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  636. };
  637. kb_col4_pq4 {
  638. nvidia,pins = "kb_col4_pq4";
  639. nvidia,function = "sdmmc3";
  640. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  641. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  642. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  643. };
  644. kb_col5_pq5 {
  645. nvidia,pins = "kb_col5_pq5";
  646. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  647. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  648. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  649. };
  650. kb_col6_pq6 {
  651. nvidia,pins = "kb_col6_pq6";
  652. nvidia,function = "rsvd2";
  653. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  654. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  655. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  656. };
  657. kb_col7_pq7 {
  658. nvidia,pins = "kb_col7_pq7";
  659. nvidia,function = "rsvd2";
  660. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  661. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  662. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  663. };
  664. kb_row0_pr0 {
  665. nvidia,pins = "kb_row0_pr0";
  666. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  667. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  668. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  669. };
  670. kb_row1_pr1 {
  671. nvidia,pins = "kb_row1_pr1";
  672. nvidia,function = "rsvd2";
  673. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  674. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  675. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  676. };
  677. kb_row2_pr2 {
  678. nvidia,pins = "kb_row2_pr2";
  679. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  680. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  681. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  682. };
  683. kb_row3_pr3 {
  684. nvidia,pins = "kb_row3_pr3";
  685. nvidia,function = "kbc";
  686. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  687. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  688. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  689. };
  690. kb_row4_pr4 {
  691. nvidia,pins = "kb_row4_pr4";
  692. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  693. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  694. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  695. };
  696. kb_row5_pr5 {
  697. nvidia,pins = "kb_row5_pr5";
  698. nvidia,function = "rsvd3";
  699. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  700. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  701. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  702. };
  703. kb_row6_pr6 {
  704. nvidia,pins = "kb_row6_pr6";
  705. nvidia,function = "displaya_alt";
  706. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  707. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  708. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  709. };
  710. kb_row7_pr7 {
  711. nvidia,pins = "kb_row7_pr7";
  712. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  713. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  714. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  715. };
  716. kb_row8_ps0 {
  717. nvidia,pins = "kb_row8_ps0";
  718. nvidia,function = "rsvd2";
  719. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  720. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  721. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  722. };
  723. kb_row9_ps1 {
  724. nvidia,pins = "kb_row9_ps1";
  725. nvidia,function = "uarta";
  726. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  727. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  728. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  729. };
  730. kb_row10_ps2 {
  731. nvidia,pins = "kb_row10_ps2";
  732. nvidia,function = "uarta";
  733. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  734. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  735. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  736. };
  737. kb_row11_ps3 {
  738. nvidia,pins = "kb_row11_ps3";
  739. nvidia,function = "rsvd2";
  740. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  741. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  742. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  743. };
  744. kb_row12_ps4 {
  745. nvidia,pins = "kb_row12_ps4";
  746. nvidia,function = "rsvd2";
  747. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  748. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  749. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  750. };
  751. kb_row13_ps5 {
  752. nvidia,pins = "kb_row13_ps5";
  753. nvidia,function = "rsvd2";
  754. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  755. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  756. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  757. };
  758. kb_row14_ps6 {
  759. nvidia,pins = "kb_row14_ps6";
  760. nvidia,function = "rsvd2";
  761. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  762. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  763. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  764. };
  765. kb_row15_ps7 {
  766. nvidia,pins = "kb_row15_ps7";
  767. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  768. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  769. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  770. };
  771. kb_row16_pt0 {
  772. nvidia,pins = "kb_row16_pt0";
  773. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  774. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  775. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  776. };
  777. kb_row17_pt1 {
  778. nvidia,pins = "kb_row17_pt1";
  779. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  780. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  781. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  782. };
  783. gen2_i2c_scl_pt5 {
  784. nvidia,pins = "gen2_i2c_scl_pt5";
  785. nvidia,function = "i2c2";
  786. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  787. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  788. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  789. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  790. };
  791. gen2_i2c_sda_pt6 {
  792. nvidia,pins = "gen2_i2c_sda_pt6";
  793. nvidia,function = "i2c2";
  794. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  795. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  796. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  797. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  798. };
  799. sdmmc4_cmd_pt7 {
  800. nvidia,pins = "sdmmc4_cmd_pt7";
  801. nvidia,function = "sdmmc4";
  802. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  803. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  804. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  805. };
  806. pu0 {
  807. nvidia,pins = "pu0";
  808. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  809. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  810. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  811. };
  812. pu1 {
  813. nvidia,pins = "pu1";
  814. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  815. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  816. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  817. };
  818. pu2 {
  819. nvidia,pins = "pu2";
  820. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  821. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  822. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  823. };
  824. pu3 {
  825. nvidia,pins = "pu3";
  826. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  827. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  828. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  829. };
  830. pu4 {
  831. nvidia,pins = "pu4";
  832. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  833. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  834. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  835. };
  836. pu5 {
  837. nvidia,pins = "pu5";
  838. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  839. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  840. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  841. };
  842. pu6 {
  843. nvidia,pins = "pu6";
  844. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  845. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  846. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  847. };
  848. pv0 {
  849. nvidia,pins = "pv0";
  850. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  851. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  852. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  853. };
  854. pv1 {
  855. nvidia,pins = "pv1";
  856. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  857. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  858. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  859. };
  860. sdmmc3_cd_n_pv2 {
  861. nvidia,pins = "sdmmc3_cd_n_pv2";
  862. nvidia,function = "sdmmc3";
  863. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  864. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  865. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  866. };
  867. sdmmc1_wp_n_pv3 {
  868. nvidia,pins = "sdmmc1_wp_n_pv3";
  869. nvidia,function = "sdmmc1";
  870. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  871. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  872. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  873. };
  874. ddc_scl_pv4 {
  875. nvidia,pins = "ddc_scl_pv4";
  876. nvidia,function = "i2c4";
  877. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  878. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  879. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  880. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  881. };
  882. ddc_sda_pv5 {
  883. nvidia,pins = "ddc_sda_pv5";
  884. nvidia,function = "i2c4";
  885. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  886. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  887. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  888. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  889. };
  890. gpio_w2_aud_pw2 {
  891. nvidia,pins = "gpio_w2_aud_pw2";
  892. nvidia,function = "rsvd2";
  893. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  894. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  895. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  896. };
  897. gpio_w3_aud_pw3 {
  898. nvidia,pins = "gpio_w3_aud_pw3";
  899. nvidia,function = "spi6";
  900. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  901. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  902. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  903. };
  904. dap_mclk1_pw4 {
  905. nvidia,pins = "dap_mclk1_pw4";
  906. nvidia,function = "extperiph1";
  907. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  908. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  909. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  910. };
  911. clk2_out_pw5 {
  912. nvidia,pins = "clk2_out_pw5";
  913. nvidia,function = "extperiph2";
  914. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  915. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  916. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  917. };
  918. uart3_txd_pw6 {
  919. nvidia,pins = "uart3_txd_pw6";
  920. nvidia,function = "rsvd2";
  921. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  922. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  923. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  924. };
  925. uart3_rxd_pw7 {
  926. nvidia,pins = "uart3_rxd_pw7";
  927. nvidia,function = "rsvd2";
  928. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  929. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  930. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  931. };
  932. dvfs_pwm_px0 {
  933. nvidia,pins = "dvfs_pwm_px0";
  934. nvidia,function = "cldvfs";
  935. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  936. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  937. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  938. };
  939. gpio_x1_aud_px1 {
  940. nvidia,pins = "gpio_x1_aud_px1";
  941. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  942. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  943. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  944. };
  945. dvfs_clk_px2 {
  946. nvidia,pins = "dvfs_clk_px2";
  947. nvidia,function = "cldvfs";
  948. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  949. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  950. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  951. };
  952. gpio_x3_aud_px3 {
  953. nvidia,pins = "gpio_x3_aud_px3";
  954. nvidia,function = "rsvd4";
  955. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  956. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  957. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  958. };
  959. gpio_x4_aud_px4 {
  960. nvidia,pins = "gpio_x4_aud_px4";
  961. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  962. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  963. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  964. };
  965. gpio_x5_aud_px5 {
  966. nvidia,pins = "gpio_x5_aud_px5";
  967. nvidia,function = "rsvd4";
  968. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  969. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  970. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  971. };
  972. gpio_x6_aud_px6 {
  973. nvidia,pins = "gpio_x6_aud_px6";
  974. nvidia,function = "gmi";
  975. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  976. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  977. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  978. };
  979. gpio_x7_aud_px7 {
  980. nvidia,pins = "gpio_x7_aud_px7";
  981. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  982. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  983. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  984. };
  985. ulpi_clk_py0 {
  986. nvidia,pins = "ulpi_clk_py0";
  987. nvidia,function = "spi1";
  988. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  989. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  990. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  991. };
  992. ulpi_dir_py1 {
  993. nvidia,pins = "ulpi_dir_py1";
  994. nvidia,function = "spi1";
  995. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  996. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  997. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  998. };
  999. ulpi_nxt_py2 {
  1000. nvidia,pins = "ulpi_nxt_py2";
  1001. nvidia,function = "spi1";
  1002. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1003. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1004. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1005. };
  1006. ulpi_stp_py3 {
  1007. nvidia,pins = "ulpi_stp_py3";
  1008. nvidia,function = "spi1";
  1009. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1010. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1011. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1012. };
  1013. sdmmc1_dat3_py4 {
  1014. nvidia,pins = "sdmmc1_dat3_py4";
  1015. nvidia,function = "sdmmc1";
  1016. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1017. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1018. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1019. };
  1020. sdmmc1_dat2_py5 {
  1021. nvidia,pins = "sdmmc1_dat2_py5";
  1022. nvidia,function = "sdmmc1";
  1023. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1024. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1025. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1026. };
  1027. sdmmc1_dat1_py6 {
  1028. nvidia,pins = "sdmmc1_dat1_py6";
  1029. nvidia,function = "sdmmc1";
  1030. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1031. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1032. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1033. };
  1034. sdmmc1_dat0_py7 {
  1035. nvidia,pins = "sdmmc1_dat0_py7";
  1036. nvidia,function = "rsvd2";
  1037. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1038. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1039. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1040. };
  1041. sdmmc1_clk_pz0 {
  1042. nvidia,pins = "sdmmc1_clk_pz0";
  1043. nvidia,function = "rsvd3";
  1044. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1045. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1046. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1047. };
  1048. sdmmc1_cmd_pz1 {
  1049. nvidia,pins = "sdmmc1_cmd_pz1";
  1050. nvidia,function = "sdmmc1";
  1051. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1052. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1053. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1054. };
  1055. pwr_i2c_scl_pz6 {
  1056. nvidia,pins = "pwr_i2c_scl_pz6";
  1057. nvidia,function = "i2cpwr";
  1058. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1059. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1060. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1061. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1062. };
  1063. pwr_i2c_sda_pz7 {
  1064. nvidia,pins = "pwr_i2c_sda_pz7";
  1065. nvidia,function = "i2cpwr";
  1066. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1067. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1068. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1069. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1070. };
  1071. sdmmc4_dat0_paa0 {
  1072. nvidia,pins = "sdmmc4_dat0_paa0";
  1073. nvidia,function = "sdmmc4";
  1074. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1075. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1076. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1077. };
  1078. sdmmc4_dat1_paa1 {
  1079. nvidia,pins = "sdmmc4_dat1_paa1";
  1080. nvidia,function = "sdmmc4";
  1081. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1082. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1083. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1084. };
  1085. sdmmc4_dat2_paa2 {
  1086. nvidia,pins = "sdmmc4_dat2_paa2";
  1087. nvidia,function = "sdmmc4";
  1088. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1089. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1090. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1091. };
  1092. sdmmc4_dat3_paa3 {
  1093. nvidia,pins = "sdmmc4_dat3_paa3";
  1094. nvidia,function = "sdmmc4";
  1095. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1096. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1097. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1098. };
  1099. sdmmc4_dat4_paa4 {
  1100. nvidia,pins = "sdmmc4_dat4_paa4";
  1101. nvidia,function = "sdmmc4";
  1102. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1103. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1104. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1105. };
  1106. sdmmc4_dat5_paa5 {
  1107. nvidia,pins = "sdmmc4_dat5_paa5";
  1108. nvidia,function = "sdmmc4";
  1109. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1110. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1111. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1112. };
  1113. sdmmc4_dat6_paa6 {
  1114. nvidia,pins = "sdmmc4_dat6_paa6";
  1115. nvidia,function = "sdmmc4";
  1116. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1117. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1118. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1119. };
  1120. sdmmc4_dat7_paa7 {
  1121. nvidia,pins = "sdmmc4_dat7_paa7";
  1122. nvidia,function = "sdmmc4";
  1123. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1124. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1125. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1126. };
  1127. pbb0 {
  1128. nvidia,pins = "pbb0";
  1129. nvidia,function = "vimclk2_alt";
  1130. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1131. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1132. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1133. };
  1134. cam_i2c_scl_pbb1 {
  1135. nvidia,pins = "cam_i2c_scl_pbb1";
  1136. nvidia,function = "i2c3";
  1137. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1138. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1139. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1140. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1141. };
  1142. cam_i2c_sda_pbb2 {
  1143. nvidia,pins = "cam_i2c_sda_pbb2";
  1144. nvidia,function = "i2c3";
  1145. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1146. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1147. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1148. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1149. };
  1150. pbb3 {
  1151. nvidia,pins = "pbb3";
  1152. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1153. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1154. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1155. };
  1156. pbb4 {
  1157. nvidia,pins = "pbb4";
  1158. nvidia,function = "vgp4";
  1159. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1160. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1161. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1162. };
  1163. pbb5 {
  1164. nvidia,pins = "pbb5";
  1165. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1166. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1167. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1168. };
  1169. pbb6 {
  1170. nvidia,pins = "pbb6";
  1171. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1172. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1173. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1174. };
  1175. pbb7 {
  1176. nvidia,pins = "pbb7";
  1177. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1178. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1179. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1180. };
  1181. cam_mclk_pcc0 {
  1182. nvidia,pins = "cam_mclk_pcc0";
  1183. nvidia,function = "vi_alt3";
  1184. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1185. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1186. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1187. };
  1188. pcc1 {
  1189. nvidia,pins = "pcc1";
  1190. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1191. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1192. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1193. };
  1194. pcc2 {
  1195. nvidia,pins = "pcc2";
  1196. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1197. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1198. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1199. };
  1200. sdmmc4_clk_pcc4 {
  1201. nvidia,pins = "sdmmc4_clk_pcc4";
  1202. nvidia,function = "sdmmc4";
  1203. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1204. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1205. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1206. };
  1207. clk2_req_pcc5 {
  1208. nvidia,pins = "clk2_req_pcc5";
  1209. nvidia,function = "rsvd2";
  1210. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1211. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1212. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1213. };
  1214. pex_l0_rst_n_pdd1 {
  1215. nvidia,pins = "pex_l0_rst_n_pdd1";
  1216. nvidia,function = "pe0";
  1217. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1218. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1219. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1220. };
  1221. pex_l0_clkreq_n_pdd2 {
  1222. nvidia,pins = "pex_l0_clkreq_n_pdd2";
  1223. nvidia,function = "pe0";
  1224. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1225. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1226. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1227. };
  1228. pex_wake_n_pdd3 {
  1229. nvidia,pins = "pex_wake_n_pdd3";
  1230. nvidia,function = "pe";
  1231. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1232. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1233. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1234. };
  1235. pex_l1_rst_n_pdd5 {
  1236. nvidia,pins = "pex_l1_rst_n_pdd5";
  1237. nvidia,function = "pe1";
  1238. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1239. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1240. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1241. };
  1242. pex_l1_clkreq_n_pdd6 {
  1243. nvidia,pins = "pex_l1_clkreq_n_pdd6";
  1244. nvidia,function = "pe1";
  1245. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1246. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1247. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1248. };
  1249. clk3_out_pee0 {
  1250. nvidia,pins = "clk3_out_pee0";
  1251. nvidia,function = "extperiph3";
  1252. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1253. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1254. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1255. };
  1256. clk3_req_pee1 {
  1257. nvidia,pins = "clk3_req_pee1";
  1258. nvidia,function = "rsvd2";
  1259. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1260. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1261. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1262. };
  1263. dap_mclk1_req_pee2 {
  1264. nvidia,pins = "dap_mclk1_req_pee2";
  1265. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1266. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1267. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1268. };
  1269. hdmi_cec_pee3 {
  1270. nvidia,pins = "hdmi_cec_pee3";
  1271. nvidia,function = "cec";
  1272. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1273. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1274. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1275. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1276. };
  1277. sdmmc3_clk_lb_out_pee4 {
  1278. nvidia,pins = "sdmmc3_clk_lb_out_pee4";
  1279. nvidia,function = "sdmmc3";
  1280. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1281. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1282. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1283. };
  1284. sdmmc3_clk_lb_in_pee5 {
  1285. nvidia,pins = "sdmmc3_clk_lb_in_pee5";
  1286. nvidia,function = "sdmmc3";
  1287. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1288. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1289. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1290. };
  1291. dp_hpd_pff0 {
  1292. nvidia,pins = "dp_hpd_pff0";
  1293. nvidia,function = "dp";
  1294. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1295. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1296. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1297. };
  1298. usb_vbus_en2_pff1 {
  1299. nvidia,pins = "usb_vbus_en2_pff1";
  1300. nvidia,function = "rsvd2";
  1301. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1302. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1303. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1304. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1305. };
  1306. pff2 {
  1307. nvidia,pins = "pff2";
  1308. nvidia,function = "rsvd2";
  1309. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1310. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1311. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1312. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1313. };
  1314. core_pwr_req {
  1315. nvidia,pins = "core_pwr_req";
  1316. nvidia,function = "pwron";
  1317. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1318. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1319. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1320. };
  1321. cpu_pwr_req {
  1322. nvidia,pins = "cpu_pwr_req";
  1323. nvidia,function = "cpu";
  1324. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1325. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1326. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1327. };
  1328. pwr_int_n {
  1329. nvidia,pins = "pwr_int_n";
  1330. nvidia,function = "pmi";
  1331. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1332. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1333. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1334. };
  1335. reset_out_n {
  1336. nvidia,pins = "reset_out_n";
  1337. nvidia,function = "reset_out_n";
  1338. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1339. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1340. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1341. };
  1342. clk_32k_in {
  1343. nvidia,pins = "clk_32k_in";
  1344. nvidia,function = "clk";
  1345. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1346. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1347. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1348. };
  1349. jtag_rtck {
  1350. nvidia,pins = "jtag_rtck";
  1351. nvidia,function = "rtck";
  1352. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1353. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1354. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1355. };
  1356. dsi_b {
  1357. nvidia,pins = "mipi_pad_ctrl_dsi_b";
  1358. nvidia,function = "dsi_b";
  1359. };
  1360. };
  1361. };
  1362. /*
  1363. * First high speed UART, exposed on the expansion connector J3A2
  1364. * Pin 41: BR_UART1_TXD
  1365. * Pin 44: BR_UART1_RXD
  1366. */
  1367. serial@70006000 {
  1368. compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
  1369. status = "okay";
  1370. };
  1371. /*
  1372. * Second high speed UART, exposed on the expansion connector J3A2
  1373. * Pin 65: UART2_RXD
  1374. * Pin 68: UART2_TXD
  1375. * Pin 71: UART2_CTS_L
  1376. * Pin 74: UART2_RTS_L
  1377. */
  1378. serial@70006040 {
  1379. compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
  1380. status = "okay";
  1381. };
  1382. /* DB9 serial port */
  1383. serial@70006300 {
  1384. status = "okay";
  1385. };
  1386. /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */
  1387. i2c@7000c000 {
  1388. status = "okay";
  1389. clock-frequency = <100000>;
  1390. rt5639: audio-codec@1c {
  1391. compatible = "realtek,rt5639";
  1392. reg = <0x1c>;
  1393. interrupt-parent = <&gpio>;
  1394. interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
  1395. realtek,ldo1-en-gpios =
  1396. <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
  1397. };
  1398. temperature-sensor@4c {
  1399. compatible = "ti,tmp451";
  1400. reg = <0x4c>;
  1401. interrupt-parent = <&gpio>;
  1402. interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
  1403. };
  1404. eeprom@56 {
  1405. compatible = "atmel,24c02";
  1406. reg = <0x56>;
  1407. pagesize = <8>;
  1408. };
  1409. };
  1410. /* Expansion GEN2_I2C_* */
  1411. i2c@7000c400 {
  1412. status = "okay";
  1413. clock-frequency = <100000>;
  1414. };
  1415. /* Expansion CAM_I2C_* */
  1416. i2c@7000c500 {
  1417. status = "okay";
  1418. clock-frequency = <100000>;
  1419. };
  1420. /* HDMI DDC */
  1421. hdmi_ddc: i2c@7000c700 {
  1422. status = "okay";
  1423. clock-frequency = <100000>;
  1424. };
  1425. /* Expansion PWR_I2C_*, on-board components */
  1426. i2c@7000d000 {
  1427. status = "okay";
  1428. clock-frequency = <400000>;
  1429. pmic: pmic@40 {
  1430. compatible = "ams,as3722";
  1431. reg = <0x40>;
  1432. interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
  1433. ams,system-power-controller;
  1434. #interrupt-cells = <2>;
  1435. interrupt-controller;
  1436. gpio-controller;
  1437. #gpio-cells = <2>;
  1438. pinctrl-names = "default";
  1439. pinctrl-0 = <&as3722_default>;
  1440. as3722_default: pinmux {
  1441. gpio0 {
  1442. pins = "gpio0";
  1443. function = "gpio";
  1444. bias-pull-down;
  1445. };
  1446. gpio1_2_4_7 {
  1447. pins = "gpio1", "gpio2", "gpio4", "gpio7";
  1448. function = "gpio";
  1449. bias-pull-up;
  1450. };
  1451. gpio3_5_6 {
  1452. pins = "gpio3", "gpio5", "gpio6";
  1453. bias-high-impedance;
  1454. };
  1455. };
  1456. regulators {
  1457. vsup-sd2-supply = <&vdd_5v0_sys>;
  1458. vsup-sd3-supply = <&vdd_5v0_sys>;
  1459. vsup-sd4-supply = <&vdd_5v0_sys>;
  1460. vsup-sd5-supply = <&vdd_5v0_sys>;
  1461. vin-ldo0-supply = <&vdd_1v35_lp0>;
  1462. vin-ldo1-6-supply = <&vdd_3v3_run>;
  1463. vin-ldo2-5-7-supply = <&vddio_1v8>;
  1464. vin-ldo3-4-supply = <&vdd_3v3_sys>;
  1465. vin-ldo9-10-supply = <&vdd_5v0_sys>;
  1466. vin-ldo11-supply = <&vdd_3v3_run>;
  1467. vdd_cpu: sd0 {
  1468. regulator-name = "+VDD_CPU_AP";
  1469. regulator-min-microvolt = <700000>;
  1470. regulator-max-microvolt = <1400000>;
  1471. regulator-min-microamp = <3500000>;
  1472. regulator-max-microamp = <3500000>;
  1473. regulator-always-on;
  1474. regulator-boot-on;
  1475. ams,ext-control = <2>;
  1476. };
  1477. sd1 {
  1478. regulator-name = "+VDD_CORE";
  1479. regulator-min-microvolt = <700000>;
  1480. regulator-max-microvolt = <1350000>;
  1481. regulator-min-microamp = <2500000>;
  1482. regulator-max-microamp = <2500000>;
  1483. regulator-always-on;
  1484. regulator-boot-on;
  1485. ams,ext-control = <1>;
  1486. };
  1487. vdd_1v35_lp0: sd2 {
  1488. regulator-name = "+1.35V_LP0(sd2)";
  1489. regulator-min-microvolt = <1350000>;
  1490. regulator-max-microvolt = <1350000>;
  1491. regulator-always-on;
  1492. regulator-boot-on;
  1493. };
  1494. sd3 {
  1495. regulator-name = "+1.35V_LP0(sd3)";
  1496. regulator-min-microvolt = <1350000>;
  1497. regulator-max-microvolt = <1350000>;
  1498. regulator-always-on;
  1499. regulator-boot-on;
  1500. };
  1501. vdd_1v05_run: sd4 {
  1502. regulator-name = "+1.05V_RUN";
  1503. regulator-min-microvolt = <1050000>;
  1504. regulator-max-microvolt = <1050000>;
  1505. };
  1506. vddio_1v8: sd5 {
  1507. regulator-name = "+1.8V_VDDIO";
  1508. regulator-min-microvolt = <1800000>;
  1509. regulator-max-microvolt = <1800000>;
  1510. regulator-boot-on;
  1511. regulator-always-on;
  1512. };
  1513. vdd_gpu: sd6 {
  1514. regulator-name = "+VDD_GPU_AP";
  1515. regulator-min-microvolt = <650000>;
  1516. regulator-max-microvolt = <1200000>;
  1517. regulator-min-microamp = <3500000>;
  1518. regulator-max-microamp = <3500000>;
  1519. regulator-boot-on;
  1520. regulator-always-on;
  1521. };
  1522. avdd_1v05_run: ldo0 {
  1523. regulator-name = "+1.05V_RUN_AVDD";
  1524. regulator-min-microvolt = <1050000>;
  1525. regulator-max-microvolt = <1050000>;
  1526. regulator-boot-on;
  1527. regulator-always-on;
  1528. ams,ext-control = <1>;
  1529. };
  1530. ldo1 {
  1531. regulator-name = "+1.8V_RUN_CAM";
  1532. regulator-min-microvolt = <1800000>;
  1533. regulator-max-microvolt = <1800000>;
  1534. };
  1535. ldo2 {
  1536. regulator-name = "+1.2V_GEN_AVDD";
  1537. regulator-min-microvolt = <1200000>;
  1538. regulator-max-microvolt = <1200000>;
  1539. regulator-boot-on;
  1540. regulator-always-on;
  1541. };
  1542. ldo3 {
  1543. regulator-name = "+1.05V_LP0_VDD_RTC";
  1544. regulator-min-microvolt = <1000000>;
  1545. regulator-max-microvolt = <1000000>;
  1546. regulator-boot-on;
  1547. regulator-always-on;
  1548. ams,enable-tracking;
  1549. };
  1550. ldo4 {
  1551. regulator-name = "+2.8V_RUN_CAM";
  1552. regulator-min-microvolt = <2800000>;
  1553. regulator-max-microvolt = <2800000>;
  1554. };
  1555. ldo5 {
  1556. regulator-name = "+1.2V_RUN_CAM_FRONT";
  1557. regulator-min-microvolt = <1200000>;
  1558. regulator-max-microvolt = <1200000>;
  1559. };
  1560. vddio_sdmmc3: ldo6 {
  1561. regulator-name = "+VDDIO_SDMMC3";
  1562. regulator-min-microvolt = <1800000>;
  1563. regulator-max-microvolt = <3300000>;
  1564. };
  1565. ldo7 {
  1566. regulator-name = "+1.05V_RUN_CAM_REAR";
  1567. regulator-min-microvolt = <1050000>;
  1568. regulator-max-microvolt = <1050000>;
  1569. };
  1570. ldo9 {
  1571. regulator-name = "+3.3V_RUN_TOUCH";
  1572. regulator-min-microvolt = <2800000>;
  1573. regulator-max-microvolt = <2800000>;
  1574. };
  1575. ldo10 {
  1576. regulator-name = "+2.8V_RUN_CAM_AF";
  1577. regulator-min-microvolt = <2800000>;
  1578. regulator-max-microvolt = <2800000>;
  1579. };
  1580. ldo11 {
  1581. regulator-name = "+1.8V_RUN_VPP_FUSE";
  1582. regulator-min-microvolt = <1800000>;
  1583. regulator-max-microvolt = <1800000>;
  1584. };
  1585. };
  1586. };
  1587. };
  1588. /* Expansion TS_SPI_* */
  1589. spi@7000d400 {
  1590. status = "okay";
  1591. };
  1592. /* Internal SPI */
  1593. spi@7000da00 {
  1594. status = "okay";
  1595. spi-max-frequency = <25000000>;
  1596. spi-flash@0 {
  1597. compatible = "winbond,w25q32dw";
  1598. reg = <0>;
  1599. spi-max-frequency = <20000000>;
  1600. };
  1601. };
  1602. pmc@7000e400 {
  1603. nvidia,invert-interrupt;
  1604. nvidia,suspend-mode = <1>;
  1605. nvidia,cpu-pwr-good-time = <500>;
  1606. nvidia,cpu-pwr-off-time = <300>;
  1607. nvidia,core-pwr-good-time = <641 3845>;
  1608. nvidia,core-pwr-off-time = <61036>;
  1609. nvidia,core-power-req-active-high;
  1610. nvidia,sys-clock-req-active-high;
  1611. i2c-thermtrip {
  1612. nvidia,i2c-controller-id = <4>;
  1613. nvidia,bus-addr = <0x40>;
  1614. nvidia,reg-addr = <0x36>;
  1615. nvidia,reg-data = <0x2>;
  1616. };
  1617. };
  1618. /* Serial ATA */
  1619. sata@70020000 {
  1620. status = "okay";
  1621. phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
  1622. phy-names = "sata-0";
  1623. hvdd-supply = <&vdd_3v3_lp0>;
  1624. vddio-supply = <&vdd_1v05_run>;
  1625. avdd-supply = <&vdd_1v05_run>;
  1626. target-5v-supply = <&vdd_5v0_sata>;
  1627. target-12v-supply = <&vdd_12v0_sata>;
  1628. };
  1629. hda@70030000 {
  1630. status = "okay";
  1631. };
  1632. usb@70090000 {
  1633. phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */
  1634. <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */
  1635. <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */
  1636. <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */
  1637. phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
  1638. avddio-pex-supply = <&vdd_1v05_run>;
  1639. dvddio-pex-supply = <&vdd_1v05_run>;
  1640. avdd-usb-supply = <&vdd_3v3_lp0>;
  1641. avdd-pll-utmip-supply = <&vddio_1v8>;
  1642. avdd-pll-erefe-supply = <&avdd_1v05_run>;
  1643. avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
  1644. hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
  1645. hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
  1646. status = "okay";
  1647. };
  1648. padctl@7009f000 {
  1649. status = "okay";
  1650. pads {
  1651. usb2 {
  1652. status = "okay";
  1653. lanes {
  1654. usb2-0 {
  1655. nvidia,function = "xusb";
  1656. status = "okay";
  1657. };
  1658. usb2-1 {
  1659. nvidia,function = "xusb";
  1660. status = "okay";
  1661. };
  1662. usb2-2 {
  1663. nvidia,function = "xusb";
  1664. status = "okay";
  1665. };
  1666. };
  1667. };
  1668. pcie {
  1669. status = "okay";
  1670. lanes {
  1671. pcie-0 {
  1672. nvidia,function = "usb3-ss";
  1673. status = "okay";
  1674. };
  1675. pcie-2 {
  1676. nvidia,function = "pcie";
  1677. status = "okay";
  1678. };
  1679. pcie-4 {
  1680. nvidia,function = "pcie";
  1681. status = "okay";
  1682. };
  1683. };
  1684. };
  1685. sata {
  1686. status = "okay";
  1687. lanes {
  1688. sata-0 {
  1689. nvidia,function = "sata";
  1690. status = "okay";
  1691. };
  1692. };
  1693. };
  1694. };
  1695. ports {
  1696. /* Micro A/B */
  1697. usb2-0 {
  1698. status = "okay";
  1699. mode = "otg";
  1700. };
  1701. /* Mini PCIe */
  1702. usb2-1 {
  1703. status = "okay";
  1704. mode = "host";
  1705. };
  1706. /* USB3 */
  1707. usb2-2 {
  1708. status = "okay";
  1709. mode = "host";
  1710. vbus-supply = <&vdd_usb3_vbus>;
  1711. };
  1712. usb3-0 {
  1713. nvidia,usb2-companion = <2>;
  1714. status = "okay";
  1715. };
  1716. };
  1717. };
  1718. /* SD card */
  1719. sdhci@700b0400 {
  1720. status = "okay";
  1721. cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  1722. power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
  1723. wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
  1724. bus-width = <4>;
  1725. vqmmc-supply = <&vddio_sdmmc3>;
  1726. };
  1727. /* eMMC */
  1728. sdhci@700b0600 {
  1729. status = "okay";
  1730. bus-width = <8>;
  1731. non-removable;
  1732. };
  1733. /* CPU DFLL clock */
  1734. clock@70110000 {
  1735. status = "okay";
  1736. vdd-cpu-supply = <&vdd_cpu>;
  1737. nvidia,i2c-fs-rate = <400000>;
  1738. };
  1739. ahub@70300000 {
  1740. i2s@70301100 {
  1741. status = "okay";
  1742. };
  1743. };
  1744. /* mini-PCIe USB */
  1745. usb@7d004000 {
  1746. status = "okay";
  1747. };
  1748. usb-phy@7d004000 {
  1749. status = "okay";
  1750. };
  1751. /* USB A connector */
  1752. usb@7d008000 {
  1753. status = "okay";
  1754. };
  1755. usb-phy@7d008000 {
  1756. status = "okay";
  1757. vbus-supply = <&vdd_usb3_vbus>;
  1758. };
  1759. clocks {
  1760. compatible = "simple-bus";
  1761. #address-cells = <1>;
  1762. #size-cells = <0>;
  1763. clk32k_in: clock@0 {
  1764. compatible = "fixed-clock";
  1765. reg = <0>;
  1766. #clock-cells = <0>;
  1767. clock-frequency = <32768>;
  1768. };
  1769. };
  1770. cpus {
  1771. cpu@0 {
  1772. vdd-cpu-supply = <&vdd_cpu>;
  1773. };
  1774. };
  1775. gpio-keys {
  1776. compatible = "gpio-keys";
  1777. power {
  1778. label = "Power";
  1779. gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
  1780. linux,code = <KEY_POWER>;
  1781. debounce-interval = <10>;
  1782. wakeup-source;
  1783. };
  1784. };
  1785. regulators {
  1786. compatible = "simple-bus";
  1787. #address-cells = <1>;
  1788. #size-cells = <0>;
  1789. vdd_mux: regulator@0 {
  1790. compatible = "regulator-fixed";
  1791. reg = <0>;
  1792. regulator-name = "+VDD_MUX";
  1793. regulator-min-microvolt = <12000000>;
  1794. regulator-max-microvolt = <12000000>;
  1795. regulator-always-on;
  1796. regulator-boot-on;
  1797. };
  1798. vdd_5v0_sys: regulator@1 {
  1799. compatible = "regulator-fixed";
  1800. reg = <1>;
  1801. regulator-name = "+5V_SYS";
  1802. regulator-min-microvolt = <5000000>;
  1803. regulator-max-microvolt = <5000000>;
  1804. regulator-always-on;
  1805. regulator-boot-on;
  1806. vin-supply = <&vdd_mux>;
  1807. };
  1808. vdd_3v3_sys: regulator@2 {
  1809. compatible = "regulator-fixed";
  1810. reg = <2>;
  1811. regulator-name = "+3.3V_SYS";
  1812. regulator-min-microvolt = <3300000>;
  1813. regulator-max-microvolt = <3300000>;
  1814. regulator-always-on;
  1815. regulator-boot-on;
  1816. vin-supply = <&vdd_mux>;
  1817. };
  1818. vdd_3v3_run: regulator@3 {
  1819. compatible = "regulator-fixed";
  1820. reg = <3>;
  1821. regulator-name = "+3.3V_RUN";
  1822. regulator-min-microvolt = <3300000>;
  1823. regulator-max-microvolt = <3300000>;
  1824. regulator-always-on;
  1825. regulator-boot-on;
  1826. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  1827. enable-active-high;
  1828. vin-supply = <&vdd_3v3_sys>;
  1829. };
  1830. vdd_3v3_hdmi: regulator@4 {
  1831. compatible = "regulator-fixed";
  1832. reg = <4>;
  1833. regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
  1834. regulator-min-microvolt = <3300000>;
  1835. regulator-max-microvolt = <3300000>;
  1836. vin-supply = <&vdd_3v3_run>;
  1837. };
  1838. vdd_usb1_vbus: regulator@7 {
  1839. compatible = "regulator-fixed";
  1840. reg = <7>;
  1841. regulator-name = "+USB0_VBUS_SW";
  1842. regulator-min-microvolt = <5000000>;
  1843. regulator-max-microvolt = <5000000>;
  1844. gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
  1845. enable-active-high;
  1846. gpio-open-drain;
  1847. vin-supply = <&vdd_5v0_sys>;
  1848. };
  1849. vdd_usb3_vbus: regulator@8 {
  1850. compatible = "regulator-fixed";
  1851. reg = <8>;
  1852. regulator-name = "+5V_USB_HS";
  1853. regulator-min-microvolt = <5000000>;
  1854. regulator-max-microvolt = <5000000>;
  1855. gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
  1856. enable-active-high;
  1857. gpio-open-drain;
  1858. vin-supply = <&vdd_5v0_sys>;
  1859. };
  1860. vdd_3v3_lp0: regulator@10 {
  1861. compatible = "regulator-fixed";
  1862. reg = <10>;
  1863. regulator-name = "+3.3V_LP0";
  1864. regulator-min-microvolt = <3300000>;
  1865. regulator-max-microvolt = <3300000>;
  1866. regulator-always-on;
  1867. regulator-boot-on;
  1868. gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
  1869. enable-active-high;
  1870. vin-supply = <&vdd_3v3_sys>;
  1871. };
  1872. vdd_hdmi_pll: regulator@11 {
  1873. compatible = "regulator-fixed";
  1874. reg = <11>;
  1875. regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
  1876. regulator-min-microvolt = <1050000>;
  1877. regulator-max-microvolt = <1050000>;
  1878. gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
  1879. vin-supply = <&vdd_1v05_run>;
  1880. };
  1881. vdd_5v0_hdmi: regulator@12 {
  1882. compatible = "regulator-fixed";
  1883. reg = <12>;
  1884. regulator-name = "+5V_HDMI_CON";
  1885. regulator-min-microvolt = <5000000>;
  1886. regulator-max-microvolt = <5000000>;
  1887. gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  1888. enable-active-high;
  1889. vin-supply = <&vdd_5v0_sys>;
  1890. };
  1891. /* Molex power connector */
  1892. vdd_5v0_sata: regulator@13 {
  1893. compatible = "regulator-fixed";
  1894. reg = <13>;
  1895. regulator-name = "+5V_SATA";
  1896. regulator-min-microvolt = <5000000>;
  1897. regulator-max-microvolt = <5000000>;
  1898. gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
  1899. enable-active-high;
  1900. vin-supply = <&vdd_5v0_sys>;
  1901. };
  1902. vdd_12v0_sata: regulator@14 {
  1903. compatible = "regulator-fixed";
  1904. reg = <14>;
  1905. regulator-name = "+12V_SATA";
  1906. regulator-min-microvolt = <12000000>;
  1907. regulator-max-microvolt = <12000000>;
  1908. gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
  1909. enable-active-high;
  1910. vin-supply = <&vdd_mux>;
  1911. };
  1912. };
  1913. sound {
  1914. compatible = "nvidia,tegra-audio-rt5640-jetson-tk1",
  1915. "nvidia,tegra-audio-rt5640";
  1916. nvidia,model = "NVIDIA Tegra Jetson TK1";
  1917. nvidia,audio-routing =
  1918. "Headphones", "HPOR",
  1919. "Headphones", "HPOL",
  1920. "Mic Jack", "MICBIAS1",
  1921. "IN2P", "Mic Jack";
  1922. nvidia,i2s-controller = <&tegra_i2s1>;
  1923. nvidia,audio-codec = <&rt5639>;
  1924. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>;
  1925. clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
  1926. <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
  1927. <&tegra_car TEGRA124_CLK_EXTERN1>;
  1928. clock-names = "pll_a", "pll_a_out0", "mclk";
  1929. };
  1930. thermal-zones {
  1931. cpu {
  1932. trips {
  1933. cpu-shutdown-trip {
  1934. temperature = <101000>;
  1935. hysteresis = <0>;
  1936. type = "critical";
  1937. };
  1938. };
  1939. };
  1940. mem {
  1941. trips {
  1942. mem-shutdown-trip {
  1943. temperature = <101000>;
  1944. hysteresis = <0>;
  1945. type = "critical";
  1946. };
  1947. };
  1948. };
  1949. gpu {
  1950. trips {
  1951. gpu-shutdown-trip {
  1952. temperature = <101000>;
  1953. hysteresis = <0>;
  1954. type = "critical";
  1955. };
  1956. };
  1957. };
  1958. };
  1959. };