tegra114-roth.dts 30 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra114.dtsi"
  4. / {
  5. model = "NVIDIA SHIELD";
  6. compatible = "nvidia,roth", "nvidia,tegra114";
  7. chosen {
  8. /* SHIELD's bootloader's arguments need to be overridden */
  9. bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1";
  10. /* SHIELD's bootloader will place initrd at this address */
  11. linux,initrd-start = <0x82000000>;
  12. linux,initrd-end = <0x82800000>;
  13. };
  14. aliases {
  15. serial0 = &uartd;
  16. };
  17. firmware {
  18. trusted-foundations {
  19. compatible = "tlm,trusted-foundations";
  20. tlm,version-major = <2>;
  21. tlm,version-minor = <8>;
  22. };
  23. };
  24. memory {
  25. /* memory >= 0x79600000 is reserved for firmware usage */
  26. reg = <0x80000000 0x79600000>;
  27. };
  28. host1x@50000000 {
  29. dsi@54300000 {
  30. status = "okay";
  31. vdd-supply = <&vdd_1v2_ap>;
  32. panel@0 {
  33. compatible = "lg,lh500wx1-sd03";
  34. reg = <0>;
  35. power-supply = <&vdd_lcd>;
  36. backlight = <&backlight>;
  37. };
  38. };
  39. };
  40. pinmux@70000868 {
  41. pinctrl-names = "default";
  42. pinctrl-0 = <&state_default>;
  43. state_default: pinmux {
  44. clk1_out_pw4 {
  45. nvidia,pins = "clk1_out_pw4";
  46. nvidia,function = "extperiph1";
  47. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  48. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  49. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  50. };
  51. dap1_din_pn1 {
  52. nvidia,pins = "dap1_din_pn1";
  53. nvidia,function = "i2s0";
  54. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  55. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  56. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  57. };
  58. dap1_dout_pn2 {
  59. nvidia,pins = "dap1_dout_pn2",
  60. "dap1_fs_pn0",
  61. "dap1_sclk_pn3";
  62. nvidia,function = "i2s0";
  63. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  64. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  65. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  66. };
  67. dap2_din_pa4 {
  68. nvidia,pins = "dap2_din_pa4";
  69. nvidia,function = "i2s1";
  70. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  71. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  72. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  73. };
  74. dap2_dout_pa5 {
  75. nvidia,pins = "dap2_dout_pa5",
  76. "dap2_fs_pa2",
  77. "dap2_sclk_pa3";
  78. nvidia,function = "i2s1";
  79. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  80. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  81. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  82. };
  83. dap4_din_pp5 {
  84. nvidia,pins = "dap4_din_pp5",
  85. "dap4_dout_pp6",
  86. "dap4_fs_pp4",
  87. "dap4_sclk_pp7";
  88. nvidia,function = "i2s3";
  89. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  90. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  91. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  92. };
  93. dvfs_pwm_px0 {
  94. nvidia,pins = "dvfs_pwm_px0",
  95. "dvfs_clk_px2";
  96. nvidia,function = "cldvfs";
  97. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  98. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  99. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  100. };
  101. ulpi_clk_py0 {
  102. nvidia,pins = "ulpi_clk_py0",
  103. "ulpi_data0_po1",
  104. "ulpi_data1_po2",
  105. "ulpi_data2_po3",
  106. "ulpi_data3_po4",
  107. "ulpi_data4_po5",
  108. "ulpi_data5_po6",
  109. "ulpi_data6_po7",
  110. "ulpi_data7_po0";
  111. nvidia,function = "ulpi";
  112. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  113. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  114. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  115. };
  116. ulpi_dir_py1 {
  117. nvidia,pins = "ulpi_dir_py1",
  118. "ulpi_nxt_py2";
  119. nvidia,function = "ulpi";
  120. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  121. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  122. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  123. };
  124. ulpi_stp_py3 {
  125. nvidia,pins = "ulpi_stp_py3";
  126. nvidia,function = "ulpi";
  127. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  128. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  129. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  130. };
  131. cam_i2c_scl_pbb1 {
  132. nvidia,pins = "cam_i2c_scl_pbb1",
  133. "cam_i2c_sda_pbb2";
  134. nvidia,function = "i2c3";
  135. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  136. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  137. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  138. nvidia,lock = <TEGRA_PIN_DISABLE>;
  139. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  140. };
  141. cam_mclk_pcc0 {
  142. nvidia,pins = "cam_mclk_pcc0",
  143. "pbb0";
  144. nvidia,function = "vi_alt3";
  145. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  146. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  147. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  148. nvidia,lock = <TEGRA_PIN_DISABLE>;
  149. };
  150. pbb4 {
  151. nvidia,pins = "pbb4";
  152. nvidia,function = "vgp4";
  153. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  154. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  155. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  156. nvidia,lock = <TEGRA_PIN_DISABLE>;
  157. };
  158. gen2_i2c_scl_pt5 {
  159. nvidia,pins = "gen2_i2c_scl_pt5",
  160. "gen2_i2c_sda_pt6";
  161. nvidia,function = "i2c2";
  162. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  163. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  164. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  165. nvidia,lock = <TEGRA_PIN_DISABLE>;
  166. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  167. };
  168. gmi_a16_pj7 {
  169. nvidia,pins = "gmi_a16_pj7",
  170. "gmi_a19_pk7";
  171. nvidia,function = "uartd";
  172. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  173. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  174. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  175. };
  176. gmi_a17_pb0 {
  177. nvidia,pins = "gmi_a17_pb0",
  178. "gmi_a18_pb1";
  179. nvidia,function = "uartd";
  180. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  181. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  182. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  183. };
  184. gmi_ad5_pg5 {
  185. nvidia,pins = "gmi_ad5_pg5",
  186. "gmi_wr_n_pi0";
  187. nvidia,function = "spi4";
  188. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  189. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  190. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  191. };
  192. gmi_ad6_pg6 {
  193. nvidia,pins = "gmi_ad6_pg6",
  194. "gmi_ad7_pg7";
  195. nvidia,function = "spi4";
  196. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  197. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  198. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  199. };
  200. gmi_ad12_ph4 {
  201. nvidia,pins = "gmi_ad12_ph4";
  202. nvidia,function = "rsvd4";
  203. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  204. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  205. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  206. };
  207. gmi_cs6_n_pi13 {
  208. nvidia,pins = "gmi_cs6_n_pi3";
  209. nvidia,function = "nand";
  210. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  211. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  212. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  213. };
  214. gmi_ad9_ph1 {
  215. nvidia,pins = "gmi_ad9_ph1";
  216. nvidia,function = "pwm1";
  217. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  218. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  219. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  220. };
  221. gmi_cs1_n_pj2 {
  222. nvidia,pins = "gmi_cs1_n_pj2",
  223. "gmi_oe_n_pi1";
  224. nvidia,function = "soc";
  225. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  226. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  227. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  228. };
  229. gmi_rst_n_pi4 {
  230. nvidia,pins = "gmi_rst_n_pi4";
  231. nvidia,function = "gmi";
  232. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  233. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  234. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  235. };
  236. gmi_iordy_pi5 {
  237. nvidia,pins = "gmi_iordy_pi5";
  238. nvidia,function = "gmi";
  239. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  240. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  241. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  242. };
  243. clk2_out_pw5 {
  244. nvidia,pins = "clk2_out_pw5";
  245. nvidia,function = "extperiph2";
  246. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  247. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  248. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  249. };
  250. sdmmc1_clk_pz0 {
  251. nvidia,pins = "sdmmc1_clk_pz0";
  252. nvidia,function = "sdmmc1";
  253. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  254. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  255. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  256. };
  257. sdmmc1_cmd_pz1 {
  258. nvidia,pins = "sdmmc1_cmd_pz1",
  259. "sdmmc1_dat0_py7",
  260. "sdmmc1_dat1_py6",
  261. "sdmmc1_dat2_py5",
  262. "sdmmc1_dat3_py4";
  263. nvidia,function = "sdmmc1";
  264. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  265. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  266. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  267. };
  268. sdmmc3_clk_pa6 {
  269. nvidia,pins = "sdmmc3_clk_pa6";
  270. nvidia,function = "sdmmc3";
  271. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  272. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  273. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  274. };
  275. sdmmc3_cmd_pa7 {
  276. nvidia,pins = "sdmmc3_cmd_pa7",
  277. "sdmmc3_dat0_pb7",
  278. "sdmmc3_dat1_pb6",
  279. "sdmmc3_dat2_pb5",
  280. "sdmmc3_dat3_pb4",
  281. "sdmmc3_cd_n_pv2",
  282. "sdmmc3_clk_lb_out_pee4",
  283. "sdmmc3_clk_lb_in_pee5";
  284. nvidia,function = "sdmmc3";
  285. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  286. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  287. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  288. };
  289. kb_col4_pq4 {
  290. nvidia,pins = "kb_col4_pq4";
  291. nvidia,function = "sdmmc3";
  292. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  293. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  294. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  295. };
  296. sdmmc4_clk_pcc4 {
  297. nvidia,pins = "sdmmc4_clk_pcc4";
  298. nvidia,function = "sdmmc4";
  299. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  300. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  301. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  302. };
  303. sdmmc4_cmd_pt7 {
  304. nvidia,pins = "sdmmc4_cmd_pt7",
  305. "sdmmc4_dat0_paa0",
  306. "sdmmc4_dat1_paa1",
  307. "sdmmc4_dat2_paa2",
  308. "sdmmc4_dat3_paa3",
  309. "sdmmc4_dat4_paa4",
  310. "sdmmc4_dat5_paa5",
  311. "sdmmc4_dat6_paa6",
  312. "sdmmc4_dat7_paa7";
  313. nvidia,function = "sdmmc4";
  314. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  315. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  316. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  317. };
  318. clk_32k_out_pa0 {
  319. nvidia,pins = "clk_32k_out_pa0";
  320. nvidia,function = "blink";
  321. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  322. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  323. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  324. };
  325. kb_col0_pq0 {
  326. nvidia,pins = "kb_col0_pq0",
  327. "kb_col1_pq1",
  328. "kb_col2_pq2",
  329. "kb_row0_pr0",
  330. "kb_row1_pr1",
  331. "kb_row2_pr2",
  332. "kb_row8_ps0";
  333. nvidia,function = "kbc";
  334. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  335. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  336. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  337. };
  338. kb_row7_pr7 {
  339. nvidia,pins = "kb_row7_pr7";
  340. nvidia,function = "rsvd2";
  341. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  342. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  343. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  344. };
  345. kb_row10_ps2 {
  346. nvidia,pins = "kb_row10_ps2";
  347. nvidia,function = "uarta";
  348. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  349. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  350. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  351. };
  352. kb_row9_ps1 {
  353. nvidia,pins = "kb_row9_ps1";
  354. nvidia,function = "uarta";
  355. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  356. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  357. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  358. };
  359. pwr_i2c_scl_pz6 {
  360. nvidia,pins = "pwr_i2c_scl_pz6",
  361. "pwr_i2c_sda_pz7";
  362. nvidia,function = "i2cpwr";
  363. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  364. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  365. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  366. nvidia,lock = <TEGRA_PIN_DISABLE>;
  367. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  368. };
  369. sys_clk_req_pz5 {
  370. nvidia,pins = "sys_clk_req_pz5";
  371. nvidia,function = "sysclk";
  372. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  373. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  374. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  375. };
  376. core_pwr_req {
  377. nvidia,pins = "core_pwr_req";
  378. nvidia,function = "pwron";
  379. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  380. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  381. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  382. };
  383. cpu_pwr_req {
  384. nvidia,pins = "cpu_pwr_req";
  385. nvidia,function = "cpu";
  386. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  387. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  388. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  389. };
  390. pwr_int_n {
  391. nvidia,pins = "pwr_int_n";
  392. nvidia,function = "pmi";
  393. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  394. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  395. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  396. };
  397. reset_out_n {
  398. nvidia,pins = "reset_out_n";
  399. nvidia,function = "reset_out_n";
  400. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  401. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  402. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  403. };
  404. clk3_out_pee0 {
  405. nvidia,pins = "clk3_out_pee0";
  406. nvidia,function = "extperiph3";
  407. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  408. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  409. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  410. };
  411. gen1_i2c_scl_pc4 {
  412. nvidia,pins = "gen1_i2c_scl_pc4",
  413. "gen1_i2c_sda_pc5";
  414. nvidia,function = "i2c1";
  415. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  416. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  417. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  418. nvidia,lock = <TEGRA_PIN_DISABLE>;
  419. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  420. };
  421. uart2_cts_n_pj5 {
  422. nvidia,pins = "uart2_cts_n_pj5";
  423. nvidia,function = "uartb";
  424. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  425. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  426. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  427. };
  428. uart2_rts_n_pj6 {
  429. nvidia,pins = "uart2_rts_n_pj6";
  430. nvidia,function = "uartb";
  431. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  432. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  433. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  434. };
  435. uart2_rxd_pc3 {
  436. nvidia,pins = "uart2_rxd_pc3";
  437. nvidia,function = "irda";
  438. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  439. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  440. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  441. };
  442. uart2_txd_pc2 {
  443. nvidia,pins = "uart2_txd_pc2";
  444. nvidia,function = "irda";
  445. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  446. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  447. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  448. };
  449. uart3_cts_n_pa1 {
  450. nvidia,pins = "uart3_cts_n_pa1",
  451. "uart3_rxd_pw7";
  452. nvidia,function = "uartc";
  453. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  454. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  455. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  456. };
  457. uart3_rts_n_pc0 {
  458. nvidia,pins = "uart3_rts_n_pc0",
  459. "uart3_txd_pw6";
  460. nvidia,function = "uartc";
  461. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  462. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  463. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  464. };
  465. owr {
  466. nvidia,pins = "owr";
  467. nvidia,function = "owr";
  468. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  469. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  470. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  471. };
  472. hdmi_cec_pee3 {
  473. nvidia,pins = "hdmi_cec_pee3";
  474. nvidia,function = "cec";
  475. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  476. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  477. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  478. nvidia,lock = <TEGRA_PIN_DISABLE>;
  479. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  480. };
  481. ddc_scl_pv4 {
  482. nvidia,pins = "ddc_scl_pv4",
  483. "ddc_sda_pv5";
  484. nvidia,function = "i2c4";
  485. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  486. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  487. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  488. nvidia,lock = <TEGRA_PIN_DISABLE>;
  489. nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
  490. };
  491. spdif_in_pk6 {
  492. nvidia,pins = "spdif_in_pk6";
  493. nvidia,function = "usb";
  494. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  495. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  496. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  497. nvidia,lock = <TEGRA_PIN_DISABLE>;
  498. };
  499. usb_vbus_en0_pn4 {
  500. nvidia,pins = "usb_vbus_en0_pn4";
  501. nvidia,function = "usb";
  502. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  503. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  504. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  505. nvidia,lock = <TEGRA_PIN_DISABLE>;
  506. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  507. };
  508. gpio_x6_aud_px6 {
  509. nvidia,pins = "gpio_x6_aud_px6";
  510. nvidia,function = "spi6";
  511. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  512. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  513. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  514. };
  515. gpio_x1_aud_px1 {
  516. nvidia,pins = "gpio_x1_aud_px1";
  517. nvidia,function = "rsvd2";
  518. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  519. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  520. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  521. };
  522. gpio_x7_aud_px7 {
  523. nvidia,pins = "gpio_x7_aud_px7";
  524. nvidia,function = "rsvd1";
  525. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  526. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  527. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  528. };
  529. gmi_adv_n_pk0 {
  530. nvidia,pins = "gmi_adv_n_pk0";
  531. nvidia,function = "gmi";
  532. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  533. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  534. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  535. };
  536. gmi_cs0_n_pj0 {
  537. nvidia,pins = "gmi_cs0_n_pj0";
  538. nvidia,function = "gmi";
  539. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  540. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  541. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  542. };
  543. pu3 {
  544. nvidia,pins = "pu3";
  545. nvidia,function = "pwm0";
  546. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  547. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  548. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  549. };
  550. gpio_x4_aud_px4 {
  551. nvidia,pins = "gpio_x4_aud_px4",
  552. "gpio_x5_aud_px5";
  553. nvidia,function = "rsvd1";
  554. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  555. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  556. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  557. };
  558. gpio_x3_aud_px3 {
  559. nvidia,pins = "gpio_x3_aud_px3";
  560. nvidia,function = "rsvd4";
  561. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  562. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  563. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  564. };
  565. gpio_w2_aud_pw2 {
  566. nvidia,pins = "gpio_w2_aud_pw2";
  567. nvidia,function = "rsvd2";
  568. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  569. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  570. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  571. };
  572. gpio_w3_aud_pw3 {
  573. nvidia,pins = "gpio_w3_aud_pw3";
  574. nvidia,function = "spi6";
  575. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  576. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  577. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  578. };
  579. dap3_fs_pp0 {
  580. nvidia,pins = "dap3_fs_pp0",
  581. "dap3_din_pp1",
  582. "dap3_dout_pp2",
  583. "dap3_sclk_pp3";
  584. nvidia,function = "i2s2";
  585. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  586. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  587. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  588. };
  589. pv0 {
  590. nvidia,pins = "pv0";
  591. nvidia,function = "rsvd4";
  592. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  593. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  594. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  595. };
  596. pv1 {
  597. nvidia,pins = "pv1";
  598. nvidia,function = "rsvd1";
  599. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  600. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  601. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  602. };
  603. pbb3 {
  604. nvidia,pins = "pbb3",
  605. "pbb5",
  606. "pbb6",
  607. "pbb7";
  608. nvidia,function = "rsvd4";
  609. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  610. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  611. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  612. };
  613. pcc1 {
  614. nvidia,pins = "pcc1",
  615. "pcc2";
  616. nvidia,function = "rsvd4";
  617. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  618. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  619. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  620. };
  621. gmi_ad0_pg0 {
  622. nvidia,pins = "gmi_ad0_pg0",
  623. "gmi_ad1_pg1";
  624. nvidia,function = "gmi";
  625. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  626. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  627. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  628. };
  629. gmi_ad10_ph2 {
  630. nvidia,pins = "gmi_ad10_ph2",
  631. "gmi_ad12_ph4",
  632. "gmi_ad15_ph7",
  633. "gmi_cs3_n_pk4";
  634. nvidia,function = "gmi";
  635. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  636. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  637. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  638. };
  639. gmi_ad11_ph3 {
  640. nvidia,pins = "gmi_ad11_ph3",
  641. "gmi_ad13_ph5",
  642. "gmi_ad8_ph0",
  643. "gmi_clk_pk1",
  644. "gmi_cs2_n_pk3";
  645. nvidia,function = "gmi";
  646. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  647. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  648. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  649. };
  650. gmi_ad14_ph6 {
  651. nvidia,pins = "gmi_ad14_ph6",
  652. "gmi_cs0_n_pj0",
  653. "gmi_cs4_n_pk2",
  654. "gmi_cs7_n_pi6",
  655. "gmi_dqs_p_pj3",
  656. "gmi_wp_n_pc7";
  657. nvidia,function = "gmi";
  658. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  659. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  660. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  661. };
  662. gmi_ad2_pg2 {
  663. nvidia,pins = "gmi_ad2_pg2",
  664. "gmi_ad3_pg3";
  665. nvidia,function = "gmi";
  666. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  667. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  668. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  669. };
  670. sdmmc1_wp_n_pv3 {
  671. nvidia,pins = "sdmmc1_wp_n_pv3";
  672. nvidia,function = "spi4";
  673. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  674. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  675. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  676. };
  677. clk2_req_pcc5 {
  678. nvidia,pins = "clk2_req_pcc5";
  679. nvidia,function = "rsvd4";
  680. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  681. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  682. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  683. };
  684. kb_col3_pq3 {
  685. nvidia,pins = "kb_col3_pq3";
  686. nvidia,function = "pwm2";
  687. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  688. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  689. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  690. };
  691. kb_col5_pq5 {
  692. nvidia,pins = "kb_col5_pq5";
  693. nvidia,function = "kbc";
  694. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  695. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  696. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  697. };
  698. kb_col6_pq6 {
  699. nvidia,pins = "kb_col6_pq6",
  700. "kb_col7_pq7";
  701. nvidia,function = "kbc";
  702. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  703. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  704. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  705. };
  706. kb_row3_pr3 {
  707. nvidia,pins = "kb_row3_pr3",
  708. "kb_row4_pr4",
  709. "kb_row6_pr6";
  710. nvidia,function = "kbc";
  711. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  712. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  713. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  714. };
  715. clk3_req_pee1 {
  716. nvidia,pins = "clk3_req_pee1";
  717. nvidia,function = "rsvd4";
  718. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  719. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  720. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  721. };
  722. pu2 {
  723. nvidia,pins = "pu2";
  724. nvidia,function = "rsvd1";
  725. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  726. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  727. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  728. };
  729. hdmi_int_pn7 {
  730. nvidia,pins = "hdmi_int_pn7";
  731. nvidia,function = "rsvd1";
  732. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  733. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  734. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  735. };
  736. drive_sdio1 {
  737. nvidia,pins = "drive_sdio1";
  738. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  739. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  740. nvidia,pull-down-strength = <36>;
  741. nvidia,pull-up-strength = <20>;
  742. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
  743. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
  744. };
  745. drive_sdio3 {
  746. nvidia,pins = "drive_sdio3";
  747. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  748. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  749. nvidia,pull-down-strength = <36>;
  750. nvidia,pull-up-strength = <20>;
  751. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  752. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  753. };
  754. drive_gma {
  755. nvidia,pins = "drive_gma";
  756. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  757. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  758. nvidia,pull-down-strength = <2>;
  759. nvidia,pull-up-strength = <2>;
  760. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  761. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  762. };
  763. };
  764. };
  765. /* Usable on reworked devices only */
  766. serial@70006300 {
  767. status = "okay";
  768. };
  769. pwm@7000a000 {
  770. status = "okay";
  771. };
  772. i2c@7000d000 {
  773. status = "okay";
  774. clock-frequency = <400000>;
  775. regulator@43 {
  776. compatible = "ti,tps51632";
  777. reg = <0x43>;
  778. regulator-name = "vdd-cpu";
  779. regulator-min-microvolt = <500000>;
  780. regulator-max-microvolt = <1520000>;
  781. regulator-always-on;
  782. regulator-boot-on;
  783. };
  784. palmas: pmic@58 {
  785. compatible = "ti,palmas";
  786. reg = <0x58>;
  787. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  788. #interrupt-cells = <2>;
  789. interrupt-controller;
  790. ti,system-power-controller;
  791. palmas_gpio: gpio {
  792. compatible = "ti,palmas-gpio";
  793. gpio-controller;
  794. #gpio-cells = <2>;
  795. };
  796. pmic {
  797. compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
  798. regulators {
  799. smps12 {
  800. regulator-name = "vdd-ddr";
  801. regulator-min-microvolt = <1200000>;
  802. regulator-max-microvolt = <1500000>;
  803. regulator-always-on;
  804. regulator-boot-on;
  805. };
  806. vdd_1v8: smps3 {
  807. regulator-name = "vdd-1v8";
  808. regulator-min-microvolt = <1800000>;
  809. regulator-max-microvolt = <1800000>;
  810. regulator-boot-on;
  811. };
  812. smps457 {
  813. regulator-name = "vdd-soc";
  814. regulator-min-microvolt = <900000>;
  815. regulator-max-microvolt = <1400000>;
  816. regulator-always-on;
  817. regulator-boot-on;
  818. };
  819. smps8 {
  820. regulator-name = "avdd-pll-1v05";
  821. regulator-min-microvolt = <1050000>;
  822. regulator-max-microvolt = <1050000>;
  823. regulator-always-on;
  824. regulator-boot-on;
  825. };
  826. smps9 {
  827. regulator-name = "vdd-2v85-emmc";
  828. regulator-min-microvolt = <2800000>;
  829. regulator-max-microvolt = <2800000>;
  830. regulator-always-on;
  831. };
  832. smps10_out1 {
  833. regulator-name = "vdd-fan";
  834. regulator-min-microvolt = <5000000>;
  835. regulator-max-microvolt = <5000000>;
  836. regulator-always-on;
  837. regulator-boot-on;
  838. };
  839. smps10_out2 {
  840. regulator-name = "vdd-5v0-sys";
  841. regulator-min-microvolt = <5000000>;
  842. regulator-max-microvolt = <5000000>;
  843. regulator-always-on;
  844. regulator-boot-on;
  845. };
  846. ldo2 {
  847. regulator-name = "vdd-2v8-display";
  848. regulator-min-microvolt = <2800000>;
  849. regulator-max-microvolt = <2800000>;
  850. regulator-always-on;
  851. regulator-boot-on;
  852. };
  853. vdd_1v2_ap: ldo3 {
  854. regulator-name = "avdd-1v2";
  855. regulator-min-microvolt = <1200000>;
  856. regulator-max-microvolt = <1200000>;
  857. regulator-always-on;
  858. regulator-boot-on;
  859. };
  860. ldo4 {
  861. regulator-name = "vpp-fuse";
  862. regulator-min-microvolt = <1800000>;
  863. regulator-max-microvolt = <1800000>;
  864. };
  865. ldo5 {
  866. regulator-name = "avdd-hdmi-pll";
  867. regulator-min-microvolt = <1200000>;
  868. regulator-max-microvolt = <1200000>;
  869. };
  870. ldo6 {
  871. regulator-name = "vdd-sensor-2v8";
  872. regulator-min-microvolt = <2850000>;
  873. regulator-max-microvolt = <2850000>;
  874. };
  875. ldo8 {
  876. regulator-name = "vdd-rtc";
  877. regulator-min-microvolt = <1100000>;
  878. regulator-max-microvolt = <1100000>;
  879. regulator-always-on;
  880. regulator-boot-on;
  881. ti,enable-ldo8-tracking;
  882. };
  883. vddio_sdmmc3: ldo9 {
  884. regulator-name = "vddio-sdmmc3";
  885. regulator-min-microvolt = <1800000>;
  886. regulator-max-microvolt = <3300000>;
  887. };
  888. ldousb {
  889. regulator-name = "avdd-usb-hdmi";
  890. regulator-min-microvolt = <3300000>;
  891. regulator-max-microvolt = <3300000>;
  892. regulator-always-on;
  893. regulator-boot-on;
  894. };
  895. vdd_3v3_sys: regen1 {
  896. regulator-name = "rail-3v3";
  897. regulator-max-microvolt = <3300000>;
  898. regulator-always-on;
  899. regulator-boot-on;
  900. };
  901. regen2 {
  902. regulator-name = "rail-5v0";
  903. regulator-max-microvolt = <5000000>;
  904. regulator-always-on;
  905. regulator-boot-on;
  906. };
  907. };
  908. };
  909. rtc {
  910. compatible = "ti,palmas-rtc";
  911. interrupt-parent = <&palmas>;
  912. interrupts = <8 0>;
  913. };
  914. };
  915. };
  916. pmc@7000e400 {
  917. nvidia,invert-interrupt;
  918. };
  919. /* SD card */
  920. sdhci@78000400 {
  921. status = "okay";
  922. bus-width = <4>;
  923. vqmmc-supply = <&vddio_sdmmc3>;
  924. cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  925. power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
  926. };
  927. /* eMMC */
  928. sdhci@78000600 {
  929. status = "okay";
  930. bus-width = <8>;
  931. non-removable;
  932. };
  933. /* External USB port (must be powered) */
  934. usb@7d000000 {
  935. status = "okay";
  936. };
  937. usb-phy@7d000000 {
  938. status = "okay";
  939. nvidia,xcvr-setup = <7>;
  940. nvidia,xcvr-lsfslew = <2>;
  941. nvidia,xcvr-lsrslew = <2>;
  942. interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  943. /* Should be changed to "otg" once we have vbus_supply */
  944. /* As of now, USB devices need to be powered externally */
  945. dr_mode = "host";
  946. };
  947. /* SHIELD controller */
  948. usb@7d008000 {
  949. status = "okay";
  950. };
  951. usb-phy@7d008000 {
  952. status = "okay";
  953. nvidia,xcvr-setup = <7>;
  954. nvidia,xcvr-lsfslew = <2>;
  955. nvidia,xcvr-lsrslew = <2>;
  956. };
  957. backlight: backlight {
  958. compatible = "pwm-backlight";
  959. pwms = <&pwm 1 40000>;
  960. brightness-levels = <0 4 8 16 32 64 128 255>;
  961. default-brightness-level = <6>;
  962. power-supply = <&lcd_bl_en>;
  963. enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  964. };
  965. clocks {
  966. compatible = "simple-bus";
  967. #address-cells = <1>;
  968. #size-cells = <0>;
  969. clk32k_in: clock@0 {
  970. compatible = "fixed-clock";
  971. reg = <0>;
  972. #clock-cells = <0>;
  973. clock-frequency = <32768>;
  974. };
  975. };
  976. gpio-keys {
  977. compatible = "gpio-keys";
  978. back {
  979. label = "Back";
  980. gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
  981. linux,code = <KEY_BACK>;
  982. };
  983. home {
  984. label = "Home";
  985. gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
  986. linux,code = <KEY_HOME>;
  987. };
  988. power {
  989. label = "Power";
  990. gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
  991. linux,code = <KEY_POWER>;
  992. wakeup-source;
  993. };
  994. };
  995. regulators {
  996. compatible = "simple-bus";
  997. #address-cells = <1>;
  998. #size-cells = <0>;
  999. lcd_bl_en: regulator@0 {
  1000. compatible = "regulator-fixed";
  1001. reg = <0>;
  1002. regulator-name = "lcd_bl_en";
  1003. regulator-min-microvolt = <5000000>;
  1004. regulator-max-microvolt = <5000000>;
  1005. regulator-boot-on;
  1006. };
  1007. vdd_lcd: regulator@1 {
  1008. compatible = "regulator-fixed";
  1009. reg = <1>;
  1010. regulator-name = "vdd_lcd_1v8";
  1011. regulator-min-microvolt = <1800000>;
  1012. regulator-max-microvolt = <1800000>;
  1013. vin-supply = <&vdd_1v8>;
  1014. enable-active-high;
  1015. gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
  1016. regulator-boot-on;
  1017. };
  1018. regulator@2 {
  1019. compatible = "regulator-fixed";
  1020. reg = <2>;
  1021. regulator-name = "vdd_1v8_ts";
  1022. regulator-min-microvolt = <1800000>;
  1023. regulator-max-microvolt = <1800000>;
  1024. gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>;
  1025. regulator-boot-on;
  1026. };
  1027. regulator@3 {
  1028. compatible = "regulator-fixed";
  1029. reg = <3>;
  1030. regulator-name = "vdd_3v3_ts";
  1031. regulator-min-microvolt = <3300000>;
  1032. regulator-max-microvolt = <3300000>;
  1033. enable-active-high;
  1034. gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
  1035. regulator-boot-on;
  1036. };
  1037. regulator@4 {
  1038. compatible = "regulator-fixed";
  1039. reg = <4>;
  1040. regulator-name = "vdd_1v8_com";
  1041. regulator-min-microvolt = <1800000>;
  1042. regulator-max-microvolt = <1800000>;
  1043. vin-supply = <&vdd_1v8>;
  1044. enable-active-high;
  1045. gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
  1046. regulator-boot-on;
  1047. };
  1048. regulator@5 {
  1049. compatible = "regulator-fixed";
  1050. reg = <5>;
  1051. regulator-name = "vdd_3v3_com";
  1052. regulator-min-microvolt = <3300000>;
  1053. regulator-max-microvolt = <3300000>;
  1054. vin-supply = <&vdd_3v3_sys>;
  1055. enable-active-high;
  1056. gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
  1057. regulator-always-on;
  1058. regulator-boot-on;
  1059. };
  1060. };
  1061. };