sun8i-a83t.dtsi 6.0 KB

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  1. /*
  2. * Copyright 2015 Vishnu Patekar
  3. *
  4. * Vishnu Patekar <vishnupatekar0510@gmail.com>
  5. *
  6. * This file is dual-licensed: you can use it either under the terms
  7. * of the GPL or the X11 license, at your option. Note that this dual
  8. * licensing only applies to this file, and not this project as a
  9. * whole.
  10. *
  11. * a) This file is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of the
  14. * License, or (at your option) any later version.
  15. *
  16. * This file is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * Or, alternatively,
  22. *
  23. * b) Permission is hereby granted, free of charge, to any person
  24. * obtaining a copy of this software and associated documentation
  25. * files (the "Software"), to deal in the Software without
  26. * restriction, including without limitation the rights to use,
  27. * copy, modify, merge, publish, distribute, sublicense, and/or
  28. * sell copies of the Software, and to permit persons to whom the
  29. * Software is furnished to do so, subject to the following
  30. * conditions:
  31. *
  32. * The above copyright notice and this permission notice shall be
  33. * included in all copies or substantial portions of the Software.
  34. *
  35. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42. * OTHER DEALINGS IN THE SOFTWARE.
  43. */
  44. #include "skeleton.dtsi"
  45. #include <dt-bindings/interrupt-controller/arm-gic.h>
  46. #include <dt-bindings/pinctrl/sun4i-a10.h>
  47. / {
  48. interrupt-parent = <&gic>;
  49. cpus {
  50. #address-cells = <1>;
  51. #size-cells = <0>;
  52. cpu@0 {
  53. compatible = "arm,cortex-a7";
  54. device_type = "cpu";
  55. reg = <0>;
  56. };
  57. cpu@1 {
  58. compatible = "arm,cortex-a7";
  59. device_type = "cpu";
  60. reg = <1>;
  61. };
  62. cpu@2 {
  63. compatible = "arm,cortex-a7";
  64. device_type = "cpu";
  65. reg = <2>;
  66. };
  67. cpu@3 {
  68. compatible = "arm,cortex-a7";
  69. device_type = "cpu";
  70. reg = <3>;
  71. };
  72. cpu@100 {
  73. compatible = "arm,cortex-a7";
  74. device_type = "cpu";
  75. reg = <0x100>;
  76. };
  77. cpu@101 {
  78. compatible = "arm,cortex-a7";
  79. device_type = "cpu";
  80. reg = <0x101>;
  81. };
  82. cpu@102 {
  83. compatible = "arm,cortex-a7";
  84. device_type = "cpu";
  85. reg = <0x102>;
  86. };
  87. cpu@103 {
  88. compatible = "arm,cortex-a7";
  89. device_type = "cpu";
  90. reg = <0x103>;
  91. };
  92. };
  93. timer {
  94. compatible = "arm,armv7-timer";
  95. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
  96. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
  97. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
  98. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
  99. };
  100. clocks {
  101. #address-cells = <1>;
  102. #size-cells = <1>;
  103. ranges;
  104. /* TODO: PRCM block has a mux for this. */
  105. osc24M: osc24M_clk {
  106. #clock-cells = <0>;
  107. compatible = "fixed-clock";
  108. clock-frequency = <24000000>;
  109. clock-output-names = "osc24M";
  110. };
  111. /*
  112. * This is called "internal OSC" in some places.
  113. * It is an internal RC-based oscillator.
  114. * TODO: Its controls are in the PRCM block.
  115. */
  116. osc16M: osc16M_clk {
  117. #clock-cells = <0>;
  118. compatible = "fixed-clock";
  119. clock-frequency = <16000000>;
  120. clock-output-names = "osc16M";
  121. };
  122. osc16Md512: osc16Md512_clk {
  123. #clock-cells = <0>;
  124. compatible = "fixed-factor-clock";
  125. clock-div = <512>;
  126. clock-mult = <1>;
  127. clocks = <&osc16M>;
  128. clock-output-names = "osc16M-d512";
  129. };
  130. };
  131. soc {
  132. compatible = "simple-bus";
  133. #address-cells = <1>;
  134. #size-cells = <1>;
  135. ranges;
  136. pio: pinctrl@01c20800 {
  137. compatible = "allwinner,sun8i-a83t-pinctrl";
  138. interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
  139. <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
  140. <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
  141. reg = <0x01c20800 0x400>;
  142. clocks = <&osc24M>;
  143. gpio-controller;
  144. interrupt-controller;
  145. #interrupt-cells = <3>;
  146. #gpio-cells = <3>;
  147. mmc0_pins_a: mmc0@0 {
  148. allwinner,pins = "PF0", "PF1", "PF2",
  149. "PF3", "PF4", "PF5";
  150. allwinner,function = "mmc0";
  151. allwinner,drive = <SUN4I_PINCTRL_30_MA>;
  152. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  153. };
  154. uart0_pins_a: uart0@0 {
  155. allwinner,pins = "PF2", "PF4";
  156. allwinner,function = "uart0";
  157. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  158. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  159. };
  160. uart0_pins_b: uart0@1 {
  161. allwinner,pins = "PB9", "PB10";
  162. allwinner,function = "uart0";
  163. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  164. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  165. };
  166. };
  167. timer@01c20c00 {
  168. compatible = "allwinner,sun4i-a10-timer";
  169. reg = <0x01c20c00 0xa0>;
  170. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  171. <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  172. clocks = <&osc24M>;
  173. };
  174. watchdog@01c20ca0 {
  175. compatible = "allwinner,sun6i-a31-wdt";
  176. reg = <0x01c20ca0 0x20>;
  177. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  178. clocks = <&osc24M>;
  179. };
  180. uart0: serial@01c28000 {
  181. compatible = "snps,dw-apb-uart";
  182. reg = <0x01c28000 0x400>;
  183. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  184. reg-shift = <2>;
  185. reg-io-width = <4>;
  186. clocks = <&osc24M>;
  187. status = "disabled";
  188. };
  189. gic: interrupt-controller@01c81000 {
  190. compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
  191. reg = <0x01c81000 0x1000>,
  192. <0x01c82000 0x1000>,
  193. <0x01c84000 0x2000>,
  194. <0x01c86000 0x2000>;
  195. interrupt-controller;
  196. #interrupt-cells = <3>;
  197. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  198. };
  199. };
  200. };