samsung_k3pe0e000b.dtsi 1.4 KB

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  1. /*
  2. * Timings and Geometry for Samsung K3PE0E000B memory part
  3. */
  4. / {
  5. samsung_K3PE0E000B: lpddr2 {
  6. compatible = "Samsung,K3PE0E000B","jedec,lpddr2-s4";
  7. density = <4096>;
  8. io-width = <32>;
  9. tRPab-min-tck = <3>;
  10. tRCD-min-tck = <3>;
  11. tWR-min-tck = <3>;
  12. tRASmin-min-tck = <3>;
  13. tRRD-min-tck = <2>;
  14. tWTR-min-tck = <2>;
  15. tXP-min-tck = <2>;
  16. tRTP-min-tck = <2>;
  17. tCKE-min-tck = <3>;
  18. tCKESR-min-tck = <3>;
  19. tFAW-min-tck = <8>;
  20. timings_samsung_K3PE0E000B_533MHz: lpddr2-timings@0 {
  21. compatible = "jedec,lpddr2-timings";
  22. min-freq = <10000000>;
  23. max-freq = <533333333>;
  24. tRPab = <21000>;
  25. tRCD = <18000>;
  26. tWR = <15000>;
  27. tRAS-min = <42000>;
  28. tRRD = <10000>;
  29. tWTR = <7500>;
  30. tXP = <7500>;
  31. tRTP = <7500>;
  32. tCKESR = <15000>;
  33. tDQSCK-max = <5500>;
  34. tFAW = <50000>;
  35. tZQCS = <90000>;
  36. tZQCL = <360000>;
  37. tZQinit = <1000000>;
  38. tRAS-max-ns = <70000>;
  39. tDQSCK-max-derated = <6000>;
  40. };
  41. timings_samsung_K3PE0E000B_266MHz: lpddr2-timings@1 {
  42. compatible = "jedec,lpddr2-timings";
  43. min-freq = <10000000>;
  44. max-freq = <266666666>;
  45. tRPab = <21000>;
  46. tRCD = <18000>;
  47. tWR = <15000>;
  48. tRAS-min = <42000>;
  49. tRRD = <10000>;
  50. tWTR = <7500>;
  51. tXP = <7500>;
  52. tRTP = <7500>;
  53. tCKESR = <15000>;
  54. tDQSCK-max = <5500>;
  55. tFAW = <50000>;
  56. tZQCS = <90000>;
  57. tZQCL = <360000>;
  58. tZQinit = <1000000>;
  59. tRAS-max-ns = <70000>;
  60. tDQSCK-max-derated = <6000>;
  61. };
  62. };
  63. };