omap3-overo-base.dtsi 7.7 KB

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  1. /*
  2. * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /*
  9. * The Gumstix Overo must be combined with an expansion board.
  10. */
  11. / {
  12. memory@0 {
  13. device_type = "memory";
  14. reg = <0 0>;
  15. };
  16. pwmleds {
  17. compatible = "pwm-leds";
  18. overo {
  19. label = "overo:blue:COM";
  20. pwms = <&twl_pwmled 1 7812500>;
  21. max-brightness = <127>;
  22. linux,default-trigger = "mmc0";
  23. };
  24. };
  25. sound {
  26. compatible = "ti,omap-twl4030";
  27. ti,model = "overo";
  28. ti,mcbsp = <&mcbsp2>;
  29. };
  30. /* HS USB Port 2 Power */
  31. hsusb2_power: hsusb2_power_reg {
  32. compatible = "regulator-fixed";
  33. regulator-name = "hsusb2_vbus";
  34. regulator-min-microvolt = <5000000>;
  35. regulator-max-microvolt = <5000000>;
  36. gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>; /* gpio_168: vbus enable */
  37. startup-delay-us = <70000>;
  38. enable-active-high;
  39. };
  40. /* HS USB Host PHY on PORT 2 */
  41. hsusb2_phy: hsusb2_phy {
  42. compatible = "usb-nop-xceiv";
  43. reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */
  44. vcc-supply = <&hsusb2_power>;
  45. };
  46. /* Regulator to trigger the nPoweron signal of the Wifi module */
  47. w3cbw003c_npoweron: regulator-w3cbw003c-npoweron {
  48. compatible = "regulator-fixed";
  49. regulator-name = "regulator-w3cbw003c-npoweron";
  50. regulator-min-microvolt = <3300000>;
  51. regulator-max-microvolt = <3300000>;
  52. gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54: nPoweron */
  53. enable-active-high;
  54. };
  55. /* Regulator to trigger the nReset signal of the Wifi module */
  56. w3cbw003c_wifi_nreset: regulator-w3cbw003c-wifi-nreset {
  57. pinctrl-names = "default";
  58. pinctrl-0 = <&w3cbw003c_pins &w3cbw003c_2_pins>;
  59. compatible = "regulator-fixed";
  60. regulator-name = "regulator-w3cbw003c-wifi-nreset";
  61. regulator-min-microvolt = <3300000>;
  62. regulator-max-microvolt = <3300000>;
  63. gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* gpio_16: WiFi nReset */
  64. startup-delay-us = <10000>;
  65. };
  66. /* Regulator to trigger the nReset signal of the Bluetooth module */
  67. w3cbw003c_bt_nreset: regulator-w3cbw003c-bt-nreset {
  68. compatible = "regulator-fixed";
  69. regulator-name = "regulator-w3cbw003c-bt-nreset";
  70. regulator-min-microvolt = <3300000>;
  71. regulator-max-microvolt = <3300000>;
  72. gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164: BT nReset */
  73. startup-delay-us = <10000>;
  74. };
  75. };
  76. &omap3_pmx_core {
  77. pinctrl-names = "default";
  78. pinctrl-0 = <
  79. &hsusb2_pins
  80. >;
  81. uart2_pins: pinmux_uart2_pins {
  82. pinctrl-single,pins = <
  83. OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */
  84. OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */
  85. OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */
  86. OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
  87. >;
  88. };
  89. i2c1_pins: pinmux_i2c1_pins {
  90. pinctrl-single,pins = <
  91. OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
  92. OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
  93. >;
  94. };
  95. mmc1_pins: pinmux_mmc1_pins {
  96. pinctrl-single,pins = <
  97. OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
  98. OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
  99. OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
  100. OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
  101. OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
  102. OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
  103. >;
  104. };
  105. mmc2_pins: pinmux_mmc2_pins {
  106. pinctrl-single,pins = <
  107. OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
  108. OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
  109. OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
  110. OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
  111. OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
  112. OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
  113. >;
  114. };
  115. /* WiFi/BT combo */
  116. w3cbw003c_pins: pinmux_w3cbw003c_pins {
  117. pinctrl-single,pins = <
  118. OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
  119. OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
  120. >;
  121. };
  122. hsusb2_pins: pinmux_hsusb2_pins {
  123. pinctrl-single,pins = <
  124. OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
  125. OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
  126. OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
  127. OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
  128. OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
  129. OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
  130. OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */
  131. OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4) /* i2c2_sda.gpio_183 */
  132. >;
  133. };
  134. };
  135. &i2c1 {
  136. pinctrl-names = "default";
  137. pinctrl-0 = <&i2c1_pins>;
  138. clock-frequency = <2600000>;
  139. twl: twl@48 {
  140. reg = <0x48>;
  141. interrupts = <7>; /* SYS_NIRQ cascaded to intc */
  142. interrupt-parent = <&intc>;
  143. twl_audio: audio {
  144. compatible = "ti,twl4030-audio";
  145. codec {
  146. };
  147. };
  148. };
  149. };
  150. #include "twl4030.dtsi"
  151. #include "twl4030_omap3.dtsi"
  152. /* i2c2 pins are used for gpio */
  153. &i2c2 {
  154. status = "disabled";
  155. };
  156. /* on board microSD slot */
  157. &mmc1 {
  158. pinctrl-names = "default";
  159. pinctrl-0 = <&mmc1_pins>;
  160. vmmc-supply = <&vmmc1>;
  161. bus-width = <4>;
  162. };
  163. /* optional on board WiFi */
  164. &mmc2 {
  165. pinctrl-names = "default";
  166. pinctrl-0 = <&mmc2_pins>;
  167. vmmc-supply = <&w3cbw003c_npoweron>;
  168. vqmmc-supply = <&w3cbw003c_bt_nreset>;
  169. vmmc_aux-supply = <&w3cbw003c_wifi_nreset>;
  170. bus-width = <4>;
  171. cap-sdio-irq;
  172. non-removable;
  173. };
  174. &twl_gpio {
  175. ti,use-leds;
  176. };
  177. &usb_otg_hs {
  178. interface-type = <0>;
  179. usb-phy = <&usb2_phy>;
  180. phys = <&usb2_phy>;
  181. phy-names = "usb2-phy";
  182. mode = <3>;
  183. power = <50>;
  184. };
  185. &usbhshost {
  186. port2-mode = "ehci-phy";
  187. };
  188. &usbhsehci {
  189. phys = <0 &hsusb2_phy>;
  190. };
  191. &uart2 {
  192. pinctrl-names = "default";
  193. pinctrl-0 = <&uart2_pins>;
  194. };
  195. &mcbsp2 {
  196. status = "okay";
  197. };
  198. &gpmc {
  199. ranges = <0 0 0x30000000 0x1000000>, /* CS0 */
  200. <4 0 0x2b000000 0x1000000>, /* CS4 */
  201. <5 0 0x2c000000 0x1000000>; /* CS5 */
  202. nand@0,0 {
  203. compatible = "ti,omap2-nand";
  204. linux,mtd-name= "micron,mt29c4g96maz";
  205. reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  206. interrupt-parent = <&gpmc>;
  207. interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  208. <1 IRQ_TYPE_NONE>; /* termcount */
  209. nand-bus-width = <16>;
  210. gpmc,device-width = <2>;
  211. ti,nand-ecc-opt = "bch8";
  212. gpmc,sync-clk-ps = <0>;
  213. gpmc,cs-on-ns = <0>;
  214. gpmc,cs-rd-off-ns = <44>;
  215. gpmc,cs-wr-off-ns = <44>;
  216. gpmc,adv-on-ns = <6>;
  217. gpmc,adv-rd-off-ns = <34>;
  218. gpmc,adv-wr-off-ns = <44>;
  219. gpmc,we-off-ns = <40>;
  220. gpmc,oe-off-ns = <54>;
  221. gpmc,access-ns = <64>;
  222. gpmc,rd-cycle-ns = <82>;
  223. gpmc,wr-cycle-ns = <82>;
  224. gpmc,wr-access-ns = <40>;
  225. gpmc,wr-data-mux-bus-ns = <0>;
  226. #address-cells = <1>;
  227. #size-cells = <1>;
  228. partition@0 {
  229. label = "SPL";
  230. reg = <0 0x80000>; /* 512KiB */
  231. };
  232. partition@80000 {
  233. label = "U-Boot";
  234. reg = <0x80000 0x1C0000>; /* 1792KiB */
  235. };
  236. partition@1c0000 {
  237. label = "Environment";
  238. reg = <0x240000 0x40000>; /* 256KiB */
  239. };
  240. partition@280000 {
  241. label = "Kernel";
  242. reg = <0x280000 0x800000>; /* 8192KiB */
  243. };
  244. partition@780000 {
  245. label = "Filesystem";
  246. reg = <0xA80000 0>;
  247. /* HACK: MTDPART_SIZ_FULL=0 so fill to end */
  248. };
  249. };
  250. };