keystone-k2g.dtsi 3.3 KB

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  1. /*
  2. * Device Tree Source for K2G SOC
  3. *
  4. * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <dt-bindings/interrupt-controller/arm-gic.h>
  16. #include <dt-bindings/pinctrl/keystone.h>
  17. #include "skeleton.dtsi"
  18. / {
  19. compatible = "ti,k2g","ti,keystone";
  20. model = "Texas Instruments K2G SoC";
  21. #address-cells = <2>;
  22. #size-cells = <2>;
  23. interrupt-parent = <&gic>;
  24. aliases {
  25. serial0 = &uart0;
  26. };
  27. cpus {
  28. #address-cells = <1>;
  29. #size-cells = <0>;
  30. cpu@0 {
  31. compatible = "arm,cortex-a15";
  32. device_type = "cpu";
  33. reg = <0>;
  34. };
  35. };
  36. gic: interrupt-controller@02561000 {
  37. compatible = "arm,cortex-a15-gic";
  38. #interrupt-cells = <3>;
  39. interrupt-controller;
  40. reg = <0x0 0x02561000 0x0 0x1000>,
  41. <0x0 0x02562000 0x0 0x2000>,
  42. <0x0 0x02564000 0x0 0x1000>,
  43. <0x0 0x02566000 0x0 0x2000>;
  44. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
  45. IRQ_TYPE_LEVEL_HIGH)>;
  46. };
  47. timer {
  48. compatible = "arm,armv7-timer";
  49. interrupts =
  50. <GIC_PPI 13
  51. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  52. <GIC_PPI 14
  53. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  54. <GIC_PPI 11
  55. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  56. <GIC_PPI 10
  57. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  58. };
  59. pmu {
  60. compatible = "arm,cortex-a15-pmu";
  61. interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
  62. };
  63. soc {
  64. #address-cells = <1>;
  65. #size-cells = <1>;
  66. compatible = "ti,keystone","simple-bus";
  67. ranges = <0x0 0x0 0x0 0xc0000000>;
  68. dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
  69. k2g_pinctrl: pinmux@02621000 {
  70. compatible = "pinctrl-single";
  71. reg = <0x02621000 0x410>;
  72. pinctrl-single,register-width = <32>;
  73. pinctrl-single,function-mask = <0x001b0007>;
  74. };
  75. devctrl: device-state-control@02620000 {
  76. compatible = "ti,keystone-devctrl", "syscon";
  77. reg = <0x02620000 0x1000>;
  78. };
  79. uart0: serial@02530c00 {
  80. compatible = "ns16550a";
  81. current-speed = <115200>;
  82. reg-shift = <2>;
  83. reg-io-width = <4>;
  84. reg = <0x02530c00 0x100>;
  85. interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
  86. clock-frequency = <200000000>;
  87. status = "disabled";
  88. };
  89. kirq0: keystone_irq@026202a0 {
  90. compatible = "ti,keystone-irq";
  91. interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>;
  92. interrupt-controller;
  93. #interrupt-cells = <1>;
  94. ti,syscon-dev = <&devctrl 0x2a0>;
  95. };
  96. dspgpio0: keystone_dsp_gpio@02620240 {
  97. compatible = "ti,keystone-dsp-gpio";
  98. gpio-controller;
  99. #gpio-cells = <2>;
  100. gpio,syscon-dev = <&devctrl 0x240>;
  101. };
  102. msgmgr: msgmgr@02a00000 {
  103. compatible = "ti,k2g-message-manager";
  104. #mbox-cells = <2>;
  105. reg-names = "queue_proxy_region",
  106. "queue_state_debug_region";
  107. reg = <0x02a00000 0x400000>, <0x028c3400 0x400>;
  108. interrupt-names = "rx_005",
  109. "rx_057";
  110. interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
  111. <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
  112. };
  113. };
  114. };