imx6sx-sdb.dtsi 15 KB

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  1. /*
  2. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /dts-v1/;
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/input/input.h>
  11. #include "imx6sx.dtsi"
  12. / {
  13. model = "Freescale i.MX6 SoloX SDB Board";
  14. compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
  15. chosen {
  16. stdout-path = &uart1;
  17. };
  18. memory {
  19. reg = <0x80000000 0x40000000>;
  20. };
  21. backlight {
  22. compatible = "pwm-backlight";
  23. pwms = <&pwm3 0 5000000>;
  24. brightness-levels = <0 4 8 16 32 64 128 255>;
  25. default-brightness-level = <6>;
  26. };
  27. gpio-keys {
  28. compatible = "gpio-keys";
  29. pinctrl-names = "default";
  30. pinctrl-0 = <&pinctrl_gpio_keys>;
  31. volume-up {
  32. label = "Volume Up";
  33. gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
  34. linux,code = <KEY_VOLUMEUP>;
  35. };
  36. volume-down {
  37. label = "Volume Down";
  38. gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  39. linux,code = <KEY_VOLUMEDOWN>;
  40. };
  41. };
  42. regulators {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <0>;
  46. vcc_sd3: regulator@0 {
  47. compatible = "regulator-fixed";
  48. reg = <0>;
  49. pinctrl-names = "default";
  50. pinctrl-0 = <&pinctrl_vcc_sd3>;
  51. regulator-name = "VCC_SD3";
  52. regulator-min-microvolt = <3000000>;
  53. regulator-max-microvolt = <3000000>;
  54. gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
  55. enable-active-high;
  56. };
  57. reg_usb_otg1_vbus: regulator@1 {
  58. compatible = "regulator-fixed";
  59. reg = <1>;
  60. pinctrl-names = "default";
  61. pinctrl-0 = <&pinctrl_usb_otg1>;
  62. regulator-name = "usb_otg1_vbus";
  63. regulator-min-microvolt = <5000000>;
  64. regulator-max-microvolt = <5000000>;
  65. gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  66. enable-active-high;
  67. };
  68. reg_usb_otg2_vbus: regulator@2 {
  69. compatible = "regulator-fixed";
  70. reg = <2>;
  71. pinctrl-names = "default";
  72. pinctrl-0 = <&pinctrl_usb_otg2>;
  73. regulator-name = "usb_otg2_vbus";
  74. regulator-min-microvolt = <5000000>;
  75. regulator-max-microvolt = <5000000>;
  76. gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  77. enable-active-high;
  78. };
  79. reg_psu_5v: regulator@3 {
  80. compatible = "regulator-fixed";
  81. reg = <3>;
  82. regulator-name = "PSU-5V0";
  83. regulator-min-microvolt = <5000000>;
  84. regulator-max-microvolt = <5000000>;
  85. };
  86. reg_lcd_3v3: regulator@4 {
  87. compatible = "regulator-fixed";
  88. reg = <4>;
  89. regulator-name = "lcd-3v3";
  90. gpio = <&gpio3 27 0>;
  91. enable-active-high;
  92. };
  93. reg_peri_3v3: regulator@5 {
  94. compatible = "regulator-fixed";
  95. reg = <5>;
  96. pinctrl-names = "default";
  97. pinctrl-0 = <&pinctrl_peri_3v3>;
  98. regulator-name = "peri_3v3";
  99. regulator-min-microvolt = <3300000>;
  100. regulator-max-microvolt = <3300000>;
  101. gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
  102. enable-active-high;
  103. regulator-always-on;
  104. };
  105. reg_enet_3v3: regulator@6 {
  106. compatible = "regulator-fixed";
  107. reg = <6>;
  108. pinctrl-names = "default";
  109. pinctrl-0 = <&pinctrl_enet_3v3>;
  110. regulator-name = "enet_3v3";
  111. regulator-min-microvolt = <3300000>;
  112. regulator-max-microvolt = <3300000>;
  113. gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
  114. };
  115. };
  116. sound {
  117. compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
  118. model = "wm8962-audio";
  119. ssi-controller = <&ssi2>;
  120. audio-codec = <&codec>;
  121. audio-routing =
  122. "Headphone Jack", "HPOUTL",
  123. "Headphone Jack", "HPOUTR",
  124. "Ext Spk", "SPKOUTL",
  125. "Ext Spk", "SPKOUTR",
  126. "AMIC", "MICBIAS",
  127. "IN3R", "AMIC";
  128. mux-int-port = <2>;
  129. mux-ext-port = <6>;
  130. };
  131. };
  132. &audmux {
  133. pinctrl-names = "default";
  134. pinctrl-0 = <&pinctrl_audmux>;
  135. status = "okay";
  136. };
  137. &fec1 {
  138. pinctrl-names = "default";
  139. pinctrl-0 = <&pinctrl_enet1>;
  140. phy-supply = <&reg_enet_3v3>;
  141. phy-mode = "rgmii";
  142. phy-handle = <&ethphy1>;
  143. status = "okay";
  144. mdio {
  145. #address-cells = <1>;
  146. #size-cells = <0>;
  147. ethphy1: ethernet-phy@1 {
  148. reg = <1>;
  149. };
  150. ethphy2: ethernet-phy@2 {
  151. reg = <2>;
  152. };
  153. };
  154. };
  155. &fec2 {
  156. pinctrl-names = "default";
  157. pinctrl-0 = <&pinctrl_enet2>;
  158. phy-mode = "rgmii";
  159. phy-handle = <&ethphy2>;
  160. status = "okay";
  161. };
  162. &i2c3 {
  163. clock-frequency = <100000>;
  164. pinctrl-names = "default";
  165. pinctrl-0 = <&pinctrl_i2c3>;
  166. status = "okay";
  167. };
  168. &i2c4 {
  169. clock-frequency = <100000>;
  170. pinctrl-names = "default";
  171. pinctrl-0 = <&pinctrl_i2c4>;
  172. status = "okay";
  173. codec: wm8962@1a {
  174. compatible = "wlf,wm8962";
  175. reg = <0x1a>;
  176. clocks = <&clks IMX6SX_CLK_AUDIO>;
  177. DCVDD-supply = <&vgen4_reg>;
  178. DBVDD-supply = <&vgen4_reg>;
  179. AVDD-supply = <&vgen4_reg>;
  180. CPVDD-supply = <&vgen4_reg>;
  181. MICVDD-supply = <&vgen3_reg>;
  182. PLLVDD-supply = <&vgen4_reg>;
  183. SPKVDD1-supply = <&reg_psu_5v>;
  184. SPKVDD2-supply = <&reg_psu_5v>;
  185. };
  186. };
  187. &lcdif1 {
  188. pinctrl-names = "default";
  189. pinctrl-0 = <&pinctrl_lcd>;
  190. lcd-supply = <&reg_lcd_3v3>;
  191. display = <&display0>;
  192. status = "okay";
  193. display0: display0 {
  194. bits-per-pixel = <16>;
  195. bus-width = <24>;
  196. display-timings {
  197. native-mode = <&timing0>;
  198. timing0: timing0 {
  199. clock-frequency = <33500000>;
  200. hactive = <800>;
  201. vactive = <480>;
  202. hback-porch = <89>;
  203. hfront-porch = <164>;
  204. vback-porch = <23>;
  205. vfront-porch = <10>;
  206. hsync-len = <10>;
  207. vsync-len = <10>;
  208. hsync-active = <0>;
  209. vsync-active = <0>;
  210. de-active = <1>;
  211. pixelclk-active = <0>;
  212. };
  213. };
  214. };
  215. };
  216. &pwm3 {
  217. pinctrl-names = "default";
  218. pinctrl-0 = <&pinctrl_pwm3>;
  219. status = "okay";
  220. };
  221. &snvs_poweroff {
  222. status = "okay";
  223. };
  224. &sai1 {
  225. pinctrl-names = "default";
  226. pinctrl-0 = <&pinctrl_sai1>;
  227. status = "disabled";
  228. };
  229. &ssi2 {
  230. status = "okay";
  231. };
  232. &uart1 {
  233. pinctrl-names = "default";
  234. pinctrl-0 = <&pinctrl_uart1>;
  235. status = "okay";
  236. };
  237. &uart5 { /* for bluetooth */
  238. pinctrl-names = "default";
  239. pinctrl-0 = <&pinctrl_uart5>;
  240. uart-has-rtscts;
  241. status = "okay";
  242. };
  243. &usbotg1 {
  244. vbus-supply = <&reg_usb_otg1_vbus>;
  245. pinctrl-names = "default";
  246. pinctrl-0 = <&pinctrl_usb_otg1_id>;
  247. status = "okay";
  248. };
  249. &usbotg2 {
  250. vbus-supply = <&reg_usb_otg2_vbus>;
  251. dr_mode = "host";
  252. status = "okay";
  253. };
  254. &usdhc2 {
  255. pinctrl-names = "default";
  256. pinctrl-0 = <&pinctrl_usdhc2>;
  257. non-removable;
  258. no-1-8-v;
  259. keep-power-in-suspend;
  260. wakeup-source;
  261. status = "okay";
  262. };
  263. &usdhc3 {
  264. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  265. pinctrl-0 = <&pinctrl_usdhc3>;
  266. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  267. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  268. bus-width = <8>;
  269. cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
  270. wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
  271. keep-power-in-suspend;
  272. wakeup-source;
  273. vmmc-supply = <&vcc_sd3>;
  274. status = "okay";
  275. };
  276. &usdhc4 {
  277. pinctrl-names = "default";
  278. pinctrl-0 = <&pinctrl_usdhc4>;
  279. cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
  280. wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
  281. status = "okay";
  282. };
  283. &wdog1 {
  284. pinctrl-names = "default";
  285. pinctrl-0 = <&pinctrl_wdog>;
  286. fsl,ext-reset-output;
  287. };
  288. &iomuxc {
  289. imx6x-sdb {
  290. pinctrl_audmux: audmuxgrp {
  291. fsl,pins = <
  292. MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
  293. MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
  294. MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
  295. MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
  296. MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
  297. >;
  298. };
  299. pinctrl_enet1: enet1grp {
  300. fsl,pins = <
  301. MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
  302. MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
  303. MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
  304. MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
  305. MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
  306. MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
  307. MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
  308. MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
  309. MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
  310. MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
  311. MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
  312. MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
  313. MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
  314. MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
  315. MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
  316. >;
  317. };
  318. pinctrl_enet_3v3: enet3v3grp {
  319. fsl,pins = <
  320. MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
  321. >;
  322. };
  323. pinctrl_enet2: enet2grp {
  324. fsl,pins = <
  325. MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
  326. MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
  327. MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
  328. MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
  329. MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
  330. MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
  331. MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
  332. MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
  333. MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
  334. MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
  335. MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
  336. MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
  337. >;
  338. };
  339. pinctrl_gpio_keys: gpio_keysgrp {
  340. fsl,pins = <
  341. MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
  342. MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
  343. >;
  344. };
  345. pinctrl_i2c1: i2c1grp {
  346. fsl,pins = <
  347. MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
  348. MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
  349. >;
  350. };
  351. pinctrl_i2c3: i2c3grp {
  352. fsl,pins = <
  353. MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
  354. MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
  355. >;
  356. };
  357. pinctrl_i2c4: i2c4grp {
  358. fsl,pins = <
  359. MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
  360. MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
  361. >;
  362. };
  363. pinctrl_lcd: lcdgrp {
  364. fsl,pins = <
  365. MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
  366. MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
  367. MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
  368. MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
  369. MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
  370. MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
  371. MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
  372. MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
  373. MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
  374. MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
  375. MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
  376. MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
  377. MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
  378. MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
  379. MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
  380. MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
  381. MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
  382. MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
  383. MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
  384. MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
  385. MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
  386. MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
  387. MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
  388. MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
  389. MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
  390. MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
  391. MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
  392. MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
  393. MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
  394. >;
  395. };
  396. pinctrl_peri_3v3: peri3v3grp {
  397. fsl,pins = <
  398. MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
  399. >;
  400. };
  401. pinctrl_pwm3: pwm3grp-1 {
  402. fsl,pins = <
  403. MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
  404. >;
  405. };
  406. pinctrl_qspi2: qspi2grp {
  407. fsl,pins = <
  408. MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
  409. MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
  410. MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
  411. MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
  412. MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
  413. MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
  414. MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
  415. MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
  416. MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
  417. MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
  418. MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
  419. MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
  420. >;
  421. };
  422. pinctrl_vcc_sd3: vccsd3grp {
  423. fsl,pins = <
  424. MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
  425. >;
  426. };
  427. pinctrl_sai1: sai1grp {
  428. fsl,pins = <
  429. MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0
  430. MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0
  431. MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0
  432. MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0
  433. MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
  434. >;
  435. };
  436. pinctrl_uart1: uart1grp {
  437. fsl,pins = <
  438. MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
  439. MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
  440. >;
  441. };
  442. pinctrl_uart5: uart5grp {
  443. fsl,pins = <
  444. MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
  445. MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
  446. MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
  447. MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
  448. >;
  449. };
  450. pinctrl_usb_otg1: usbotg1grp {
  451. fsl,pins = <
  452. MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
  453. >;
  454. };
  455. pinctrl_usb_otg1_id: usbotg1idgrp {
  456. fsl,pins = <
  457. MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
  458. >;
  459. };
  460. pinctrl_usb_otg2: usbot2ggrp {
  461. fsl,pins = <
  462. MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
  463. >;
  464. };
  465. pinctrl_usdhc2: usdhc2grp {
  466. fsl,pins = <
  467. MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
  468. MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
  469. MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
  470. MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
  471. MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
  472. MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
  473. >;
  474. };
  475. pinctrl_usdhc3: usdhc3grp {
  476. fsl,pins = <
  477. MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
  478. MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
  479. MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
  480. MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
  481. MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
  482. MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
  483. MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
  484. MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
  485. MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
  486. MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
  487. MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
  488. MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
  489. >;
  490. };
  491. pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
  492. fsl,pins = <
  493. MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
  494. MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
  495. MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
  496. MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
  497. MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
  498. MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
  499. MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
  500. MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
  501. MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
  502. MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
  503. >;
  504. };
  505. pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
  506. fsl,pins = <
  507. MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
  508. MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
  509. MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
  510. MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
  511. MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
  512. MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
  513. MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
  514. MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
  515. MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
  516. MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
  517. >;
  518. };
  519. pinctrl_usdhc4: usdhc4grp {
  520. fsl,pins = <
  521. MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
  522. MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
  523. MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
  524. MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
  525. MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
  526. MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
  527. MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
  528. MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
  529. >;
  530. };
  531. pinctrl_wdog: wdoggrp {
  532. fsl,pins = <
  533. MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
  534. >;
  535. };
  536. };
  537. };