imx53-mba53.dts 5.5 KB

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  1. /*
  2. * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
  3. * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. /dts-v1/;
  13. #include "imx53-tqma53.dtsi"
  14. / {
  15. model = "TQ MBa53 starter kit";
  16. compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
  17. chosen {
  18. stdout-path = &uart2;
  19. };
  20. backlight {
  21. compatible = "pwm-backlight";
  22. pwms = <&pwm2 0 50000>;
  23. brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
  24. default-brightness-level = <10>;
  25. enable-gpios = <&gpio7 7 0>;
  26. power-supply = <&reg_backlight>;
  27. };
  28. disp1: display@disp1 {
  29. compatible = "fsl,imx-parallel-display";
  30. pinctrl-names = "default";
  31. pinctrl-0 = <&pinctrl_disp1_1>;
  32. interface-pix-fmt = "rgb24";
  33. status = "disabled";
  34. port {
  35. display1_in: endpoint {
  36. remote-endpoint = <&ipu_di1_disp1>;
  37. };
  38. };
  39. };
  40. regulators {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <0>;
  44. reg_backlight: regulator@0 {
  45. compatible = "regulator-fixed";
  46. reg = <0>;
  47. regulator-name = "lcd-supply";
  48. gpio = <&gpio2 5 0>;
  49. startup-delay-us = <5000>;
  50. };
  51. reg_3p2v: regulator@1 {
  52. compatible = "regulator-fixed";
  53. reg = <1>;
  54. regulator-name = "3P2V";
  55. regulator-min-microvolt = <3200000>;
  56. regulator-max-microvolt = <3200000>;
  57. regulator-always-on;
  58. };
  59. };
  60. sound {
  61. compatible = "tq,imx53-mba53-sgtl5000",
  62. "fsl,imx-audio-sgtl5000";
  63. model = "imx53-mba53-sgtl5000";
  64. ssi-controller = <&ssi2>;
  65. audio-codec = <&codec>;
  66. audio-routing =
  67. "MIC_IN", "Mic Jack",
  68. "Mic Jack", "Mic Bias",
  69. "Headphone Jack", "HP_OUT";
  70. mux-int-port = <2>;
  71. mux-ext-port = <5>;
  72. };
  73. };
  74. &ldb {
  75. pinctrl-names = "default";
  76. pinctrl-0 = <&pinctrl_lvds1_1>;
  77. status = "disabled";
  78. };
  79. &iomuxc {
  80. lvds1 {
  81. pinctrl_lvds1_1: lvds1-grp1 {
  82. fsl,pins = <
  83. MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
  84. MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
  85. MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
  86. MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
  87. MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
  88. >;
  89. };
  90. pinctrl_lvds1_2: lvds1-grp2 {
  91. fsl,pins = <
  92. MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
  93. MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
  94. MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
  95. MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
  96. MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
  97. >;
  98. };
  99. };
  100. disp1 {
  101. pinctrl_disp1_1: disp1-grp1 {
  102. fsl,pins = <
  103. MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
  104. MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */
  105. MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */
  106. MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */
  107. MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
  108. MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
  109. MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
  110. MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
  111. MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
  112. MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
  113. MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
  114. MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
  115. MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
  116. MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
  117. MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
  118. MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
  119. MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
  120. MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
  121. MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000
  122. MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000
  123. MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000
  124. MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000
  125. MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000
  126. MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000
  127. MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000
  128. MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000
  129. MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000
  130. MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000
  131. >;
  132. };
  133. };
  134. tve {
  135. pinctrl_vga_sync_1: vgasync-grp1 {
  136. fsl,pins = <
  137. /* VGA_VSYNC, HSYNC with max drive strength */
  138. MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6
  139. MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6
  140. >;
  141. };
  142. };
  143. };
  144. &ipu_di1_disp1 {
  145. remote-endpoint = <&display1_in>;
  146. };
  147. &cspi {
  148. status = "okay";
  149. };
  150. &audmux {
  151. status = "okay";
  152. pinctrl-names = "default";
  153. pinctrl-0 = <&pinctrl_audmux>;
  154. };
  155. &i2c2 {
  156. codec: sgtl5000@a {
  157. compatible = "fsl,sgtl5000";
  158. reg = <0x0a>;
  159. clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
  160. VDDA-supply = <&reg_3p2v>;
  161. VDDIO-supply = <&reg_3p2v>;
  162. };
  163. expander: pca9554@20 {
  164. compatible = "pca9554";
  165. reg = <0x20>;
  166. interrupts = <109>;
  167. #gpio-cells = <2>;
  168. gpio-controller;
  169. };
  170. sensor2: lm75@49 {
  171. compatible = "lm75";
  172. reg = <0x49>;
  173. };
  174. };
  175. &fec {
  176. phy-reset-gpios = <&gpio7 6 0>;
  177. status = "okay";
  178. };
  179. &esdhc2 {
  180. status = "okay";
  181. };
  182. &uart3 {
  183. status = "okay";
  184. };
  185. &ecspi1 {
  186. status = "okay";
  187. };
  188. &usbotg {
  189. dr_mode = "host";
  190. status = "okay";
  191. };
  192. &usbh1 {
  193. status = "okay";
  194. };
  195. &uart1 {
  196. status = "okay";
  197. };
  198. &ssi2 {
  199. status = "okay";
  200. };
  201. &uart2 {
  202. status = "okay";
  203. };
  204. &can1 {
  205. status = "okay";
  206. };
  207. &can2 {
  208. status = "okay";
  209. };
  210. &i2c3 {
  211. status = "okay";
  212. };
  213. &tve {
  214. pinctrl-names = "default";
  215. pinctrl-0 = <&pinctrl_vga_sync_1>;
  216. ddc-i2c-bus = <&i2c3>;
  217. fsl,tve-mode = "vga";
  218. fsl,hsync-pin = <4>;
  219. fsl,vsync-pin = <6>;
  220. status = "okay";
  221. };