hisi-x5hd2.dtsi 13 KB

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  1. /*
  2. * Copyright (c) 2013-2014 Linaro Ltd.
  3. * Copyright (c) 2013-2014 Hisilicon Limited.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * publishhed by the Free Software Foundation.
  8. */
  9. #include "skeleton.dtsi"
  10. #include <dt-bindings/clock/hix5hd2-clock.h>
  11. / {
  12. aliases {
  13. serial0 = &uart0;
  14. };
  15. gic: interrupt-controller@f8a01000 {
  16. compatible = "arm,cortex-a9-gic";
  17. #interrupt-cells = <3>;
  18. #address-cells = <0>;
  19. interrupt-controller;
  20. /* gic dist base, gic cpu base */
  21. reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
  22. };
  23. soc {
  24. #address-cells = <1>;
  25. #size-cells = <1>;
  26. compatible = "simple-bus";
  27. interrupt-parent = <&gic>;
  28. ranges = <0 0xf8000000 0x8000000>;
  29. amba {
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. compatible = "simple-bus";
  33. ranges;
  34. timer0: timer@00002000 {
  35. compatible = "arm,sp804", "arm,primecell";
  36. reg = <0x00002000 0x1000>;
  37. /* timer00 & timer01 */
  38. interrupts = <0 24 4>;
  39. clocks = <&clock HIX5HD2_FIXED_24M>;
  40. status = "disabled";
  41. };
  42. timer1: timer@00a29000 {
  43. /*
  44. * Only used in NORMAL state, not available ins
  45. * SLOW or DOZE state.
  46. * The rate is fixed in 24MHz.
  47. */
  48. compatible = "arm,sp804", "arm,primecell";
  49. reg = <0x00a29000 0x1000>;
  50. /* timer10 & timer11 */
  51. interrupts = <0 25 4>;
  52. clocks = <&clock HIX5HD2_FIXED_24M>;
  53. status = "disabled";
  54. };
  55. timer2: timer@00a2a000 {
  56. compatible = "arm,sp804", "arm,primecell";
  57. reg = <0x00a2a000 0x1000>;
  58. /* timer20 & timer21 */
  59. interrupts = <0 26 4>;
  60. clocks = <&clock HIX5HD2_FIXED_24M>;
  61. status = "disabled";
  62. };
  63. timer3: timer@00a2b000 {
  64. compatible = "arm,sp804", "arm,primecell";
  65. reg = <0x00a2b000 0x1000>;
  66. /* timer30 & timer31 */
  67. interrupts = <0 27 4>;
  68. clocks = <&clock HIX5HD2_FIXED_24M>;
  69. status = "disabled";
  70. };
  71. timer4: timer@00a81000 {
  72. compatible = "arm,sp804", "arm,primecell";
  73. reg = <0x00a81000 0x1000>;
  74. /* timer30 & timer31 */
  75. interrupts = <0 28 4>;
  76. clocks = <&clock HIX5HD2_FIXED_24M>;
  77. status = "disabled";
  78. };
  79. uart0: uart@00b00000 {
  80. compatible = "arm,pl011", "arm,primecell";
  81. reg = <0x00b00000 0x1000>;
  82. interrupts = <0 49 4>;
  83. clocks = <&clock HIX5HD2_FIXED_83M>;
  84. clock-names = "apb_pclk";
  85. status = "disabled";
  86. };
  87. uart1: uart@00006000 {
  88. compatible = "arm,pl011", "arm,primecell";
  89. reg = <0x00006000 0x1000>;
  90. interrupts = <0 50 4>;
  91. clocks = <&clock HIX5HD2_FIXED_83M>;
  92. clock-names = "apb_pclk";
  93. status = "disabled";
  94. };
  95. uart2: uart@00b02000 {
  96. compatible = "arm,pl011", "arm,primecell";
  97. reg = <0x00b02000 0x1000>;
  98. interrupts = <0 51 4>;
  99. clocks = <&clock HIX5HD2_FIXED_83M>;
  100. clock-names = "apb_pclk";
  101. status = "disabled";
  102. };
  103. uart3: uart@00b03000 {
  104. compatible = "arm,pl011", "arm,primecell";
  105. reg = <0x00b03000 0x1000>;
  106. interrupts = <0 52 4>;
  107. clocks = <&clock HIX5HD2_FIXED_83M>;
  108. clock-names = "apb_pclk";
  109. status = "disabled";
  110. };
  111. uart4: uart@00b04000 {
  112. compatible = "arm,pl011", "arm,primecell";
  113. reg = <0xb04000 0x1000>;
  114. interrupts = <0 53 4>;
  115. clocks = <&clock HIX5HD2_FIXED_83M>;
  116. clock-names = "apb_pclk";
  117. status = "disabled";
  118. };
  119. gpio0: gpio@b20000 {
  120. compatible = "arm,pl061", "arm,primecell";
  121. reg = <0xb20000 0x1000>;
  122. interrupts = <0 108 0x4>;
  123. gpio-controller;
  124. #gpio-cells = <2>;
  125. clocks = <&clock HIX5HD2_FIXED_100M>;
  126. clock-names = "apb_pclk";
  127. interrupt-controller;
  128. #interrupt-cells = <2>;
  129. status = "disabled";
  130. };
  131. gpio1: gpio@b21000 {
  132. compatible = "arm,pl061", "arm,primecell";
  133. reg = <0xb21000 0x1000>;
  134. interrupts = <0 109 0x4>;
  135. gpio-controller;
  136. #gpio-cells = <2>;
  137. clocks = <&clock HIX5HD2_FIXED_100M>;
  138. clock-names = "apb_pclk";
  139. interrupt-controller;
  140. #interrupt-cells = <2>;
  141. status = "disabled";
  142. };
  143. gpio2: gpio@b22000 {
  144. compatible = "arm,pl061", "arm,primecell";
  145. reg = <0xb22000 0x1000>;
  146. interrupts = <0 110 0x4>;
  147. gpio-controller;
  148. #gpio-cells = <2>;
  149. clocks = <&clock HIX5HD2_FIXED_100M>;
  150. clock-names = "apb_pclk";
  151. interrupt-controller;
  152. #interrupt-cells = <2>;
  153. status = "disabled";
  154. };
  155. gpio3: gpio@b23000 {
  156. compatible = "arm,pl061", "arm,primecell";
  157. reg = <0xb23000 0x1000>;
  158. interrupts = <0 111 0x4>;
  159. gpio-controller;
  160. #gpio-cells = <2>;
  161. clocks = <&clock HIX5HD2_FIXED_100M>;
  162. clock-names = "apb_pclk";
  163. interrupt-controller;
  164. #interrupt-cells = <2>;
  165. status = "disabled";
  166. };
  167. gpio4: gpio@b24000 {
  168. compatible = "arm,pl061", "arm,primecell";
  169. reg = <0xb24000 0x1000>;
  170. interrupts = <0 112 0x4>;
  171. gpio-controller;
  172. #gpio-cells = <2>;
  173. clocks = <&clock HIX5HD2_FIXED_100M>;
  174. clock-names = "apb_pclk";
  175. interrupt-controller;
  176. #interrupt-cells = <2>;
  177. status = "disabled";
  178. };
  179. gpio5: gpio@004000 {
  180. compatible = "arm,pl061", "arm,primecell";
  181. reg = <0x004000 0x1000>;
  182. interrupts = <0 113 0x4>;
  183. gpio-controller;
  184. #gpio-cells = <2>;
  185. clocks = <&clock HIX5HD2_FIXED_100M>;
  186. clock-names = "apb_pclk";
  187. interrupt-controller;
  188. #interrupt-cells = <2>;
  189. status = "disabled";
  190. };
  191. gpio6: gpio@b26000 {
  192. compatible = "arm,pl061", "arm,primecell";
  193. reg = <0xb26000 0x1000>;
  194. interrupts = <0 114 0x4>;
  195. gpio-controller;
  196. #gpio-cells = <2>;
  197. clocks = <&clock HIX5HD2_FIXED_100M>;
  198. clock-names = "apb_pclk";
  199. interrupt-controller;
  200. #interrupt-cells = <2>;
  201. status = "disabled";
  202. };
  203. gpio7: gpio@b27000 {
  204. compatible = "arm,pl061", "arm,primecell";
  205. reg = <0xb27000 0x1000>;
  206. interrupts = <0 115 0x4>;
  207. gpio-controller;
  208. #gpio-cells = <2>;
  209. clocks = <&clock HIX5HD2_FIXED_100M>;
  210. clock-names = "apb_pclk";
  211. interrupt-controller;
  212. #interrupt-cells = <2>;
  213. status = "disabled";
  214. };
  215. gpio8: gpio@b28000 {
  216. compatible = "arm,pl061", "arm,primecell";
  217. reg = <0xb28000 0x1000>;
  218. interrupts = <0 116 0x4>;
  219. gpio-controller;
  220. #gpio-cells = <2>;
  221. clocks = <&clock HIX5HD2_FIXED_100M>;
  222. clock-names = "apb_pclk";
  223. interrupt-controller;
  224. #interrupt-cells = <2>;
  225. status = "disabled";
  226. };
  227. gpio9: gpio@b29000 {
  228. compatible = "arm,pl061", "arm,primecell";
  229. reg = <0xb29000 0x1000>;
  230. interrupts = <0 117 0x4>;
  231. gpio-controller;
  232. #gpio-cells = <2>;
  233. clocks = <&clock HIX5HD2_FIXED_100M>;
  234. clock-names = "apb_pclk";
  235. interrupt-controller;
  236. #interrupt-cells = <2>;
  237. status = "disabled";
  238. };
  239. gpio10: gpio@b2a000 {
  240. compatible = "arm,pl061", "arm,primecell";
  241. reg = <0xb2a000 0x1000>;
  242. interrupts = <0 118 0x4>;
  243. gpio-controller;
  244. #gpio-cells = <2>;
  245. clocks = <&clock HIX5HD2_FIXED_100M>;
  246. clock-names = "apb_pclk";
  247. interrupt-controller;
  248. #interrupt-cells = <2>;
  249. status = "disabled";
  250. };
  251. gpio11: gpio@b2b000 {
  252. compatible = "arm,pl061", "arm,primecell";
  253. reg = <0xb2b000 0x1000>;
  254. interrupts = <0 119 0x4>;
  255. gpio-controller;
  256. #gpio-cells = <2>;
  257. clocks = <&clock HIX5HD2_FIXED_100M>;
  258. clock-names = "apb_pclk";
  259. interrupt-controller;
  260. #interrupt-cells = <2>;
  261. status = "disabled";
  262. };
  263. gpio12: gpio@b2c000 {
  264. compatible = "arm,pl061", "arm,primecell";
  265. reg = <0xb2c000 0x1000>;
  266. interrupts = <0 120 0x4>;
  267. gpio-controller;
  268. #gpio-cells = <2>;
  269. clocks = <&clock HIX5HD2_FIXED_100M>;
  270. clock-names = "apb_pclk";
  271. interrupt-controller;
  272. #interrupt-cells = <2>;
  273. status = "disabled";
  274. };
  275. gpio13: gpio@b2d000 {
  276. compatible = "arm,pl061", "arm,primecell";
  277. reg = <0xb2d000 0x1000>;
  278. interrupts = <0 121 0x4>;
  279. gpio-controller;
  280. #gpio-cells = <2>;
  281. clocks = <&clock HIX5HD2_FIXED_100M>;
  282. clock-names = "apb_pclk";
  283. interrupt-controller;
  284. #interrupt-cells = <2>;
  285. status = "disabled";
  286. };
  287. gpio14: gpio@b2e000 {
  288. compatible = "arm,pl061", "arm,primecell";
  289. reg = <0xb2e000 0x1000>;
  290. interrupts = <0 122 0x4>;
  291. gpio-controller;
  292. #gpio-cells = <2>;
  293. clocks = <&clock HIX5HD2_FIXED_100M>;
  294. clock-names = "apb_pclk";
  295. interrupt-controller;
  296. #interrupt-cells = <2>;
  297. status = "disabled";
  298. };
  299. gpio15: gpio@b2f000 {
  300. compatible = "arm,pl061", "arm,primecell";
  301. reg = <0xb2f000 0x1000>;
  302. interrupts = <0 123 0x4>;
  303. gpio-controller;
  304. #gpio-cells = <2>;
  305. clocks = <&clock HIX5HD2_FIXED_100M>;
  306. clock-names = "apb_pclk";
  307. interrupt-controller;
  308. #interrupt-cells = <2>;
  309. status = "disabled";
  310. };
  311. gpio16: gpio@b30000 {
  312. compatible = "arm,pl061", "arm,primecell";
  313. reg = <0xb30000 0x1000>;
  314. interrupts = <0 124 0x4>;
  315. gpio-controller;
  316. #gpio-cells = <2>;
  317. clocks = <&clock HIX5HD2_FIXED_100M>;
  318. clock-names = "apb_pclk";
  319. interrupt-controller;
  320. #interrupt-cells = <2>;
  321. status = "disabled";
  322. };
  323. gpio17: gpio@b31000 {
  324. compatible = "arm,pl061", "arm,primecell";
  325. reg = <0xb31000 0x1000>;
  326. interrupts = <0 125 0x4>;
  327. gpio-controller;
  328. #gpio-cells = <2>;
  329. clocks = <&clock HIX5HD2_FIXED_100M>;
  330. clock-names = "apb_pclk";
  331. interrupt-controller;
  332. #interrupt-cells = <2>;
  333. status = "disabled";
  334. };
  335. wdt0: watchdog@a2c000 {
  336. compatible = "arm,sp805", "arm,primecell";
  337. arm,primecell-periphid = <0x00141805>;
  338. reg = <0xa2c000 0x1000>;
  339. interrupts = <0 29 4>;
  340. clocks = <&clock HIX5HD2_WDG0_RST>;
  341. clock-names = "apb_pclk";
  342. };
  343. };
  344. local_timer@00a00600 {
  345. compatible = "arm,cortex-a9-twd-timer";
  346. reg = <0x00a00600 0x20>;
  347. interrupts = <1 13 0xf01>;
  348. };
  349. l2: l2-cache {
  350. compatible = "arm,pl310-cache";
  351. reg = <0x00a10000 0x100000>;
  352. interrupts = <0 15 4>;
  353. cache-unified;
  354. cache-level = <2>;
  355. };
  356. sysctrl: system-controller@00000000 {
  357. compatible = "hisilicon,sysctrl", "syscon";
  358. reg = <0x00000000 0x1000>;
  359. };
  360. reboot {
  361. compatible = "syscon-reboot";
  362. regmap = <&sysctrl>;
  363. offset = <0x4>;
  364. mask = <0xdeadbeef>;
  365. };
  366. cpuctrl@00a22000 {
  367. compatible = "hisilicon,cpuctrl";
  368. #address-cells = <1>;
  369. #size-cells = <1>;
  370. reg = <0x00a22000 0x2000>;
  371. ranges = <0 0x00a22000 0x2000>;
  372. clock: clock@0 {
  373. compatible = "hisilicon,hix5hd2-clock";
  374. reg = <0 0x2000>;
  375. #clock-cells = <1>;
  376. };
  377. };
  378. /* unremovable emmc as mmcblk0 */
  379. mmc: mmc@1830000 {
  380. compatible = "snps,dw-mshc";
  381. reg = <0x1830000 0x1000>;
  382. interrupts = <0 35 4>;
  383. clocks = <&clock HIX5HD2_MMC_CIU_RST>,
  384. <&clock HIX5HD2_MMC_BIU_CLK>;
  385. clock-names = "ciu", "biu";
  386. };
  387. sd: mmc@1820000 {
  388. compatible = "snps,dw-mshc";
  389. reg = <0x1820000 0x1000>;
  390. interrupts = <0 34 4>;
  391. clocks = <&clock HIX5HD2_SD_CIU_RST>,
  392. <&clock HIX5HD2_SD_BIU_CLK>;
  393. clock-names = "ciu","biu";
  394. };
  395. gmac0: ethernet@1840000 {
  396. compatible = "hisilicon,hix5hd2-gmac";
  397. reg = <0x1840000 0x1000>,<0x184300c 0x4>;
  398. interrupts = <0 71 4>;
  399. clocks = <&clock HIX5HD2_MAC0_CLK>;
  400. status = "disabled";
  401. };
  402. gmac1: ethernet@1841000 {
  403. compatible = "hisilicon,hix5hd2-gmac";
  404. reg = <0x1841000 0x1000>,<0x1843010 0x4>;
  405. interrupts = <0 72 4>;
  406. clocks = <&clock HIX5HD2_MAC1_CLK>;
  407. status = "disabled";
  408. };
  409. usb0: ehci@1890000 {
  410. compatible = "generic-ehci";
  411. reg = <0x1890000 0x1000>;
  412. interrupts = <0 66 4>;
  413. clocks = <&clock HIX5HD2_USB_CLK>;
  414. };
  415. usb1: ohci@1880000 {
  416. compatible = "generic-ohci";
  417. reg = <0x1880000 0x1000>;
  418. interrupts = <0 67 4>;
  419. clocks = <&clock HIX5HD2_USB_CLK>;
  420. };
  421. peripheral_ctrl: syscon@a20000 {
  422. compatible = "syscon";
  423. reg = <0xa20000 0x1000>;
  424. };
  425. sata_phy: phy@1900000 {
  426. compatible = "hisilicon,hix5hd2-sata-phy";
  427. reg = <0x1900000 0x10000>;
  428. #phy-cells = <0>;
  429. hisilicon,peripheral-syscon = <&peripheral_ctrl>;
  430. hisilicon,power-reg = <0x8 10>;
  431. };
  432. ahci: sata@1900000 {
  433. compatible = "hisilicon,hisi-ahci";
  434. reg = <0x1900000 0x10000>;
  435. interrupts = <0 70 4>;
  436. clocks = <&clock HIX5HD2_SATA_CLK>;
  437. };
  438. ir: ir@001000 {
  439. compatible = "hisilicon,hix5hd2-ir";
  440. reg = <0x001000 0x1000>;
  441. interrupts = <0 47 4>;
  442. clocks = <&clock HIX5HD2_FIXED_24M>;
  443. hisilicon,power-syscon = <&sysctrl>;
  444. };
  445. i2c0: i2c@b10000 {
  446. compatible = "hisilicon,hix5hd2-i2c";
  447. reg = <0xb10000 0x1000>;
  448. interrupts = <0 38 4>;
  449. clocks = <&clock HIX5HD2_I2C0_RST>;
  450. #address-cells = <1>;
  451. #size-cells = <0>;
  452. status = "disabled";
  453. };
  454. i2c1: i2c@b11000 {
  455. compatible = "hisilicon,hix5hd2-i2c";
  456. reg = <0xb11000 0x1000>;
  457. interrupts = <0 39 4>;
  458. clocks = <&clock HIX5HD2_I2C1_RST>;
  459. #address-cells = <1>;
  460. #size-cells = <0>;
  461. status = "disabled";
  462. };
  463. i2c2: i2c@b12000 {
  464. compatible = "hisilicon,hix5hd2-i2c";
  465. reg = <0xb12000 0x1000>;
  466. interrupts = <0 40 4>;
  467. clocks = <&clock HIX5HD2_I2C2_RST>;
  468. #address-cells = <1>;
  469. #size-cells = <0>;
  470. status = "disabled";
  471. };
  472. i2c3: i2c@b13000 {
  473. compatible = "hisilicon,hix5hd2-i2c";
  474. reg = <0xb13000 0x1000>;
  475. interrupts = <0 41 4>;
  476. clocks = <&clock HIX5HD2_I2C3_RST>;
  477. #address-cells = <1>;
  478. #size-cells = <0>;
  479. status = "disabled";
  480. };
  481. i2c4: i2c@b16000 {
  482. compatible = "hisilicon,hix5hd2-i2c";
  483. reg = <0xb16000 0x1000>;
  484. interrupts = <0 43 4>;
  485. clocks = <&clock HIX5HD2_I2C4_RST>;
  486. #address-cells = <1>;
  487. #size-cells = <0>;
  488. status = "disabled";
  489. };
  490. i2c5: i2c@b17000 {
  491. compatible = "hisilicon,hix5hd2-i2c";
  492. reg = <0xb17000 0x1000>;
  493. interrupts = <0 44 4>;
  494. clocks = <&clock HIX5HD2_I2C5_RST>;
  495. #address-cells = <1>;
  496. #size-cells = <0>;
  497. status = "disabled";
  498. };
  499. };
  500. };