exynos5410.dtsi 7.8 KB

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  1. /*
  2. * SAMSUNG EXYNOS5410 SoC device tree source
  3. *
  4. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
  8. * EXYNOS5410 based board files can include this file and provide
  9. * values for board specfic bindings.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include "exynos54xx.dtsi"
  16. #include "exynos-syscon-restart.dtsi"
  17. #include <dt-bindings/clock/exynos5410.h>
  18. #include <dt-bindings/interrupt-controller/arm-gic.h>
  19. / {
  20. compatible = "samsung,exynos5410", "samsung,exynos5";
  21. interrupt-parent = <&gic>;
  22. aliases {
  23. pinctrl0 = &pinctrl_0;
  24. pinctrl1 = &pinctrl_1;
  25. pinctrl2 = &pinctrl_2;
  26. pinctrl3 = &pinctrl_3;
  27. };
  28. cpus {
  29. #address-cells = <1>;
  30. #size-cells = <0>;
  31. cpu0: cpu@0 {
  32. device_type = "cpu";
  33. compatible = "arm,cortex-a15";
  34. reg = <0x0>;
  35. clock-frequency = <1600000000>;
  36. };
  37. cpu1: cpu@1 {
  38. device_type = "cpu";
  39. compatible = "arm,cortex-a15";
  40. reg = <0x1>;
  41. clock-frequency = <1600000000>;
  42. };
  43. cpu2: cpu@2 {
  44. device_type = "cpu";
  45. compatible = "arm,cortex-a15";
  46. reg = <0x2>;
  47. clock-frequency = <1600000000>;
  48. };
  49. cpu3: cpu@3 {
  50. device_type = "cpu";
  51. compatible = "arm,cortex-a15";
  52. reg = <0x3>;
  53. clock-frequency = <1600000000>;
  54. };
  55. };
  56. soc: soc {
  57. compatible = "simple-bus";
  58. #address-cells = <1>;
  59. #size-cells = <1>;
  60. ranges;
  61. pmu_system_controller: system-controller@10040000 {
  62. compatible = "samsung,exynos5410-pmu", "syscon";
  63. reg = <0x10040000 0x5000>;
  64. clock-names = "clkout16";
  65. clocks = <&fin_pll>;
  66. #clock-cells = <1>;
  67. };
  68. clock: clock-controller@10010000 {
  69. compatible = "samsung,exynos5410-clock";
  70. reg = <0x10010000 0x30000>;
  71. #clock-cells = <1>;
  72. };
  73. tmu_cpu0: tmu@10060000 {
  74. compatible = "samsung,exynos5420-tmu";
  75. reg = <0x10060000 0x100>;
  76. interrupts = <GIC_SPI 65 0>;
  77. clocks = <&clock CLK_TMU>;
  78. clock-names = "tmu_apbif";
  79. #include "exynos4412-tmu-sensor-conf.dtsi"
  80. };
  81. tmu_cpu1: tmu@10064000 {
  82. compatible = "samsung,exynos5420-tmu";
  83. reg = <0x10064000 0x100>;
  84. interrupts = <GIC_SPI 183 0>;
  85. clocks = <&clock CLK_TMU>;
  86. clock-names = "tmu_apbif";
  87. #include "exynos4412-tmu-sensor-conf.dtsi"
  88. };
  89. tmu_cpu2: tmu@10068000 {
  90. compatible = "samsung,exynos5420-tmu";
  91. reg = <0x10068000 0x100>;
  92. interrupts = <GIC_SPI 184 0>;
  93. clocks = <&clock CLK_TMU>;
  94. clock-names = "tmu_apbif";
  95. #include "exynos4412-tmu-sensor-conf.dtsi"
  96. };
  97. tmu_cpu3: tmu@1006c000 {
  98. compatible = "samsung,exynos5420-tmu";
  99. reg = <0x1006c000 0x100>;
  100. interrupts = <GIC_SPI 185 0>;
  101. clocks = <&clock CLK_TMU>;
  102. clock-names = "tmu_apbif";
  103. #include "exynos4412-tmu-sensor-conf.dtsi"
  104. };
  105. mmc_0: mmc@12200000 {
  106. compatible = "samsung,exynos5250-dw-mshc";
  107. reg = <0x12200000 0x1000>;
  108. interrupts = <0 75 0>;
  109. #address-cells = <1>;
  110. #size-cells = <0>;
  111. clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
  112. clock-names = "biu", "ciu";
  113. fifo-depth = <0x80>;
  114. status = "disabled";
  115. };
  116. mmc_1: mmc@12210000 {
  117. compatible = "samsung,exynos5250-dw-mshc";
  118. reg = <0x12210000 0x1000>;
  119. interrupts = <0 76 0>;
  120. #address-cells = <1>;
  121. #size-cells = <0>;
  122. clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
  123. clock-names = "biu", "ciu";
  124. fifo-depth = <0x80>;
  125. status = "disabled";
  126. };
  127. mmc_2: mmc@12220000 {
  128. compatible = "samsung,exynos5250-dw-mshc";
  129. reg = <0x12220000 0x1000>;
  130. interrupts = <0 77 0>;
  131. #address-cells = <1>;
  132. #size-cells = <0>;
  133. clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
  134. clock-names = "biu", "ciu";
  135. fifo-depth = <0x80>;
  136. status = "disabled";
  137. };
  138. pinctrl_0: pinctrl@13400000 {
  139. compatible = "samsung,exynos5410-pinctrl";
  140. reg = <0x13400000 0x1000>;
  141. interrupts = <0 45 0>;
  142. wakeup-interrupt-controller {
  143. compatible = "samsung,exynos4210-wakeup-eint";
  144. interrupt-parent = <&gic>;
  145. interrupts = <0 32 0>;
  146. };
  147. };
  148. pinctrl_1: pinctrl@14000000 {
  149. compatible = "samsung,exynos5410-pinctrl";
  150. reg = <0x14000000 0x1000>;
  151. interrupts = <0 46 0>;
  152. };
  153. pinctrl_2: pinctrl@10d10000 {
  154. compatible = "samsung,exynos5410-pinctrl";
  155. reg = <0x10d10000 0x1000>;
  156. interrupts = <0 50 0>;
  157. };
  158. pinctrl_3: pinctrl@03860000 {
  159. compatible = "samsung,exynos5410-pinctrl";
  160. reg = <0x03860000 0x1000>;
  161. interrupts = <0 47 0>;
  162. };
  163. };
  164. thermal-zones {
  165. cpu0_thermal: cpu0-thermal {
  166. thermal-sensors = <&tmu_cpu0>;
  167. #include "exynos5420-trip-points.dtsi"
  168. };
  169. cpu1_thermal: cpu1-thermal {
  170. thermal-sensors = <&tmu_cpu1>;
  171. #include "exynos5420-trip-points.dtsi"
  172. };
  173. cpu2_thermal: cpu2-thermal {
  174. thermal-sensors = <&tmu_cpu2>;
  175. #include "exynos5420-trip-points.dtsi"
  176. };
  177. cpu3_thermal: cpu3-thermal {
  178. thermal-sensors = <&tmu_cpu3>;
  179. #include "exynos5420-trip-points.dtsi"
  180. };
  181. };
  182. };
  183. &i2c_0 {
  184. clocks = <&clock CLK_I2C0>;
  185. clock-names = "i2c";
  186. pinctrl-names = "default";
  187. pinctrl-0 = <&i2c0_bus>;
  188. };
  189. &i2c_1 {
  190. clocks = <&clock CLK_I2C1>;
  191. clock-names = "i2c";
  192. pinctrl-names = "default";
  193. pinctrl-0 = <&i2c1_bus>;
  194. };
  195. &i2c_2 {
  196. clocks = <&clock CLK_I2C2>;
  197. clock-names = "i2c";
  198. pinctrl-names = "default";
  199. pinctrl-0 = <&i2c2_bus>;
  200. };
  201. &i2c_3 {
  202. clocks = <&clock CLK_I2C3>;
  203. clock-names = "i2c";
  204. pinctrl-names = "default";
  205. pinctrl-0 = <&i2c3_bus>;
  206. };
  207. &hsi2c_4 {
  208. clocks = <&clock CLK_USI0>;
  209. clock-names = "hsi2c";
  210. pinctrl-names = "default";
  211. pinctrl-0 = <&i2c4_hs_bus>;
  212. };
  213. &hsi2c_5 {
  214. clocks = <&clock CLK_USI1>;
  215. clock-names = "hsi2c";
  216. pinctrl-names = "default";
  217. pinctrl-0 = <&i2c5_hs_bus>;
  218. };
  219. &hsi2c_6 {
  220. clocks = <&clock CLK_USI2>;
  221. clock-names = "hsi2c";
  222. pinctrl-names = "default";
  223. pinctrl-0 = <&i2c6_hs_bus>;
  224. };
  225. &hsi2c_7 {
  226. clocks = <&clock CLK_USI3>;
  227. clock-names = "hsi2c";
  228. pinctrl-names = "default";
  229. pinctrl-0 = <&i2c7_hs_bus>;
  230. };
  231. &mct {
  232. clocks = <&fin_pll>, <&clock CLK_MCT>;
  233. clock-names = "fin_pll", "mct";
  234. };
  235. &pwm {
  236. clocks = <&clock CLK_PWM>;
  237. clock-names = "timers";
  238. };
  239. &rtc {
  240. clocks = <&clock CLK_RTC>;
  241. clock-names = "rtc";
  242. status = "disabled";
  243. };
  244. &serial_0 {
  245. clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
  246. clock-names = "uart", "clk_uart_baud0";
  247. };
  248. &serial_1 {
  249. clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
  250. clock-names = "uart", "clk_uart_baud0";
  251. };
  252. &serial_2 {
  253. clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
  254. clock-names = "uart", "clk_uart_baud0";
  255. };
  256. &serial_3 {
  257. clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
  258. clock-names = "uart", "clk_uart_baud0";
  259. };
  260. &sss {
  261. clocks = <&clock CLK_SSS>;
  262. clock-names = "secss";
  263. };
  264. &sromc {
  265. #address-cells = <2>;
  266. #size-cells = <1>;
  267. ranges = <0 0 0x04000000 0x20000
  268. 1 0 0x05000000 0x20000
  269. 2 0 0x06000000 0x20000
  270. 3 0 0x07000000 0x20000>;
  271. };
  272. &usbdrd3_0 {
  273. clocks = <&clock CLK_USBD300>;
  274. clock-names = "usbdrd30";
  275. };
  276. &usbdrd_phy0 {
  277. clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
  278. clock-names = "phy", "ref";
  279. samsung,pmu-syscon = <&pmu_system_controller>;
  280. };
  281. &usbdrd3_1 {
  282. clocks = <&clock CLK_USBD301>;
  283. clock-names = "usbdrd30";
  284. };
  285. &usbdrd_dwc3_1 {
  286. interrupts = <GIC_SPI 200 0>;
  287. };
  288. &usbdrd_phy1 {
  289. clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
  290. clock-names = "phy", "ref";
  291. samsung,pmu-syscon = <&pmu_system_controller>;
  292. };
  293. &usbhost1 {
  294. clocks = <&clock CLK_USBH20>;
  295. clock-names = "usbhost";
  296. };
  297. &usbhost2 {
  298. clocks = <&clock CLK_USBH20>;
  299. clock-names = "usbhost";
  300. };
  301. &usb2_phy {
  302. clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
  303. clock-names = "phy", "ref";
  304. samsung,sysreg-phandle = <&sysreg_system_controller>;
  305. samsung,pmureg-phandle = <&pmu_system_controller>;
  306. };
  307. &watchdog {
  308. clocks = <&clock CLK_WDT>;
  309. clock-names = "watchdog";
  310. samsung,syscon-phandle = <&pmu_system_controller>;
  311. };
  312. #include "exynos5410-pinctrl.dtsi"