exynos5260.dtsi 7.4 KB

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  1. /*
  2. * SAMSUNG EXYNOS5260 SoC device tree source
  3. *
  4. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <dt-bindings/clock/exynos5260-clk.h>
  12. / {
  13. compatible = "samsung,exynos5260", "samsung,exynos5";
  14. interrupt-parent = <&gic>;
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. pinctrl0 = &pinctrl_0;
  19. pinctrl1 = &pinctrl_1;
  20. pinctrl2 = &pinctrl_2;
  21. serial0 = &uart0;
  22. serial1 = &uart1;
  23. serial2 = &uart2;
  24. serial3 = &uart3;
  25. };
  26. cpus {
  27. #address-cells = <1>;
  28. #size-cells = <0>;
  29. cpu@0 {
  30. device_type = "cpu";
  31. compatible = "arm,cortex-a15";
  32. reg = <0x0>;
  33. cci-control-port = <&cci_control1>;
  34. };
  35. cpu@1 {
  36. device_type = "cpu";
  37. compatible = "arm,cortex-a15";
  38. reg = <0x1>;
  39. cci-control-port = <&cci_control1>;
  40. };
  41. cpu@100 {
  42. device_type = "cpu";
  43. compatible = "arm,cortex-a7";
  44. reg = <0x100>;
  45. cci-control-port = <&cci_control0>;
  46. };
  47. cpu@101 {
  48. device_type = "cpu";
  49. compatible = "arm,cortex-a7";
  50. reg = <0x101>;
  51. cci-control-port = <&cci_control0>;
  52. };
  53. cpu@102 {
  54. device_type = "cpu";
  55. compatible = "arm,cortex-a7";
  56. reg = <0x102>;
  57. cci-control-port = <&cci_control0>;
  58. };
  59. cpu@103 {
  60. device_type = "cpu";
  61. compatible = "arm,cortex-a7";
  62. reg = <0x103>;
  63. cci-control-port = <&cci_control0>;
  64. };
  65. };
  66. soc: soc {
  67. compatible = "simple-bus";
  68. #address-cells = <1>;
  69. #size-cells = <1>;
  70. ranges;
  71. clock_top: clock-controller@10010000 {
  72. compatible = "samsung,exynos5260-clock-top";
  73. reg = <0x10010000 0x10000>;
  74. #clock-cells = <1>;
  75. };
  76. clock_peri: clock-controller@10200000 {
  77. compatible = "samsung,exynos5260-clock-peri";
  78. reg = <0x10200000 0x10000>;
  79. #clock-cells = <1>;
  80. };
  81. clock_egl: clock-controller@10600000 {
  82. compatible = "samsung,exynos5260-clock-egl";
  83. reg = <0x10600000 0x10000>;
  84. #clock-cells = <1>;
  85. };
  86. clock_kfc: clock-controller@10700000 {
  87. compatible = "samsung,exynos5260-clock-kfc";
  88. reg = <0x10700000 0x10000>;
  89. #clock-cells = <1>;
  90. };
  91. clock_g2d: clock-controller@10A00000 {
  92. compatible = "samsung,exynos5260-clock-g2d";
  93. reg = <0x10A00000 0x10000>;
  94. #clock-cells = <1>;
  95. };
  96. clock_mif: clock-controller@10CE0000 {
  97. compatible = "samsung,exynos5260-clock-mif";
  98. reg = <0x10CE0000 0x10000>;
  99. #clock-cells = <1>;
  100. };
  101. clock_mfc: clock-controller@11090000 {
  102. compatible = "samsung,exynos5260-clock-mfc";
  103. reg = <0x11090000 0x10000>;
  104. #clock-cells = <1>;
  105. };
  106. clock_g3d: clock-controller@11830000 {
  107. compatible = "samsung,exynos5260-clock-g3d";
  108. reg = <0x11830000 0x10000>;
  109. #clock-cells = <1>;
  110. };
  111. clock_fsys: clock-controller@122E0000 {
  112. compatible = "samsung,exynos5260-clock-fsys";
  113. reg = <0x122E0000 0x10000>;
  114. #clock-cells = <1>;
  115. };
  116. clock_aud: clock-controller@128C0000 {
  117. compatible = "samsung,exynos5260-clock-aud";
  118. reg = <0x128C0000 0x10000>;
  119. #clock-cells = <1>;
  120. };
  121. clock_isp: clock-controller@133C0000 {
  122. compatible = "samsung,exynos5260-clock-isp";
  123. reg = <0x133C0000 0x10000>;
  124. #clock-cells = <1>;
  125. };
  126. clock_gscl: clock-controller@13F00000 {
  127. compatible = "samsung,exynos5260-clock-gscl";
  128. reg = <0x13F00000 0x10000>;
  129. #clock-cells = <1>;
  130. };
  131. clock_disp: clock-controller@14550000 {
  132. compatible = "samsung,exynos5260-clock-disp";
  133. reg = <0x14550000 0x10000>;
  134. #clock-cells = <1>;
  135. };
  136. gic: interrupt-controller@10481000 {
  137. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  138. #interrupt-cells = <3>;
  139. #address-cells = <0>;
  140. #size-cells = <0>;
  141. interrupt-controller;
  142. reg = <0x10481000 0x1000>,
  143. <0x10482000 0x1000>,
  144. <0x10484000 0x2000>,
  145. <0x10486000 0x2000>;
  146. interrupts = <1 9 0xf04>;
  147. };
  148. chipid: chipid@10000000 {
  149. compatible = "samsung,exynos4210-chipid";
  150. reg = <0x10000000 0x100>;
  151. };
  152. mct: mct@100B0000 {
  153. compatible = "samsung,exynos4210-mct";
  154. reg = <0x100B0000 0x1000>;
  155. clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
  156. clock-names = "fin_pll", "mct";
  157. interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
  158. <0 107 0>, <0 122 0>, <0 123 0>,
  159. <0 124 0>, <0 125 0>, <0 126 0>,
  160. <0 127 0>, <0 128 0>, <0 129 0>;
  161. };
  162. cci: cci@10F00000 {
  163. compatible = "arm,cci-400";
  164. #address-cells = <1>;
  165. #size-cells = <1>;
  166. reg = <0x10F00000 0x1000>;
  167. ranges = <0x0 0x10F00000 0x6000>;
  168. cci_control0: slave-if@4000 {
  169. compatible = "arm,cci-400-ctrl-if";
  170. interface-type = "ace";
  171. reg = <0x4000 0x1000>;
  172. };
  173. cci_control1: slave-if@5000 {
  174. compatible = "arm,cci-400-ctrl-if";
  175. interface-type = "ace";
  176. reg = <0x5000 0x1000>;
  177. };
  178. };
  179. pinctrl_0: pinctrl@11600000 {
  180. compatible = "samsung,exynos5260-pinctrl";
  181. reg = <0x11600000 0x1000>;
  182. interrupts = <0 79 0>;
  183. wakeup-interrupt-controller {
  184. compatible = "samsung,exynos4210-wakeup-eint";
  185. interrupt-parent = <&gic>;
  186. interrupts = <0 32 0>;
  187. };
  188. };
  189. pinctrl_1: pinctrl@12290000 {
  190. compatible = "samsung,exynos5260-pinctrl";
  191. reg = <0x12290000 0x1000>;
  192. interrupts = <0 157 0>;
  193. };
  194. pinctrl_2: pinctrl@128B0000 {
  195. compatible = "samsung,exynos5260-pinctrl";
  196. reg = <0x128B0000 0x1000>;
  197. interrupts = <0 243 0>;
  198. };
  199. pmu_system_controller: system-controller@10D50000 {
  200. compatible = "samsung,exynos5260-pmu", "syscon";
  201. reg = <0x10D50000 0x10000>;
  202. };
  203. uart0: serial@12C00000 {
  204. compatible = "samsung,exynos4210-uart";
  205. reg = <0x12C00000 0x100>;
  206. interrupts = <0 146 0>;
  207. clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
  208. clock-names = "uart", "clk_uart_baud0";
  209. status = "disabled";
  210. };
  211. uart1: serial@12C10000 {
  212. compatible = "samsung,exynos4210-uart";
  213. reg = <0x12C10000 0x100>;
  214. interrupts = <0 147 0>;
  215. clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
  216. clock-names = "uart", "clk_uart_baud0";
  217. status = "disabled";
  218. };
  219. uart2: serial@12C20000 {
  220. compatible = "samsung,exynos4210-uart";
  221. reg = <0x12C20000 0x100>;
  222. interrupts = <0 148 0>;
  223. clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
  224. clock-names = "uart", "clk_uart_baud0";
  225. status = "disabled";
  226. };
  227. uart3: serial@12860000 {
  228. compatible = "samsung,exynos4210-uart";
  229. reg = <0x12860000 0x100>;
  230. interrupts = <0 145 0>;
  231. clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
  232. clock-names = "uart", "clk_uart_baud0";
  233. status = "disabled";
  234. };
  235. mmc_0: mmc@12140000 {
  236. compatible = "samsung,exynos5250-dw-mshc";
  237. reg = <0x12140000 0x2000>;
  238. interrupts = <0 156 0>;
  239. #address-cells = <1>;
  240. #size-cells = <0>;
  241. clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
  242. clock-names = "biu", "ciu";
  243. fifo-depth = <64>;
  244. status = "disabled";
  245. };
  246. mmc_1: mmc@12150000 {
  247. compatible = "samsung,exynos5250-dw-mshc";
  248. reg = <0x12150000 0x2000>;
  249. interrupts = <0 158 0>;
  250. #address-cells = <1>;
  251. #size-cells = <0>;
  252. clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
  253. clock-names = "biu", "ciu";
  254. fifo-depth = <64>;
  255. status = "disabled";
  256. };
  257. mmc_2: mmc@12160000 {
  258. compatible = "samsung,exynos5250-dw-mshc";
  259. reg = <0x12160000 0x2000>;
  260. interrupts = <0 159 0>;
  261. #address-cells = <1>;
  262. #size-cells = <0>;
  263. clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
  264. clock-names = "biu", "ciu";
  265. fifo-depth = <64>;
  266. status = "disabled";
  267. };
  268. };
  269. };
  270. #include "exynos5260-pinctrl.dtsi"