exynos4x12.dtsi 14 KB

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  1. /*
  2. * Samsung's Exynos4x12 SoCs device tree source
  3. *
  4. * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
  8. * based board files can include this file and provide values for board specfic
  9. * bindings.
  10. *
  11. * Note: This file does not include device nodes for all the controllers in
  12. * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
  13. * nodes can be added to this file.
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License version 2 as
  17. * published by the Free Software Foundation.
  18. */
  19. #include "exynos4.dtsi"
  20. #include "exynos4x12-pinctrl.dtsi"
  21. #include "exynos4-cpu-thermal.dtsi"
  22. / {
  23. aliases {
  24. pinctrl0 = &pinctrl_0;
  25. pinctrl1 = &pinctrl_1;
  26. pinctrl2 = &pinctrl_2;
  27. pinctrl3 = &pinctrl_3;
  28. fimc-lite0 = &fimc_lite_0;
  29. fimc-lite1 = &fimc_lite_1;
  30. mshc0 = &mshc_0;
  31. };
  32. sysram@02020000 {
  33. compatible = "mmio-sram";
  34. reg = <0x02020000 0x40000>;
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. ranges = <0 0x02020000 0x40000>;
  38. smp-sysram@0 {
  39. compatible = "samsung,exynos4210-sysram";
  40. reg = <0x0 0x1000>;
  41. };
  42. smp-sysram@2f000 {
  43. compatible = "samsung,exynos4210-sysram-ns";
  44. reg = <0x2f000 0x1000>;
  45. };
  46. };
  47. pd_isp: isp-power-domain@10023CA0 {
  48. compatible = "samsung,exynos4210-pd";
  49. reg = <0x10023CA0 0x20>;
  50. #power-domain-cells = <0>;
  51. };
  52. l2c: l2-cache-controller@10502000 {
  53. compatible = "arm,pl310-cache";
  54. reg = <0x10502000 0x1000>;
  55. cache-unified;
  56. cache-level = <2>;
  57. arm,tag-latency = <2 2 1>;
  58. arm,data-latency = <3 2 1>;
  59. arm,double-linefill = <1>;
  60. arm,double-linefill-incr = <0>;
  61. arm,double-linefill-wrap = <1>;
  62. arm,prefetch-drop = <1>;
  63. arm,prefetch-offset = <7>;
  64. };
  65. clock: clock-controller@10030000 {
  66. compatible = "samsung,exynos4412-clock";
  67. reg = <0x10030000 0x20000>;
  68. #clock-cells = <1>;
  69. };
  70. mct@10050000 {
  71. compatible = "samsung,exynos4412-mct";
  72. reg = <0x10050000 0x800>;
  73. interrupt-parent = <&mct_map>;
  74. interrupts = <0>, <1>, <2>, <3>, <4>;
  75. clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
  76. clock-names = "fin_pll", "mct";
  77. mct_map: mct-map {
  78. #interrupt-cells = <1>;
  79. #address-cells = <0>;
  80. #size-cells = <0>;
  81. interrupt-map = <0 &gic 0 57 0>,
  82. <1 &combiner 12 5>,
  83. <2 &combiner 12 6>,
  84. <3 &combiner 12 7>,
  85. <4 &gic 1 12 0>;
  86. };
  87. };
  88. adc: adc@126C0000 {
  89. compatible = "samsung,exynos-adc-v1";
  90. reg = <0x126C0000 0x100>;
  91. interrupt-parent = <&combiner>;
  92. interrupts = <10 3>;
  93. clocks = <&clock CLK_TSADC>;
  94. clock-names = "adc";
  95. #io-channel-cells = <1>;
  96. io-channel-ranges;
  97. samsung,syscon-phandle = <&pmu_system_controller>;
  98. status = "disabled";
  99. };
  100. g2d: g2d@10800000 {
  101. compatible = "samsung,exynos4212-g2d";
  102. reg = <0x10800000 0x1000>;
  103. interrupts = <0 89 0>;
  104. clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
  105. clock-names = "sclk_fimg2d", "fimg2d";
  106. iommus = <&sysmmu_g2d>;
  107. };
  108. camera {
  109. clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
  110. <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
  111. clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
  112. /* fimc_[0-3] are configured outside, under phandles */
  113. fimc_lite_0: fimc-lite@12390000 {
  114. compatible = "samsung,exynos4212-fimc-lite";
  115. reg = <0x12390000 0x1000>;
  116. interrupts = <0 105 0>;
  117. power-domains = <&pd_isp>;
  118. clocks = <&clock CLK_FIMC_LITE0>;
  119. clock-names = "flite";
  120. iommus = <&sysmmu_fimc_lite0>;
  121. status = "disabled";
  122. };
  123. fimc_lite_1: fimc-lite@123A0000 {
  124. compatible = "samsung,exynos4212-fimc-lite";
  125. reg = <0x123A0000 0x1000>;
  126. interrupts = <0 106 0>;
  127. power-domains = <&pd_isp>;
  128. clocks = <&clock CLK_FIMC_LITE1>;
  129. clock-names = "flite";
  130. iommus = <&sysmmu_fimc_lite1>;
  131. status = "disabled";
  132. };
  133. fimc_is: fimc-is@12000000 {
  134. compatible = "samsung,exynos4212-fimc-is", "simple-bus";
  135. reg = <0x12000000 0x260000>;
  136. interrupts = <0 90 0>, <0 95 0>;
  137. power-domains = <&pd_isp>;
  138. clocks = <&clock CLK_FIMC_LITE0>,
  139. <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
  140. <&clock CLK_PPMUISPMX>,
  141. <&clock CLK_MOUT_MPLL_USER_T>,
  142. <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
  143. <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
  144. <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>,
  145. <&clock CLK_PWM_ISP>,
  146. <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>,
  147. <&clock CLK_DIV_MCUISP0>,
  148. <&clock CLK_DIV_MCUISP1>,
  149. <&clock CLK_UART_ISP_SCLK>,
  150. <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
  151. <&clock CLK_ACLK400_MCUISP>,
  152. <&clock CLK_DIV_ACLK400_MCUISP>;
  153. clock-names = "lite0", "lite1", "ppmuispx",
  154. "ppmuispmx", "mpll", "isp",
  155. "drc", "fd", "mcuisp",
  156. "gicisp", "mcuctl_isp", "pwm_isp",
  157. "ispdiv0", "ispdiv1", "mcuispdiv0",
  158. "mcuispdiv1", "uart", "aclk200",
  159. "div_aclk200", "aclk400mcuisp",
  160. "div_aclk400mcuisp";
  161. iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
  162. <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
  163. iommu-names = "isp", "drc", "fd", "mcuctl";
  164. #address-cells = <1>;
  165. #size-cells = <1>;
  166. ranges;
  167. status = "disabled";
  168. pmu@10020000 {
  169. reg = <0x10020000 0x3000>;
  170. };
  171. i2c1_isp: i2c-isp@12140000 {
  172. compatible = "samsung,exynos4212-i2c-isp";
  173. reg = <0x12140000 0x100>;
  174. clocks = <&clock CLK_I2C1_ISP>;
  175. clock-names = "i2c_isp";
  176. #address-cells = <1>;
  177. #size-cells = <0>;
  178. };
  179. };
  180. };
  181. mshc_0: mmc@12550000 {
  182. compatible = "samsung,exynos4412-dw-mshc";
  183. reg = <0x12550000 0x1000>;
  184. interrupts = <0 77 0>;
  185. #address-cells = <1>;
  186. #size-cells = <0>;
  187. fifo-depth = <0x80>;
  188. clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
  189. clock-names = "biu", "ciu";
  190. status = "disabled";
  191. };
  192. sysmmu_g2d: sysmmu@10A40000{
  193. compatible = "samsung,exynos-sysmmu";
  194. reg = <0x10A40000 0x1000>;
  195. interrupt-parent = <&combiner>;
  196. interrupts = <4 7>;
  197. clock-names = "sysmmu", "master";
  198. clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
  199. #iommu-cells = <0>;
  200. };
  201. sysmmu_fimc_isp: sysmmu@12260000 {
  202. compatible = "samsung,exynos-sysmmu";
  203. reg = <0x12260000 0x1000>;
  204. interrupt-parent = <&combiner>;
  205. interrupts = <16 2>;
  206. power-domains = <&pd_isp>;
  207. clock-names = "sysmmu";
  208. clocks = <&clock CLK_SMMU_ISP>;
  209. #iommu-cells = <0>;
  210. };
  211. sysmmu_fimc_drc: sysmmu@12270000 {
  212. compatible = "samsung,exynos-sysmmu";
  213. reg = <0x12270000 0x1000>;
  214. interrupt-parent = <&combiner>;
  215. interrupts = <16 3>;
  216. power-domains = <&pd_isp>;
  217. clock-names = "sysmmu";
  218. clocks = <&clock CLK_SMMU_DRC>;
  219. #iommu-cells = <0>;
  220. };
  221. sysmmu_fimc_fd: sysmmu@122A0000 {
  222. compatible = "samsung,exynos-sysmmu";
  223. reg = <0x122A0000 0x1000>;
  224. interrupt-parent = <&combiner>;
  225. interrupts = <16 4>;
  226. power-domains = <&pd_isp>;
  227. clock-names = "sysmmu";
  228. clocks = <&clock CLK_SMMU_FD>;
  229. #iommu-cells = <0>;
  230. };
  231. sysmmu_fimc_mcuctl: sysmmu@122B0000 {
  232. compatible = "samsung,exynos-sysmmu";
  233. reg = <0x122B0000 0x1000>;
  234. interrupt-parent = <&combiner>;
  235. interrupts = <16 5>;
  236. power-domains = <&pd_isp>;
  237. clock-names = "sysmmu";
  238. clocks = <&clock CLK_SMMU_ISPCX>;
  239. #iommu-cells = <0>;
  240. };
  241. sysmmu_fimc_lite0: sysmmu@123B0000 {
  242. compatible = "samsung,exynos-sysmmu";
  243. reg = <0x123B0000 0x1000>;
  244. interrupt-parent = <&combiner>;
  245. interrupts = <16 0>;
  246. power-domains = <&pd_isp>;
  247. clock-names = "sysmmu", "master";
  248. clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>;
  249. #iommu-cells = <0>;
  250. };
  251. sysmmu_fimc_lite1: sysmmu@123C0000 {
  252. compatible = "samsung,exynos-sysmmu";
  253. reg = <0x123C0000 0x1000>;
  254. interrupt-parent = <&combiner>;
  255. interrupts = <16 1>;
  256. power-domains = <&pd_isp>;
  257. clock-names = "sysmmu", "master";
  258. clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
  259. #iommu-cells = <0>;
  260. };
  261. bus_dmc: bus_dmc {
  262. compatible = "samsung,exynos-bus";
  263. clocks = <&clock CLK_DIV_DMC>;
  264. clock-names = "bus";
  265. operating-points-v2 = <&bus_dmc_opp_table>;
  266. status = "disabled";
  267. };
  268. bus_acp: bus_acp {
  269. compatible = "samsung,exynos-bus";
  270. clocks = <&clock CLK_DIV_ACP>;
  271. clock-names = "bus";
  272. operating-points-v2 = <&bus_acp_opp_table>;
  273. status = "disabled";
  274. };
  275. bus_c2c: bus_c2c {
  276. compatible = "samsung,exynos-bus";
  277. clocks = <&clock CLK_DIV_C2C>;
  278. clock-names = "bus";
  279. operating-points-v2 = <&bus_dmc_opp_table>;
  280. status = "disabled";
  281. };
  282. bus_dmc_opp_table: opp_table1 {
  283. compatible = "operating-points-v2";
  284. opp-shared;
  285. opp@100000000 {
  286. opp-hz = /bits/ 64 <100000000>;
  287. opp-microvolt = <900000>;
  288. };
  289. opp@134000000 {
  290. opp-hz = /bits/ 64 <134000000>;
  291. opp-microvolt = <900000>;
  292. };
  293. opp@160000000 {
  294. opp-hz = /bits/ 64 <160000000>;
  295. opp-microvolt = <900000>;
  296. };
  297. opp@267000000 {
  298. opp-hz = /bits/ 64 <267000000>;
  299. opp-microvolt = <950000>;
  300. };
  301. opp@400000000 {
  302. opp-hz = /bits/ 64 <400000000>;
  303. opp-microvolt = <1050000>;
  304. };
  305. };
  306. bus_acp_opp_table: opp_table2 {
  307. compatible = "operating-points-v2";
  308. opp-shared;
  309. opp@100000000 {
  310. opp-hz = /bits/ 64 <100000000>;
  311. };
  312. opp@134000000 {
  313. opp-hz = /bits/ 64 <134000000>;
  314. };
  315. opp@160000000 {
  316. opp-hz = /bits/ 64 <160000000>;
  317. };
  318. opp@267000000 {
  319. opp-hz = /bits/ 64 <267000000>;
  320. };
  321. };
  322. bus_leftbus: bus_leftbus {
  323. compatible = "samsung,exynos-bus";
  324. clocks = <&clock CLK_DIV_GDL>;
  325. clock-names = "bus";
  326. operating-points-v2 = <&bus_leftbus_opp_table>;
  327. status = "disabled";
  328. };
  329. bus_rightbus: bus_rightbus {
  330. compatible = "samsung,exynos-bus";
  331. clocks = <&clock CLK_DIV_GDR>;
  332. clock-names = "bus";
  333. operating-points-v2 = <&bus_leftbus_opp_table>;
  334. status = "disabled";
  335. };
  336. bus_display: bus_display {
  337. compatible = "samsung,exynos-bus";
  338. clocks = <&clock CLK_ACLK160>;
  339. clock-names = "bus";
  340. operating-points-v2 = <&bus_display_opp_table>;
  341. status = "disabled";
  342. };
  343. bus_fsys: bus_fsys {
  344. compatible = "samsung,exynos-bus";
  345. clocks = <&clock CLK_ACLK133>;
  346. clock-names = "bus";
  347. operating-points-v2 = <&bus_fsys_opp_table>;
  348. status = "disabled";
  349. };
  350. bus_peri: bus_peri {
  351. compatible = "samsung,exynos-bus";
  352. clocks = <&clock CLK_ACLK100>;
  353. clock-names = "bus";
  354. operating-points-v2 = <&bus_peri_opp_table>;
  355. status = "disabled";
  356. };
  357. bus_mfc: bus_mfc {
  358. compatible = "samsung,exynos-bus";
  359. clocks = <&clock CLK_SCLK_MFC>;
  360. clock-names = "bus";
  361. operating-points-v2 = <&bus_leftbus_opp_table>;
  362. status = "disabled";
  363. };
  364. bus_leftbus_opp_table: opp_table3 {
  365. compatible = "operating-points-v2";
  366. opp-shared;
  367. opp@100000000 {
  368. opp-hz = /bits/ 64 <100000000>;
  369. opp-microvolt = <900000>;
  370. };
  371. opp@134000000 {
  372. opp-hz = /bits/ 64 <134000000>;
  373. opp-microvolt = <925000>;
  374. };
  375. opp@160000000 {
  376. opp-hz = /bits/ 64 <160000000>;
  377. opp-microvolt = <950000>;
  378. };
  379. opp@200000000 {
  380. opp-hz = /bits/ 64 <200000000>;
  381. opp-microvolt = <1000000>;
  382. };
  383. };
  384. bus_display_opp_table: opp_table4 {
  385. compatible = "operating-points-v2";
  386. opp-shared;
  387. opp@160000000 {
  388. opp-hz = /bits/ 64 <160000000>;
  389. };
  390. opp@200000000 {
  391. opp-hz = /bits/ 64 <200000000>;
  392. };
  393. };
  394. bus_fsys_opp_table: opp_table5 {
  395. compatible = "operating-points-v2";
  396. opp-shared;
  397. opp@100000000 {
  398. opp-hz = /bits/ 64 <100000000>;
  399. };
  400. opp@134000000 {
  401. opp-hz = /bits/ 64 <134000000>;
  402. };
  403. };
  404. bus_peri_opp_table: opp_table6 {
  405. compatible = "operating-points-v2";
  406. opp-shared;
  407. opp@50000000 {
  408. opp-hz = /bits/ 64 <50000000>;
  409. };
  410. opp@100000000 {
  411. opp-hz = /bits/ 64 <100000000>;
  412. };
  413. };
  414. };
  415. &combiner {
  416. interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  417. <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
  418. <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
  419. <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
  420. <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
  421. };
  422. &exynos_usbphy {
  423. compatible = "samsung,exynos4x12-usb2-phy";
  424. samsung,sysreg-phandle = <&sys_reg>;
  425. };
  426. &fimc_0 {
  427. compatible = "samsung,exynos4212-fimc";
  428. samsung,pix-limits = <4224 8192 1920 4224>;
  429. samsung,mainscaler-ext;
  430. samsung,isp-wb;
  431. samsung,cam-if;
  432. };
  433. &fimc_1 {
  434. compatible = "samsung,exynos4212-fimc";
  435. samsung,pix-limits = <4224 8192 1920 4224>;
  436. samsung,mainscaler-ext;
  437. samsung,isp-wb;
  438. samsung,cam-if;
  439. };
  440. &fimc_2 {
  441. compatible = "samsung,exynos4212-fimc";
  442. samsung,pix-limits = <4224 8192 1920 4224>;
  443. samsung,mainscaler-ext;
  444. samsung,isp-wb;
  445. samsung,lcd-wb;
  446. samsung,cam-if;
  447. };
  448. &fimc_3 {
  449. compatible = "samsung,exynos4212-fimc";
  450. samsung,pix-limits = <1920 8192 1366 1920>;
  451. samsung,rotators = <0>;
  452. samsung,mainscaler-ext;
  453. samsung,isp-wb;
  454. samsung,lcd-wb;
  455. };
  456. &hdmi {
  457. compatible = "samsung,exynos4212-hdmi";
  458. };
  459. &jpeg_codec {
  460. compatible = "samsung,exynos4212-jpeg";
  461. };
  462. &rotator {
  463. compatible = "samsung,exynos4212-rotator";
  464. };
  465. &mixer {
  466. compatible = "samsung,exynos4212-mixer";
  467. clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
  468. clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
  469. <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
  470. };
  471. &pinctrl_0 {
  472. compatible = "samsung,exynos4x12-pinctrl";
  473. reg = <0x11400000 0x1000>;
  474. interrupts = <0 47 0>;
  475. };
  476. &pinctrl_1 {
  477. compatible = "samsung,exynos4x12-pinctrl";
  478. reg = <0x11000000 0x1000>;
  479. interrupts = <0 46 0>;
  480. wakup_eint: wakeup-interrupt-controller {
  481. compatible = "samsung,exynos4210-wakeup-eint";
  482. interrupt-parent = <&gic>;
  483. interrupts = <0 32 0>;
  484. };
  485. };
  486. &pinctrl_2 {
  487. compatible = "samsung,exynos4x12-pinctrl";
  488. reg = <0x03860000 0x1000>;
  489. interrupt-parent = <&combiner>;
  490. interrupts = <10 0>;
  491. };
  492. &pinctrl_3 {
  493. compatible = "samsung,exynos4x12-pinctrl";
  494. reg = <0x106E0000 0x1000>;
  495. interrupts = <0 72 0>;
  496. };
  497. &pmu_system_controller {
  498. compatible = "samsung,exynos4212-pmu", "syscon";
  499. clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
  500. "clkout4", "clkout8", "clkout9";
  501. clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
  502. <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
  503. <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
  504. #clock-cells = <1>;
  505. };
  506. &tmu {
  507. compatible = "samsung,exynos4412-tmu";
  508. interrupt-parent = <&combiner>;
  509. interrupts = <2 4>;
  510. reg = <0x100C0000 0x100>;
  511. clocks = <&clock 383>;
  512. clock-names = "tmu_apbif";
  513. status = "disabled";
  514. };