exynos4415.dtsi 16 KB

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  1. /*
  2. * Samsung's Exynos4415 SoC device tree source
  3. *
  4. * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  5. *
  6. * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415
  7. * based board files can include this file and provide values for board
  8. * specific bindings.
  9. *
  10. * Note: This file does not include device nodes for all the controllers in
  11. * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional
  12. * nodes can be added to this file.
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License version 2 as
  16. * published by the Free Software Foundation.
  17. */
  18. #include <dt-bindings/clock/exynos4415.h>
  19. #include <dt-bindings/clock/exynos-audss-clk.h>
  20. / {
  21. compatible = "samsung,exynos4415";
  22. interrupt-parent = <&gic>;
  23. #address-cells = <1>;
  24. #size-cells = <1>;
  25. aliases {
  26. pinctrl0 = &pinctrl_0;
  27. pinctrl1 = &pinctrl_1;
  28. pinctrl2 = &pinctrl_2;
  29. mshc0 = &mshc_0;
  30. mshc1 = &mshc_1;
  31. mshc2 = &mshc_2;
  32. spi0 = &spi_0;
  33. spi1 = &spi_1;
  34. spi2 = &spi_2;
  35. i2c0 = &i2c_0;
  36. i2c1 = &i2c_1;
  37. i2c2 = &i2c_2;
  38. i2c3 = &i2c_3;
  39. i2c4 = &i2c_4;
  40. i2c5 = &i2c_5;
  41. i2c6 = &i2c_6;
  42. i2c7 = &i2c_7;
  43. };
  44. cpus {
  45. #address-cells = <1>;
  46. #size-cells = <0>;
  47. cpu0: cpu@a00 {
  48. device_type = "cpu";
  49. compatible = "arm,cortex-a9";
  50. reg = <0xa00>;
  51. clock-frequency = <1600000000>;
  52. };
  53. cpu1: cpu@a01 {
  54. device_type = "cpu";
  55. compatible = "arm,cortex-a9";
  56. reg = <0xa01>;
  57. clock-frequency = <1600000000>;
  58. };
  59. cpu2: cpu@a02 {
  60. device_type = "cpu";
  61. compatible = "arm,cortex-a9";
  62. reg = <0xa02>;
  63. clock-frequency = <1600000000>;
  64. };
  65. cpu3: cpu@a03 {
  66. device_type = "cpu";
  67. compatible = "arm,cortex-a9";
  68. reg = <0xa03>;
  69. clock-frequency = <1600000000>;
  70. };
  71. };
  72. soc: soc {
  73. compatible = "simple-bus";
  74. #address-cells = <1>;
  75. #size-cells = <1>;
  76. ranges;
  77. sysram@02020000 {
  78. compatible = "mmio-sram";
  79. reg = <0x02020000 0x50000>;
  80. #address-cells = <1>;
  81. #size-cells = <1>;
  82. ranges = <0 0x02020000 0x50000>;
  83. smp-sysram@0 {
  84. compatible = "samsung,exynos4210-sysram";
  85. reg = <0x0 0x1000>;
  86. };
  87. smp-sysram@4f000 {
  88. compatible = "samsung,exynos4210-sysram-ns";
  89. reg = <0x4f000 0x1000>;
  90. };
  91. };
  92. pinctrl_2: pinctrl@03860000 {
  93. compatible = "samsung,exynos4415-pinctrl";
  94. reg = <0x03860000 0x1000>;
  95. interrupts = <0 242 0>;
  96. };
  97. chipid@10000000 {
  98. compatible = "samsung,exynos4210-chipid";
  99. reg = <0x10000000 0x100>;
  100. };
  101. sysreg_system_controller: syscon@10010000 {
  102. compatible = "samsung,exynos4-sysreg", "syscon";
  103. reg = <0x10010000 0x400>;
  104. };
  105. pmu_system_controller: system-controller@10020000 {
  106. compatible = "samsung,exynos4415-pmu", "syscon";
  107. reg = <0x10020000 0x4000>;
  108. };
  109. mipi_phy: video-phy@10020710 {
  110. compatible = "samsung,s5pv210-mipi-video-phy";
  111. #phy-cells = <1>;
  112. syscon = <&pmu_system_controller>;
  113. };
  114. pd_cam: cam-power-domain@10024000 {
  115. compatible = "samsung,exynos4210-pd";
  116. reg = <0x10024000 0x20>;
  117. #power-domain-cells = <0>;
  118. };
  119. pd_tv: tv-power-domain@10024020 {
  120. compatible = "samsung,exynos4210-pd";
  121. reg = <0x10024020 0x20>;
  122. #power-domain-cells = <0>;
  123. };
  124. pd_mfc: mfc-power-domain@10024040 {
  125. compatible = "samsung,exynos4210-pd";
  126. reg = <0x10024040 0x20>;
  127. #power-domain-cells = <0>;
  128. };
  129. pd_g3d: g3d-power-domain@10024060 {
  130. compatible = "samsung,exynos4210-pd";
  131. reg = <0x10024060 0x20>;
  132. #power-domain-cells = <0>;
  133. };
  134. pd_lcd0: lcd0-power-domain@10024080 {
  135. compatible = "samsung,exynos4210-pd";
  136. reg = <0x10024080 0x20>;
  137. #power-domain-cells = <0>;
  138. };
  139. pd_isp0: isp0-power-domain@100240A0 {
  140. compatible = "samsung,exynos4210-pd";
  141. reg = <0x100240A0 0x20>;
  142. #power-domain-cells = <0>;
  143. };
  144. pd_isp1: isp1-power-domain@100240E0 {
  145. compatible = "samsung,exynos4210-pd";
  146. reg = <0x100240E0 0x20>;
  147. #power-domain-cells = <0>;
  148. };
  149. cmu: clock-controller@10030000 {
  150. compatible = "samsung,exynos4415-cmu";
  151. reg = <0x10030000 0x18000>;
  152. #clock-cells = <1>;
  153. };
  154. rtc: rtc@10070000 {
  155. compatible = "samsung,s3c6410-rtc";
  156. reg = <0x10070000 0x100>;
  157. interrupts = <0 73 0>, <0 74 0>;
  158. status = "disabled";
  159. };
  160. mct@10050000 {
  161. compatible = "samsung,exynos4210-mct";
  162. reg = <0x10050000 0x800>;
  163. interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
  164. <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
  165. clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
  166. clock-names = "fin_pll", "mct";
  167. };
  168. gic: interrupt-controller@10481000 {
  169. compatible = "arm,cortex-a9-gic";
  170. #interrupt-cells = <3>;
  171. interrupt-controller;
  172. reg = <0x10481000 0x1000>,
  173. <0x10482000 0x1000>,
  174. <0x10484000 0x2000>,
  175. <0x10486000 0x2000>;
  176. interrupts = <1 9 0xf04>;
  177. };
  178. l2c: l2-cache-controller@10502000 {
  179. compatible = "arm,pl310-cache";
  180. reg = <0x10502000 0x1000>;
  181. cache-unified;
  182. cache-level = <2>;
  183. arm,tag-latency = <2 2 1>;
  184. arm,data-latency = <3 2 1>;
  185. arm,double-linefill = <1>;
  186. arm,double-linefill-incr = <0>;
  187. arm,double-linefill-wrap = <1>;
  188. arm,prefetch-drop = <1>;
  189. arm,prefetch-offset = <7>;
  190. };
  191. cmu_dmc: clock-controller@105C0000 {
  192. compatible = "samsung,exynos4415-cmu-dmc";
  193. reg = <0x105C0000 0x3000>;
  194. #clock-cells = <1>;
  195. };
  196. pinctrl_1: pinctrl@11000000 {
  197. compatible = "samsung,exynos4415-pinctrl";
  198. reg = <0x11000000 0x1000>;
  199. interrupts = <0 225 0>;
  200. wakeup-interrupt-controller {
  201. compatible = "samsung,exynos4210-wakeup-eint";
  202. interrupt-parent = <&gic>;
  203. interrupts = <0 48 0>;
  204. };
  205. };
  206. pinctrl_0: pinctrl@11400000 {
  207. compatible = "samsung,exynos4415-pinctrl";
  208. reg = <0x11400000 0x1000>;
  209. interrupts = <0 240 0>;
  210. };
  211. fimd: fimd@11C00000 {
  212. compatible = "samsung,exynos4415-fimd";
  213. reg = <0x11C00000 0x30000>;
  214. interrupt-names = "fifo", "vsync", "lcd_sys";
  215. interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
  216. clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
  217. clock-names = "sclk_fimd", "fimd";
  218. samsung,power-domain = <&pd_lcd0>;
  219. iommus = <&sysmmu_fimd0>;
  220. samsung,sysreg = <&sysreg_system_controller>;
  221. status = "disabled";
  222. };
  223. dsi_0: dsi@11C80000 {
  224. compatible = "samsung,exynos4415-mipi-dsi";
  225. reg = <0x11C80000 0x10000>;
  226. interrupts = <0 83 0>;
  227. samsung,phy-type = <0>;
  228. samsung,power-domain = <&pd_lcd0>;
  229. phys = <&mipi_phy 1>;
  230. phy-names = "dsim";
  231. clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
  232. clock-names = "bus_clk", "pll_clk";
  233. #address-cells = <1>;
  234. #size-cells = <0>;
  235. status = "disabled";
  236. };
  237. sysmmu_fimd0: sysmmu@11E20000 {
  238. compatible = "samsung,exynos-sysmmu";
  239. reg = <0x11e20000 0x1000>;
  240. interrupts = <0 80 0>, <0 81 0>;
  241. clock-names = "sysmmu", "master";
  242. clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
  243. power-domains = <&pd_lcd0>;
  244. #iommu-cells = <0>;
  245. };
  246. hsotg: hsotg@12480000 {
  247. compatible = "samsung,s3c6400-hsotg";
  248. reg = <0x12480000 0x20000>;
  249. interrupts = <0 141 0>;
  250. clocks = <&cmu CLK_USBDEVICE>;
  251. clock-names = "otg";
  252. phys = <&exynos_usbphy 0>;
  253. phy-names = "usb2-phy";
  254. status = "disabled";
  255. };
  256. mshc_0: mshc@12510000 {
  257. compatible = "samsung,exynos5250-dw-mshc";
  258. reg = <0x12510000 0x1000>;
  259. interrupts = <0 142 0>;
  260. clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
  261. clock-names = "biu", "ciu";
  262. fifo-depth = <0x80>;
  263. #address-cells = <1>;
  264. #size-cells = <0>;
  265. status = "disabled";
  266. };
  267. mshc_1: mshc@12520000 {
  268. compatible = "samsung,exynos5250-dw-mshc";
  269. reg = <0x12520000 0x1000>;
  270. interrupts = <0 143 0>;
  271. clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
  272. clock-names = "biu", "ciu";
  273. fifo-depth = <0x80>;
  274. #address-cells = <1>;
  275. #size-cells = <0>;
  276. status = "disabled";
  277. };
  278. mshc_2: mshc@12530000 {
  279. compatible = "samsung,exynos5250-dw-mshc";
  280. reg = <0x12530000 0x1000>;
  281. interrupts = <0 144 0>;
  282. clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
  283. clock-names = "biu", "ciu";
  284. fifo-depth = <0x80>;
  285. #address-cells = <1>;
  286. #size-cells = <0>;
  287. status = "disabled";
  288. };
  289. ehci: ehci@12580000 {
  290. compatible = "samsung,exynos4210-ehci";
  291. reg = <0x12580000 0x100>;
  292. interrupts = <0 140 0>;
  293. clocks = <&cmu CLK_USBHOST>;
  294. clock-names = "usbhost";
  295. status = "disabled";
  296. #address-cells = <1>;
  297. #size-cells = <0>;
  298. port@0 {
  299. reg = <0>;
  300. phys = <&exynos_usbphy 1>;
  301. status = "disabled";
  302. };
  303. port@1 {
  304. reg = <1>;
  305. phys = <&exynos_usbphy 2>;
  306. status = "disabled";
  307. };
  308. port@2 {
  309. reg = <2>;
  310. phys = <&exynos_usbphy 3>;
  311. status = "disabled";
  312. };
  313. };
  314. ohci: ohci@12590000 {
  315. compatible = "samsung,exynos4210-ohci";
  316. reg = <0x12590000 0x100>;
  317. interrupts = <0 140 0>;
  318. clocks = <&cmu CLK_USBHOST>;
  319. clock-names = "usbhost";
  320. status = "disabled";
  321. #address-cells = <1>;
  322. #size-cells = <0>;
  323. port@0 {
  324. reg = <0>;
  325. phys = <&exynos_usbphy 1>;
  326. status = "disabled";
  327. };
  328. };
  329. exynos_usbphy: exynos-usbphy@125B0000 {
  330. compatible = "samsung,exynos4x12-usb2-phy";
  331. reg = <0x125B0000 0x100>;
  332. samsung,pmureg-phandle = <&pmu_system_controller>;
  333. samsung,sysreg-phandle = <&sysreg_system_controller>;
  334. clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>;
  335. clock-names = "phy", "ref";
  336. #phy-cells = <1>;
  337. status = "disabled";
  338. };
  339. amba {
  340. compatible = "simple-bus";
  341. #address-cells = <1>;
  342. #size-cells = <1>;
  343. interrupt-parent = <&gic>;
  344. ranges;
  345. pdma0: pdma@12680000 {
  346. compatible = "arm,pl330", "arm,primecell";
  347. reg = <0x12680000 0x1000>;
  348. interrupts = <0 138 0>;
  349. clocks = <&cmu CLK_PDMA0>;
  350. clock-names = "apb_pclk";
  351. #dma-cells = <1>;
  352. #dma-channels = <8>;
  353. #dma-requests = <32>;
  354. };
  355. pdma1: pdma@12690000 {
  356. compatible = "arm,pl330", "arm,primecell";
  357. reg = <0x12690000 0x1000>;
  358. interrupts = <0 139 0>;
  359. clocks = <&cmu CLK_PDMA1>;
  360. clock-names = "apb_pclk";
  361. #dma-cells = <1>;
  362. #dma-channels = <8>;
  363. #dma-requests = <32>;
  364. };
  365. };
  366. adc: adc@126C0000 {
  367. compatible = "samsung,exynos3250-adc",
  368. "samsung,exynos-adc-v2";
  369. reg = <0x126C0000 0x100>, <0x10020718 0x4>;
  370. interrupts = <0 137 0>;
  371. clock-names = "adc", "sclk";
  372. clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
  373. #io-channel-cells = <1>;
  374. io-channel-ranges;
  375. status = "disabled";
  376. };
  377. serial_0: serial@13800000 {
  378. compatible = "samsung,exynos4210-uart";
  379. reg = <0x13800000 0x100>;
  380. interrupts = <0 109 0>;
  381. clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
  382. clock-names = "uart", "clk_uart_baud0";
  383. status = "disabled";
  384. };
  385. serial_1: serial@13810000 {
  386. compatible = "samsung,exynos4210-uart";
  387. reg = <0x13810000 0x100>;
  388. interrupts = <0 110 0>;
  389. clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
  390. clock-names = "uart", "clk_uart_baud0";
  391. status = "disabled";
  392. };
  393. serial_2: serial@13820000 {
  394. compatible = "samsung,exynos4210-uart";
  395. reg = <0x13820000 0x100>;
  396. interrupts = <0 111 0>;
  397. clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
  398. clock-names = "uart", "clk_uart_baud0";
  399. status = "disabled";
  400. };
  401. serial_3: serial@13830000 {
  402. compatible = "samsung,exynos4210-uart";
  403. reg = <0x13830000 0x100>;
  404. interrupts = <0 112 0>;
  405. clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
  406. clock-names = "uart", "clk_uart_baud0";
  407. status = "disabled";
  408. };
  409. i2c_0: i2c@13860000 {
  410. #address-cells = <1>;
  411. #size-cells = <0>;
  412. compatible = "samsung,s3c2440-i2c";
  413. reg = <0x13860000 0x100>;
  414. interrupts = <0 113 0>;
  415. clocks = <&cmu CLK_I2C0>;
  416. clock-names = "i2c";
  417. pinctrl-names = "default";
  418. pinctrl-0 = <&i2c0_bus>;
  419. status = "disabled";
  420. };
  421. i2c_1: i2c@13870000 {
  422. #address-cells = <1>;
  423. #size-cells = <0>;
  424. compatible = "samsung,s3c2440-i2c";
  425. reg = <0x13870000 0x100>;
  426. interrupts = <0 114 0>;
  427. clocks = <&cmu CLK_I2C1>;
  428. clock-names = "i2c";
  429. pinctrl-names = "default";
  430. pinctrl-0 = <&i2c1_bus>;
  431. status = "disabled";
  432. };
  433. i2c_2: i2c@13880000 {
  434. #address-cells = <1>;
  435. #size-cells = <0>;
  436. compatible = "samsung,s3c2440-i2c";
  437. reg = <0x13880000 0x100>;
  438. interrupts = <0 115 0>;
  439. clocks = <&cmu CLK_I2C2>;
  440. clock-names = "i2c";
  441. pinctrl-names = "default";
  442. pinctrl-0 = <&i2c2_bus>;
  443. status = "disabled";
  444. };
  445. i2c_3: i2c@13890000 {
  446. #address-cells = <1>;
  447. #size-cells = <0>;
  448. compatible = "samsung,s3c2440-i2c";
  449. reg = <0x13890000 0x100>;
  450. interrupts = <0 116 0>;
  451. clocks = <&cmu CLK_I2C3>;
  452. clock-names = "i2c";
  453. pinctrl-names = "default";
  454. pinctrl-0 = <&i2c3_bus>;
  455. status = "disabled";
  456. };
  457. i2c_4: i2c@138A0000 {
  458. #address-cells = <1>;
  459. #size-cells = <0>;
  460. compatible = "samsung,s3c2440-i2c";
  461. reg = <0x138A0000 0x100>;
  462. interrupts = <0 117 0>;
  463. clocks = <&cmu CLK_I2C4>;
  464. clock-names = "i2c";
  465. pinctrl-names = "default";
  466. pinctrl-0 = <&i2c4_bus>;
  467. status = "disabled";
  468. };
  469. i2c_5: i2c@138B0000 {
  470. #address-cells = <1>;
  471. #size-cells = <0>;
  472. compatible = "samsung,s3c2440-i2c";
  473. reg = <0x138B0000 0x100>;
  474. interrupts = <0 118 0>;
  475. clocks = <&cmu CLK_I2C5>;
  476. clock-names = "i2c";
  477. pinctrl-names = "default";
  478. pinctrl-0 = <&i2c5_bus>;
  479. status = "disabled";
  480. };
  481. i2c_6: i2c@138C0000 {
  482. #address-cells = <1>;
  483. #size-cells = <0>;
  484. compatible = "samsung,s3c2440-i2c";
  485. reg = <0x138C0000 0x100>;
  486. interrupts = <0 119 0>;
  487. clocks = <&cmu CLK_I2C6>;
  488. clock-names = "i2c";
  489. pinctrl-names = "default";
  490. pinctrl-0 = <&i2c6_bus>;
  491. status = "disabled";
  492. };
  493. i2c_7: i2c@138D0000 {
  494. #address-cells = <1>;
  495. #size-cells = <0>;
  496. compatible = "samsung,s3c2440-i2c";
  497. reg = <0x138D0000 0x100>;
  498. interrupts = <0 120 0>;
  499. clocks = <&cmu CLK_I2C7>;
  500. clock-names = "i2c";
  501. pinctrl-names = "default";
  502. pinctrl-0 = <&i2c7_bus>;
  503. status = "disabled";
  504. };
  505. spi_0: spi@13920000 {
  506. compatible = "samsung,exynos4210-spi";
  507. reg = <0x13920000 0x100>;
  508. interrupts = <0 121 0>;
  509. dmas = <&pdma0 7>, <&pdma0 6>;
  510. dma-names = "tx", "rx";
  511. #address-cells = <1>;
  512. #size-cells = <0>;
  513. clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
  514. clock-names = "spi", "spi_busclk0";
  515. samsung,spi-src-clk = <0>;
  516. pinctrl-names = "default";
  517. pinctrl-0 = <&spi0_bus>;
  518. status = "disabled";
  519. };
  520. spi_1: spi@13930000 {
  521. compatible = "samsung,exynos4210-spi";
  522. reg = <0x13930000 0x100>;
  523. interrupts = <0 122 0>;
  524. dmas = <&pdma1 7>, <&pdma1 6>;
  525. dma-names = "tx", "rx";
  526. #address-cells = <1>;
  527. #size-cells = <0>;
  528. clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
  529. clock-names = "spi", "spi_busclk0";
  530. samsung,spi-src-clk = <0>;
  531. pinctrl-names = "default";
  532. pinctrl-0 = <&spi1_bus>;
  533. status = "disabled";
  534. };
  535. spi_2: spi@13940000 {
  536. compatible = "samsung,exynos4210-spi";
  537. reg = <0x13940000 0x100>;
  538. interrupts = <0 123 0>;
  539. dmas = <&pdma0 9>, <&pdma0 8>;
  540. dma-names = "tx", "rx";
  541. #address-cells = <1>;
  542. #size-cells = <0>;
  543. clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>;
  544. clock-names = "spi", "spi_busclk0";
  545. samsung,spi-src-clk = <0>;
  546. pinctrl-names = "default";
  547. pinctrl-0 = <&spi2_bus>;
  548. status = "disabled";
  549. };
  550. clock_audss: clock-controller@03810000 {
  551. compatible = "samsung,exynos4210-audss-clock";
  552. reg = <0x03810000 0x0C>;
  553. #clock-cells = <1>;
  554. };
  555. i2s0: i2s@3830000 {
  556. compatible = "samsung,s5pv210-i2s";
  557. reg = <0x03830000 0x100>;
  558. interrupts = <0 124 0>;
  559. clocks = <&clock_audss EXYNOS_I2S_BUS>,
  560. <&clock_audss EXYNOS_SCLK_I2S>;
  561. clock-names = "iis", "i2s_opclk0";
  562. dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>;
  563. dma-names = "tx", "rx", "tx-sec";
  564. pinctrl-names = "default";
  565. pinctrl-0 = <&i2s0_bus>;
  566. samsung,idma-addr = <0x03000000>;
  567. status = "disabled";
  568. };
  569. pwm: pwm@139D0000 {
  570. compatible = "samsung,exynos4210-pwm";
  571. reg = <0x139D0000 0x1000>;
  572. interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
  573. <0 107 0>, <0 108 0>;
  574. #pwm-cells = <3>;
  575. status = "disabled";
  576. };
  577. pmu {
  578. compatible = "arm,cortex-a9-pmu";
  579. interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
  580. };
  581. };
  582. };
  583. #include "exynos4415-pinctrl.dtsi"