exynos4212.dtsi 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134
  1. /*
  2. * Samsung's Exynos4212 SoC device tree source
  3. *
  4. * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212
  8. * based board files can include this file and provide values for board specfic
  9. * bindings.
  10. *
  11. * Note: This file does not include device nodes for all the controllers in
  12. * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional
  13. * nodes can be added to this file.
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License version 2 as
  17. * published by the Free Software Foundation.
  18. */
  19. #include "exynos4x12.dtsi"
  20. / {
  21. compatible = "samsung,exynos4212", "samsung,exynos4";
  22. cpus {
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. cpu0: cpu@A00 {
  26. device_type = "cpu";
  27. compatible = "arm,cortex-a9";
  28. reg = <0xA00>;
  29. clocks = <&clock CLK_ARM_CLK>;
  30. clock-names = "cpu";
  31. operating-points-v2 = <&cpu0_opp_table>;
  32. cooling-min-level = <13>;
  33. cooling-max-level = <7>;
  34. #cooling-cells = <2>; /* min followed by max */
  35. };
  36. cpu@A01 {
  37. device_type = "cpu";
  38. compatible = "arm,cortex-a9";
  39. reg = <0xA01>;
  40. operating-points-v2 = <&cpu0_opp_table>;
  41. };
  42. };
  43. cpu0_opp_table: opp_table0 {
  44. compatible = "operating-points-v2";
  45. opp-shared;
  46. opp00 {
  47. opp-hz = /bits/ 64 <200000000>;
  48. opp-microvolt = <900000>;
  49. clock-latency-ns = <200000>;
  50. };
  51. opp01 {
  52. opp-hz = /bits/ 64 <300000000>;
  53. opp-microvolt = <900000>;
  54. clock-latency-ns = <200000>;
  55. };
  56. opp02 {
  57. opp-hz = /bits/ 64 <400000000>;
  58. opp-microvolt = <925000>;
  59. clock-latency-ns = <200000>;
  60. };
  61. opp03 {
  62. opp-hz = /bits/ 64 <500000000>;
  63. opp-microvolt = <950000>;
  64. clock-latency-ns = <200000>;
  65. };
  66. opp04 {
  67. opp-hz = /bits/ 64 <600000000>;
  68. opp-microvolt = <975000>;
  69. clock-latency-ns = <200000>;
  70. };
  71. opp05 {
  72. opp-hz = /bits/ 64 <700000000>;
  73. opp-microvolt = <987500>;
  74. clock-latency-ns = <200000>;
  75. };
  76. opp06 {
  77. opp-hz = /bits/ 64 <800000000>;
  78. opp-microvolt = <1000000>;
  79. clock-latency-ns = <200000>;
  80. };
  81. opp07 {
  82. opp-hz = /bits/ 64 <900000000>;
  83. opp-microvolt = <1037500>;
  84. clock-latency-ns = <200000>;
  85. };
  86. opp08 {
  87. opp-hz = /bits/ 64 <1000000000>;
  88. opp-microvolt = <1087500>;
  89. clock-latency-ns = <200000>;
  90. };
  91. opp09 {
  92. opp-hz = /bits/ 64 <1100000000>;
  93. opp-microvolt = <1137500>;
  94. clock-latency-ns = <200000>;
  95. };
  96. opp10 {
  97. opp-hz = /bits/ 64 <1200000000>;
  98. opp-microvolt = <1187500>;
  99. clock-latency-ns = <200000>;
  100. };
  101. opp11 {
  102. opp-hz = /bits/ 64 <1300000000>;
  103. opp-microvolt = <1250000>;
  104. clock-latency-ns = <200000>;
  105. };
  106. opp12 {
  107. opp-hz = /bits/ 64 <1400000000>;
  108. opp-microvolt = <1287500>;
  109. clock-latency-ns = <200000>;
  110. };
  111. opp13 {
  112. opp-hz = /bits/ 64 <1500000000>;
  113. opp-microvolt = <1350000>;
  114. clock-latency-ns = <200000>;
  115. turbo-mode;
  116. };
  117. };
  118. };
  119. &combiner {
  120. samsung,combiner-nr = <18>;
  121. };
  122. &gic {
  123. cpu-offset = <0x8000>;
  124. };