exynos4210.dtsi 10 KB

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  1. /*
  2. * Samsung's Exynos4210 SoC device tree source
  3. *
  4. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. * Copyright (c) 2010-2011 Linaro Ltd.
  7. * www.linaro.org
  8. *
  9. * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
  10. * based board files can include this file and provide values for board specfic
  11. * bindings.
  12. *
  13. * Note: This file does not include device nodes for all the controllers in
  14. * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
  15. * nodes can be added to this file.
  16. *
  17. * This program is free software; you can redistribute it and/or modify
  18. * it under the terms of the GNU General Public License version 2 as
  19. * published by the Free Software Foundation.
  20. */
  21. #include "exynos4.dtsi"
  22. #include "exynos4210-pinctrl.dtsi"
  23. #include "exynos4-cpu-thermal.dtsi"
  24. / {
  25. compatible = "samsung,exynos4210", "samsung,exynos4";
  26. aliases {
  27. pinctrl0 = &pinctrl_0;
  28. pinctrl1 = &pinctrl_1;
  29. pinctrl2 = &pinctrl_2;
  30. };
  31. cpus {
  32. #address-cells = <1>;
  33. #size-cells = <0>;
  34. cpu0: cpu@900 {
  35. device_type = "cpu";
  36. compatible = "arm,cortex-a9";
  37. reg = <0x900>;
  38. clocks = <&clock CLK_ARM_CLK>;
  39. clock-names = "cpu";
  40. clock-latency = <160000>;
  41. operating-points = <
  42. 1200000 1250000
  43. 1000000 1150000
  44. 800000 1075000
  45. 500000 975000
  46. 400000 975000
  47. 200000 950000
  48. >;
  49. cooling-min-level = <4>;
  50. cooling-max-level = <2>;
  51. #cooling-cells = <2>; /* min followed by max */
  52. };
  53. cpu@901 {
  54. device_type = "cpu";
  55. compatible = "arm,cortex-a9";
  56. reg = <0x901>;
  57. };
  58. };
  59. sysram: sysram@02020000 {
  60. compatible = "mmio-sram";
  61. reg = <0x02020000 0x20000>;
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. ranges = <0 0x02020000 0x20000>;
  65. smp-sysram@0 {
  66. compatible = "samsung,exynos4210-sysram";
  67. reg = <0x0 0x1000>;
  68. };
  69. smp-sysram@1f000 {
  70. compatible = "samsung,exynos4210-sysram-ns";
  71. reg = <0x1f000 0x1000>;
  72. };
  73. };
  74. pd_lcd1: lcd1-power-domain@10023CA0 {
  75. compatible = "samsung,exynos4210-pd";
  76. reg = <0x10023CA0 0x20>;
  77. #power-domain-cells = <0>;
  78. };
  79. l2c: l2-cache-controller@10502000 {
  80. compatible = "arm,pl310-cache";
  81. reg = <0x10502000 0x1000>;
  82. cache-unified;
  83. cache-level = <2>;
  84. arm,tag-latency = <2 2 1>;
  85. arm,data-latency = <2 2 1>;
  86. };
  87. mct: mct@10050000 {
  88. compatible = "samsung,exynos4210-mct";
  89. reg = <0x10050000 0x800>;
  90. interrupt-parent = <&mct_map>;
  91. interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
  92. clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
  93. clock-names = "fin_pll", "mct";
  94. mct_map: mct-map {
  95. #interrupt-cells = <1>;
  96. #address-cells = <0>;
  97. #size-cells = <0>;
  98. interrupt-map = <0 &gic 0 57 0>,
  99. <1 &gic 0 69 0>,
  100. <2 &combiner 12 6>,
  101. <3 &combiner 12 7>,
  102. <4 &gic 0 42 0>,
  103. <5 &gic 0 48 0>;
  104. };
  105. };
  106. clock: clock-controller@10030000 {
  107. compatible = "samsung,exynos4210-clock";
  108. reg = <0x10030000 0x20000>;
  109. #clock-cells = <1>;
  110. };
  111. pinctrl_0: pinctrl@11400000 {
  112. compatible = "samsung,exynos4210-pinctrl";
  113. reg = <0x11400000 0x1000>;
  114. interrupts = <0 47 0>;
  115. };
  116. pinctrl_1: pinctrl@11000000 {
  117. compatible = "samsung,exynos4210-pinctrl";
  118. reg = <0x11000000 0x1000>;
  119. interrupts = <0 46 0>;
  120. wakup_eint: wakeup-interrupt-controller {
  121. compatible = "samsung,exynos4210-wakeup-eint";
  122. interrupt-parent = <&gic>;
  123. interrupts = <0 32 0>;
  124. };
  125. };
  126. pinctrl_2: pinctrl@03860000 {
  127. compatible = "samsung,exynos4210-pinctrl";
  128. reg = <0x03860000 0x1000>;
  129. };
  130. tmu: tmu@100C0000 {
  131. compatible = "samsung,exynos4210-tmu";
  132. interrupt-parent = <&combiner>;
  133. reg = <0x100C0000 0x100>;
  134. interrupts = <2 4>;
  135. clocks = <&clock CLK_TMU_APBIF>;
  136. clock-names = "tmu_apbif";
  137. samsung,tmu_gain = <15>;
  138. samsung,tmu_reference_voltage = <7>;
  139. status = "disabled";
  140. };
  141. thermal-zones {
  142. cpu_thermal: cpu-thermal {
  143. polling-delay-passive = <0>;
  144. polling-delay = <0>;
  145. thermal-sensors = <&tmu 0>;
  146. trips {
  147. cpu_alert0: cpu-alert-0 {
  148. temperature = <85000>; /* millicelsius */
  149. };
  150. cpu_alert1: cpu-alert-1 {
  151. temperature = <100000>; /* millicelsius */
  152. };
  153. cpu_alert2: cpu-alert-2 {
  154. temperature = <110000>; /* millicelsius */
  155. };
  156. };
  157. };
  158. };
  159. g2d: g2d@12800000 {
  160. compatible = "samsung,s5pv210-g2d";
  161. reg = <0x12800000 0x1000>;
  162. interrupts = <0 89 0>;
  163. clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
  164. clock-names = "sclk_fimg2d", "fimg2d";
  165. power-domains = <&pd_lcd0>;
  166. iommus = <&sysmmu_g2d>;
  167. };
  168. camera {
  169. clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
  170. <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
  171. clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
  172. fimc_0: fimc@11800000 {
  173. samsung,pix-limits = <4224 8192 1920 4224>;
  174. samsung,mainscaler-ext;
  175. samsung,cam-if;
  176. };
  177. fimc_1: fimc@11810000 {
  178. samsung,pix-limits = <4224 8192 1920 4224>;
  179. samsung,mainscaler-ext;
  180. samsung,cam-if;
  181. };
  182. fimc_2: fimc@11820000 {
  183. samsung,pix-limits = <4224 8192 1920 4224>;
  184. samsung,mainscaler-ext;
  185. samsung,lcd-wb;
  186. };
  187. fimc_3: fimc@11830000 {
  188. samsung,pix-limits = <1920 8192 1366 1920>;
  189. samsung,rotators = <0>;
  190. samsung,mainscaler-ext;
  191. samsung,lcd-wb;
  192. };
  193. };
  194. mixer: mixer@12C10000 {
  195. clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
  196. "sclk_mixer";
  197. clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
  198. <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
  199. <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
  200. };
  201. ppmu_lcd1: ppmu_lcd1@12240000 {
  202. compatible = "samsung,exynos-ppmu";
  203. reg = <0x12240000 0x2000>;
  204. clocks = <&clock CLK_PPMULCD1>;
  205. clock-names = "ppmu";
  206. status = "disabled";
  207. };
  208. sysmmu_g2d: sysmmu@12A20000 {
  209. compatible = "samsung,exynos-sysmmu";
  210. reg = <0x12A20000 0x1000>;
  211. interrupt-parent = <&combiner>;
  212. interrupts = <4 7>;
  213. clock-names = "sysmmu", "master";
  214. clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
  215. power-domains = <&pd_lcd0>;
  216. #iommu-cells = <0>;
  217. };
  218. sysmmu_fimd1: sysmmu@12220000 {
  219. compatible = "samsung,exynos-sysmmu";
  220. interrupt-parent = <&combiner>;
  221. reg = <0x12220000 0x1000>;
  222. interrupts = <5 3>;
  223. clock-names = "sysmmu", "master";
  224. clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
  225. power-domains = <&pd_lcd1>;
  226. #iommu-cells = <0>;
  227. };
  228. bus_dmc: bus_dmc {
  229. compatible = "samsung,exynos-bus";
  230. clocks = <&clock CLK_DIV_DMC>;
  231. clock-names = "bus";
  232. operating-points-v2 = <&bus_dmc_opp_table>;
  233. status = "disabled";
  234. };
  235. bus_acp: bus_acp {
  236. compatible = "samsung,exynos-bus";
  237. clocks = <&clock CLK_DIV_ACP>;
  238. clock-names = "bus";
  239. operating-points-v2 = <&bus_acp_opp_table>;
  240. status = "disabled";
  241. };
  242. bus_peri: bus_peri {
  243. compatible = "samsung,exynos-bus";
  244. clocks = <&clock CLK_ACLK100>;
  245. clock-names = "bus";
  246. operating-points-v2 = <&bus_peri_opp_table>;
  247. status = "disabled";
  248. };
  249. bus_fsys: bus_fsys {
  250. compatible = "samsung,exynos-bus";
  251. clocks = <&clock CLK_ACLK133>;
  252. clock-names = "bus";
  253. operating-points-v2 = <&bus_fsys_opp_table>;
  254. status = "disabled";
  255. };
  256. bus_display: bus_display {
  257. compatible = "samsung,exynos-bus";
  258. clocks = <&clock CLK_ACLK160>;
  259. clock-names = "bus";
  260. operating-points-v2 = <&bus_display_opp_table>;
  261. status = "disabled";
  262. };
  263. bus_lcd0: bus_lcd0 {
  264. compatible = "samsung,exynos-bus";
  265. clocks = <&clock CLK_ACLK200>;
  266. clock-names = "bus";
  267. operating-points-v2 = <&bus_leftbus_opp_table>;
  268. status = "disabled";
  269. };
  270. bus_leftbus: bus_leftbus {
  271. compatible = "samsung,exynos-bus";
  272. clocks = <&clock CLK_DIV_GDL>;
  273. clock-names = "bus";
  274. operating-points-v2 = <&bus_leftbus_opp_table>;
  275. status = "disabled";
  276. };
  277. bus_rightbus: bus_rightbus {
  278. compatible = "samsung,exynos-bus";
  279. clocks = <&clock CLK_DIV_GDR>;
  280. clock-names = "bus";
  281. operating-points-v2 = <&bus_leftbus_opp_table>;
  282. status = "disabled";
  283. };
  284. bus_mfc: bus_mfc {
  285. compatible = "samsung,exynos-bus";
  286. clocks = <&clock CLK_SCLK_MFC>;
  287. clock-names = "bus";
  288. operating-points-v2 = <&bus_leftbus_opp_table>;
  289. status = "disabled";
  290. };
  291. bus_dmc_opp_table: opp_table1 {
  292. compatible = "operating-points-v2";
  293. opp-shared;
  294. opp@134000000 {
  295. opp-hz = /bits/ 64 <134000000>;
  296. opp-microvolt = <1025000>;
  297. };
  298. opp@267000000 {
  299. opp-hz = /bits/ 64 <267000000>;
  300. opp-microvolt = <1050000>;
  301. };
  302. opp@400000000 {
  303. opp-hz = /bits/ 64 <400000000>;
  304. opp-microvolt = <1150000>;
  305. };
  306. };
  307. bus_acp_opp_table: opp_table2 {
  308. compatible = "operating-points-v2";
  309. opp-shared;
  310. opp@134000000 {
  311. opp-hz = /bits/ 64 <134000000>;
  312. };
  313. opp@160000000 {
  314. opp-hz = /bits/ 64 <160000000>;
  315. };
  316. opp@200000000 {
  317. opp-hz = /bits/ 64 <200000000>;
  318. };
  319. };
  320. bus_peri_opp_table: opp_table3 {
  321. compatible = "operating-points-v2";
  322. opp-shared;
  323. opp@5000000 {
  324. opp-hz = /bits/ 64 <5000000>;
  325. };
  326. opp@100000000 {
  327. opp-hz = /bits/ 64 <100000000>;
  328. };
  329. };
  330. bus_fsys_opp_table: opp_table4 {
  331. compatible = "operating-points-v2";
  332. opp-shared;
  333. opp@10000000 {
  334. opp-hz = /bits/ 64 <10000000>;
  335. };
  336. opp@134000000 {
  337. opp-hz = /bits/ 64 <134000000>;
  338. };
  339. };
  340. bus_display_opp_table: opp_table5 {
  341. compatible = "operating-points-v2";
  342. opp-shared;
  343. opp@100000000 {
  344. opp-hz = /bits/ 64 <100000000>;
  345. };
  346. opp@134000000 {
  347. opp-hz = /bits/ 64 <134000000>;
  348. };
  349. opp@160000000 {
  350. opp-hz = /bits/ 64 <160000000>;
  351. };
  352. };
  353. bus_leftbus_opp_table: opp_table6 {
  354. compatible = "operating-points-v2";
  355. opp-shared;
  356. opp@100000000 {
  357. opp-hz = /bits/ 64 <100000000>;
  358. };
  359. opp@160000000 {
  360. opp-hz = /bits/ 64 <160000000>;
  361. };
  362. opp@200000000 {
  363. opp-hz = /bits/ 64 <200000000>;
  364. };
  365. };
  366. };
  367. &gic {
  368. cpu-offset = <0x8000>;
  369. };
  370. &combiner {
  371. samsung,combiner-nr = <16>;
  372. interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  373. <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
  374. <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
  375. <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
  376. };
  377. &mdma1 {
  378. power-domains = <&pd_lcd0>;
  379. };
  380. &pmu_system_controller {
  381. clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
  382. "clkout4", "clkout8", "clkout9";
  383. clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
  384. <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
  385. <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
  386. #clock-cells = <1>;
  387. };
  388. &rotator {
  389. power-domains = <&pd_lcd0>;
  390. };
  391. &sysmmu_rotator {
  392. power-domains = <&pd_lcd0>;
  393. };