exynos3250.dtsi 21 KB

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  1. /*
  2. * Samsung's Exynos3250 SoC device tree source
  3. *
  4. * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
  8. * based board files can include this file and provide values for board specfic
  9. * bindings.
  10. *
  11. * Note: This file does not include device nodes for all the controllers in
  12. * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  13. * nodes can be added to this file.
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License version 2 as
  17. * published by the Free Software Foundation.
  18. */
  19. #include "exynos4-cpu-thermal.dtsi"
  20. #include "exynos-syscon-restart.dtsi"
  21. #include <dt-bindings/clock/exynos3250.h>
  22. / {
  23. compatible = "samsung,exynos3250";
  24. interrupt-parent = <&gic>;
  25. #address-cells = <1>;
  26. #size-cells = <1>;
  27. aliases {
  28. pinctrl0 = &pinctrl_0;
  29. pinctrl1 = &pinctrl_1;
  30. mshc0 = &mshc_0;
  31. mshc1 = &mshc_1;
  32. mshc2 = &mshc_2;
  33. spi0 = &spi_0;
  34. spi1 = &spi_1;
  35. i2c0 = &i2c_0;
  36. i2c1 = &i2c_1;
  37. i2c2 = &i2c_2;
  38. i2c3 = &i2c_3;
  39. i2c4 = &i2c_4;
  40. i2c5 = &i2c_5;
  41. i2c6 = &i2c_6;
  42. i2c7 = &i2c_7;
  43. serial0 = &serial_0;
  44. serial1 = &serial_1;
  45. serial2 = &serial_2;
  46. };
  47. cpus {
  48. #address-cells = <1>;
  49. #size-cells = <0>;
  50. cpu0: cpu@0 {
  51. device_type = "cpu";
  52. compatible = "arm,cortex-a7";
  53. reg = <0>;
  54. clock-frequency = <1000000000>;
  55. clocks = <&cmu CLK_ARM_CLK>;
  56. clock-names = "cpu";
  57. #cooling-cells = <2>;
  58. operating-points = <
  59. 1000000 1150000
  60. 900000 1112500
  61. 800000 1075000
  62. 700000 1037500
  63. 600000 1000000
  64. 500000 962500
  65. 400000 925000
  66. 300000 887500
  67. 200000 850000
  68. 100000 850000
  69. >;
  70. };
  71. cpu1: cpu@1 {
  72. device_type = "cpu";
  73. compatible = "arm,cortex-a7";
  74. reg = <1>;
  75. clock-frequency = <1000000000>;
  76. };
  77. };
  78. soc: soc {
  79. compatible = "simple-bus";
  80. #address-cells = <1>;
  81. #size-cells = <1>;
  82. ranges;
  83. fixed-rate-clocks {
  84. #address-cells = <1>;
  85. #size-cells = <0>;
  86. xusbxti: clock@0 {
  87. compatible = "fixed-clock";
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. reg = <0>;
  91. clock-frequency = <0>;
  92. #clock-cells = <0>;
  93. clock-output-names = "xusbxti";
  94. };
  95. xxti: clock@1 {
  96. compatible = "fixed-clock";
  97. reg = <1>;
  98. clock-frequency = <0>;
  99. #clock-cells = <0>;
  100. clock-output-names = "xxti";
  101. };
  102. xtcxo: clock@2 {
  103. compatible = "fixed-clock";
  104. reg = <2>;
  105. clock-frequency = <0>;
  106. #clock-cells = <0>;
  107. clock-output-names = "xtcxo";
  108. };
  109. };
  110. sysram@02020000 {
  111. compatible = "mmio-sram";
  112. reg = <0x02020000 0x40000>;
  113. #address-cells = <1>;
  114. #size-cells = <1>;
  115. ranges = <0 0x02020000 0x40000>;
  116. smp-sysram@0 {
  117. compatible = "samsung,exynos4210-sysram";
  118. reg = <0x0 0x1000>;
  119. };
  120. smp-sysram@3f000 {
  121. compatible = "samsung,exynos4210-sysram-ns";
  122. reg = <0x3f000 0x1000>;
  123. };
  124. };
  125. chipid@10000000 {
  126. compatible = "samsung,exynos4210-chipid";
  127. reg = <0x10000000 0x100>;
  128. };
  129. sys_reg: syscon@10010000 {
  130. compatible = "samsung,exynos3-sysreg", "syscon";
  131. reg = <0x10010000 0x400>;
  132. };
  133. pmu_system_controller: system-controller@10020000 {
  134. compatible = "samsung,exynos3250-pmu", "syscon";
  135. reg = <0x10020000 0x4000>;
  136. interrupt-controller;
  137. #interrupt-cells = <3>;
  138. interrupt-parent = <&gic>;
  139. };
  140. mipi_phy: video-phy {
  141. compatible = "samsung,s5pv210-mipi-video-phy";
  142. #phy-cells = <1>;
  143. syscon = <&pmu_system_controller>;
  144. };
  145. pd_cam: cam-power-domain@10023C00 {
  146. compatible = "samsung,exynos4210-pd";
  147. reg = <0x10023C00 0x20>;
  148. #power-domain-cells = <0>;
  149. };
  150. pd_mfc: mfc-power-domain@10023C40 {
  151. compatible = "samsung,exynos4210-pd";
  152. reg = <0x10023C40 0x20>;
  153. #power-domain-cells = <0>;
  154. };
  155. pd_g3d: g3d-power-domain@10023C60 {
  156. compatible = "samsung,exynos4210-pd";
  157. reg = <0x10023C60 0x20>;
  158. #power-domain-cells = <0>;
  159. };
  160. pd_lcd0: lcd0-power-domain@10023C80 {
  161. compatible = "samsung,exynos4210-pd";
  162. reg = <0x10023C80 0x20>;
  163. #power-domain-cells = <0>;
  164. };
  165. pd_isp: isp-power-domain@10023CA0 {
  166. compatible = "samsung,exynos4210-pd";
  167. reg = <0x10023CA0 0x20>;
  168. #power-domain-cells = <0>;
  169. };
  170. cmu: clock-controller@10030000 {
  171. compatible = "samsung,exynos3250-cmu";
  172. reg = <0x10030000 0x20000>;
  173. #clock-cells = <1>;
  174. assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
  175. <&cmu CLK_MOUT_ACLK_266_SUB>;
  176. assigned-clock-parents = <&cmu CLK_FIN_PLL>,
  177. <&cmu CLK_FIN_PLL>;
  178. };
  179. cmu_dmc: clock-controller@105C0000 {
  180. compatible = "samsung,exynos3250-cmu-dmc";
  181. reg = <0x105C0000 0x2000>;
  182. #clock-cells = <1>;
  183. };
  184. rtc: rtc@10070000 {
  185. compatible = "samsung,s3c6410-rtc";
  186. reg = <0x10070000 0x100>;
  187. interrupts = <0 73 0>, <0 74 0>;
  188. interrupt-parent = <&pmu_system_controller>;
  189. status = "disabled";
  190. };
  191. tmu: tmu@100C0000 {
  192. compatible = "samsung,exynos3250-tmu";
  193. reg = <0x100C0000 0x100>;
  194. interrupts = <0 216 0>;
  195. clocks = <&cmu CLK_TMU_APBIF>;
  196. clock-names = "tmu_apbif";
  197. #include "exynos4412-tmu-sensor-conf.dtsi"
  198. status = "disabled";
  199. };
  200. gic: interrupt-controller@10481000 {
  201. compatible = "arm,cortex-a15-gic";
  202. #interrupt-cells = <3>;
  203. interrupt-controller;
  204. reg = <0x10481000 0x1000>,
  205. <0x10482000 0x1000>,
  206. <0x10484000 0x2000>,
  207. <0x10486000 0x2000>;
  208. interrupts = <1 9 0xf04>;
  209. };
  210. mct@10050000 {
  211. compatible = "samsung,exynos4210-mct";
  212. reg = <0x10050000 0x800>;
  213. interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
  214. <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
  215. clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
  216. clock-names = "fin_pll", "mct";
  217. };
  218. pinctrl_1: pinctrl@11000000 {
  219. compatible = "samsung,exynos3250-pinctrl";
  220. reg = <0x11000000 0x1000>;
  221. interrupts = <0 225 0>;
  222. wakeup-interrupt-controller {
  223. compatible = "samsung,exynos4210-wakeup-eint";
  224. interrupts = <0 48 0>;
  225. };
  226. };
  227. pinctrl_0: pinctrl@11400000 {
  228. compatible = "samsung,exynos3250-pinctrl";
  229. reg = <0x11400000 0x1000>;
  230. interrupts = <0 240 0>;
  231. };
  232. jpeg: codec@11830000 {
  233. compatible = "samsung,exynos3250-jpeg";
  234. reg = <0x11830000 0x1000>;
  235. interrupts = <0 171 0>;
  236. clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
  237. clock-names = "jpeg", "sclk";
  238. power-domains = <&pd_cam>;
  239. assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
  240. assigned-clock-rates = <0>, <150000000>;
  241. assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
  242. iommus = <&sysmmu_jpeg>;
  243. status = "disabled";
  244. };
  245. sysmmu_jpeg: sysmmu@11A60000 {
  246. compatible = "samsung,exynos-sysmmu";
  247. reg = <0x11a60000 0x1000>;
  248. interrupts = <0 156 0>, <0 161 0>;
  249. clock-names = "sysmmu", "master";
  250. clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
  251. power-domains = <&pd_cam>;
  252. #iommu-cells = <0>;
  253. };
  254. fimd: fimd@11c00000 {
  255. compatible = "samsung,exynos3250-fimd";
  256. reg = <0x11c00000 0x30000>;
  257. interrupt-names = "fifo", "vsync", "lcd_sys";
  258. interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
  259. clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
  260. clock-names = "sclk_fimd", "fimd";
  261. power-domains = <&pd_lcd0>;
  262. iommus = <&sysmmu_fimd0>;
  263. samsung,sysreg = <&sys_reg>;
  264. status = "disabled";
  265. };
  266. dsi_0: dsi@11C80000 {
  267. compatible = "samsung,exynos3250-mipi-dsi";
  268. reg = <0x11C80000 0x10000>;
  269. interrupts = <0 83 0>;
  270. samsung,phy-type = <0>;
  271. power-domains = <&pd_lcd0>;
  272. phys = <&mipi_phy 1>;
  273. phy-names = "dsim";
  274. clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
  275. clock-names = "bus_clk", "pll_clk";
  276. #address-cells = <1>;
  277. #size-cells = <0>;
  278. status = "disabled";
  279. };
  280. sysmmu_fimd0: sysmmu@11E20000 {
  281. compatible = "samsung,exynos-sysmmu";
  282. reg = <0x11e20000 0x1000>;
  283. interrupts = <0 80 0>, <0 81 0>;
  284. clock-names = "sysmmu", "master";
  285. clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
  286. power-domains = <&pd_lcd0>;
  287. #iommu-cells = <0>;
  288. };
  289. hsotg: hsotg@12480000 {
  290. compatible = "snps,dwc2";
  291. reg = <0x12480000 0x20000>;
  292. interrupts = <0 141 0>;
  293. clocks = <&cmu CLK_USBOTG>;
  294. clock-names = "otg";
  295. phys = <&exynos_usbphy 0>;
  296. phy-names = "usb2-phy";
  297. status = "disabled";
  298. };
  299. mshc_0: mshc@12510000 {
  300. compatible = "samsung,exynos5420-dw-mshc";
  301. reg = <0x12510000 0x1000>;
  302. interrupts = <0 142 0>;
  303. clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
  304. clock-names = "biu", "ciu";
  305. fifo-depth = <0x80>;
  306. #address-cells = <1>;
  307. #size-cells = <0>;
  308. status = "disabled";
  309. };
  310. mshc_1: mshc@12520000 {
  311. compatible = "samsung,exynos5420-dw-mshc";
  312. reg = <0x12520000 0x1000>;
  313. interrupts = <0 143 0>;
  314. clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
  315. clock-names = "biu", "ciu";
  316. fifo-depth = <0x80>;
  317. #address-cells = <1>;
  318. #size-cells = <0>;
  319. status = "disabled";
  320. };
  321. mshc_2: mshc@12530000 {
  322. compatible = "samsung,exynos5250-dw-mshc";
  323. reg = <0x12530000 0x1000>;
  324. interrupts = <0 144 0>;
  325. clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
  326. clock-names = "biu", "ciu";
  327. fifo-depth = <0x80>;
  328. #address-cells = <1>;
  329. #size-cells = <0>;
  330. status = "disabled";
  331. };
  332. exynos_usbphy: exynos-usbphy@125B0000 {
  333. compatible = "samsung,exynos3250-usb2-phy";
  334. reg = <0x125B0000 0x100>;
  335. samsung,pmureg-phandle = <&pmu_system_controller>;
  336. clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
  337. clock-names = "phy", "ref";
  338. #phy-cells = <1>;
  339. status = "disabled";
  340. };
  341. amba {
  342. compatible = "simple-bus";
  343. #address-cells = <1>;
  344. #size-cells = <1>;
  345. ranges;
  346. pdma0: pdma@12680000 {
  347. compatible = "arm,pl330", "arm,primecell";
  348. reg = <0x12680000 0x1000>;
  349. interrupts = <0 138 0>;
  350. clocks = <&cmu CLK_PDMA0>;
  351. clock-names = "apb_pclk";
  352. #dma-cells = <1>;
  353. #dma-channels = <8>;
  354. #dma-requests = <32>;
  355. };
  356. pdma1: pdma@12690000 {
  357. compatible = "arm,pl330", "arm,primecell";
  358. reg = <0x12690000 0x1000>;
  359. interrupts = <0 139 0>;
  360. clocks = <&cmu CLK_PDMA1>;
  361. clock-names = "apb_pclk";
  362. #dma-cells = <1>;
  363. #dma-channels = <8>;
  364. #dma-requests = <32>;
  365. };
  366. };
  367. adc: adc@126C0000 {
  368. compatible = "samsung,exynos3250-adc",
  369. "samsung,exynos-adc-v2";
  370. reg = <0x126C0000 0x100>;
  371. interrupts = <0 137 0>;
  372. clock-names = "adc", "sclk";
  373. clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
  374. #io-channel-cells = <1>;
  375. io-channel-ranges;
  376. samsung,syscon-phandle = <&pmu_system_controller>;
  377. status = "disabled";
  378. };
  379. mfc: codec@13400000 {
  380. compatible = "samsung,mfc-v7";
  381. reg = <0x13400000 0x10000>;
  382. interrupts = <0 102 0>;
  383. clock-names = "mfc", "sclk_mfc";
  384. clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
  385. power-domains = <&pd_mfc>;
  386. iommus = <&sysmmu_mfc>;
  387. };
  388. sysmmu_mfc: sysmmu@13620000 {
  389. compatible = "samsung,exynos-sysmmu";
  390. reg = <0x13620000 0x1000>;
  391. interrupts = <0 96 0>, <0 98 0>;
  392. clock-names = "sysmmu", "master";
  393. clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
  394. power-domains = <&pd_mfc>;
  395. #iommu-cells = <0>;
  396. };
  397. serial_0: serial@13800000 {
  398. compatible = "samsung,exynos4210-uart";
  399. reg = <0x13800000 0x100>;
  400. interrupts = <0 109 0>;
  401. clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
  402. clock-names = "uart", "clk_uart_baud0";
  403. pinctrl-names = "default";
  404. pinctrl-0 = <&uart0_data &uart0_fctl>;
  405. status = "disabled";
  406. };
  407. serial_1: serial@13810000 {
  408. compatible = "samsung,exynos4210-uart";
  409. reg = <0x13810000 0x100>;
  410. interrupts = <0 110 0>;
  411. clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
  412. clock-names = "uart", "clk_uart_baud0";
  413. pinctrl-names = "default";
  414. pinctrl-0 = <&uart1_data>;
  415. status = "disabled";
  416. };
  417. serial_2: serial@13820000 {
  418. compatible = "samsung,exynos4210-uart";
  419. reg = <0x13820000 0x100>;
  420. interrupts = <0 111 0>;
  421. clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
  422. clock-names = "uart", "clk_uart_baud0";
  423. pinctrl-names = "default";
  424. pinctrl-0 = <&uart2_data>;
  425. status = "disabled";
  426. };
  427. i2c_0: i2c@13860000 {
  428. #address-cells = <1>;
  429. #size-cells = <0>;
  430. compatible = "samsung,s3c2440-i2c";
  431. reg = <0x13860000 0x100>;
  432. interrupts = <0 113 0>;
  433. clocks = <&cmu CLK_I2C0>;
  434. clock-names = "i2c";
  435. pinctrl-names = "default";
  436. pinctrl-0 = <&i2c0_bus>;
  437. status = "disabled";
  438. };
  439. i2c_1: i2c@13870000 {
  440. #address-cells = <1>;
  441. #size-cells = <0>;
  442. compatible = "samsung,s3c2440-i2c";
  443. reg = <0x13870000 0x100>;
  444. interrupts = <0 114 0>;
  445. clocks = <&cmu CLK_I2C1>;
  446. clock-names = "i2c";
  447. pinctrl-names = "default";
  448. pinctrl-0 = <&i2c1_bus>;
  449. status = "disabled";
  450. };
  451. i2c_2: i2c@13880000 {
  452. #address-cells = <1>;
  453. #size-cells = <0>;
  454. compatible = "samsung,s3c2440-i2c";
  455. reg = <0x13880000 0x100>;
  456. interrupts = <0 115 0>;
  457. clocks = <&cmu CLK_I2C2>;
  458. clock-names = "i2c";
  459. pinctrl-names = "default";
  460. pinctrl-0 = <&i2c2_bus>;
  461. status = "disabled";
  462. };
  463. i2c_3: i2c@13890000 {
  464. #address-cells = <1>;
  465. #size-cells = <0>;
  466. compatible = "samsung,s3c2440-i2c";
  467. reg = <0x13890000 0x100>;
  468. interrupts = <0 116 0>;
  469. clocks = <&cmu CLK_I2C3>;
  470. clock-names = "i2c";
  471. pinctrl-names = "default";
  472. pinctrl-0 = <&i2c3_bus>;
  473. status = "disabled";
  474. };
  475. i2c_4: i2c@138A0000 {
  476. #address-cells = <1>;
  477. #size-cells = <0>;
  478. compatible = "samsung,s3c2440-i2c";
  479. reg = <0x138A0000 0x100>;
  480. interrupts = <0 117 0>;
  481. clocks = <&cmu CLK_I2C4>;
  482. clock-names = "i2c";
  483. pinctrl-names = "default";
  484. pinctrl-0 = <&i2c4_bus>;
  485. status = "disabled";
  486. };
  487. i2c_5: i2c@138B0000 {
  488. #address-cells = <1>;
  489. #size-cells = <0>;
  490. compatible = "samsung,s3c2440-i2c";
  491. reg = <0x138B0000 0x100>;
  492. interrupts = <0 118 0>;
  493. clocks = <&cmu CLK_I2C5>;
  494. clock-names = "i2c";
  495. pinctrl-names = "default";
  496. pinctrl-0 = <&i2c5_bus>;
  497. status = "disabled";
  498. };
  499. i2c_6: i2c@138C0000 {
  500. #address-cells = <1>;
  501. #size-cells = <0>;
  502. compatible = "samsung,s3c2440-i2c";
  503. reg = <0x138C0000 0x100>;
  504. interrupts = <0 119 0>;
  505. clocks = <&cmu CLK_I2C6>;
  506. clock-names = "i2c";
  507. pinctrl-names = "default";
  508. pinctrl-0 = <&i2c6_bus>;
  509. status = "disabled";
  510. };
  511. i2c_7: i2c@138D0000 {
  512. #address-cells = <1>;
  513. #size-cells = <0>;
  514. compatible = "samsung,s3c2440-i2c";
  515. reg = <0x138D0000 0x100>;
  516. interrupts = <0 120 0>;
  517. clocks = <&cmu CLK_I2C7>;
  518. clock-names = "i2c";
  519. pinctrl-names = "default";
  520. pinctrl-0 = <&i2c7_bus>;
  521. status = "disabled";
  522. };
  523. spi_0: spi@13920000 {
  524. compatible = "samsung,exynos4210-spi";
  525. reg = <0x13920000 0x100>;
  526. interrupts = <0 121 0>;
  527. dmas = <&pdma0 7>, <&pdma0 6>;
  528. dma-names = "tx", "rx";
  529. #address-cells = <1>;
  530. #size-cells = <0>;
  531. clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
  532. clock-names = "spi", "spi_busclk0";
  533. samsung,spi-src-clk = <0>;
  534. pinctrl-names = "default";
  535. pinctrl-0 = <&spi0_bus>;
  536. status = "disabled";
  537. };
  538. spi_1: spi@13930000 {
  539. compatible = "samsung,exynos4210-spi";
  540. reg = <0x13930000 0x100>;
  541. interrupts = <0 122 0>;
  542. dmas = <&pdma1 7>, <&pdma1 6>;
  543. dma-names = "tx", "rx";
  544. #address-cells = <1>;
  545. #size-cells = <0>;
  546. clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
  547. clock-names = "spi", "spi_busclk0";
  548. samsung,spi-src-clk = <0>;
  549. pinctrl-names = "default";
  550. pinctrl-0 = <&spi1_bus>;
  551. status = "disabled";
  552. };
  553. i2s2: i2s@13970000 {
  554. compatible = "samsung,s3c6410-i2s";
  555. reg = <0x13970000 0x100>;
  556. interrupts = <0 126 0>;
  557. clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
  558. clock-names = "iis", "i2s_opclk0";
  559. dmas = <&pdma0 14>, <&pdma0 13>;
  560. dma-names = "tx", "rx";
  561. pinctrl-0 = <&i2s2_bus>;
  562. pinctrl-names = "default";
  563. status = "disabled";
  564. };
  565. pwm: pwm@139D0000 {
  566. compatible = "samsung,exynos4210-pwm";
  567. reg = <0x139D0000 0x1000>;
  568. interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
  569. <0 107 0>, <0 108 0>;
  570. #pwm-cells = <3>;
  571. status = "disabled";
  572. };
  573. pmu {
  574. compatible = "arm,cortex-a7-pmu";
  575. interrupts = <0 18 0>, <0 19 0>;
  576. };
  577. ppmu_dmc0: ppmu_dmc0@106a0000 {
  578. compatible = "samsung,exynos-ppmu";
  579. reg = <0x106a0000 0x2000>;
  580. status = "disabled";
  581. };
  582. ppmu_dmc1: ppmu_dmc1@106b0000 {
  583. compatible = "samsung,exynos-ppmu";
  584. reg = <0x106b0000 0x2000>;
  585. status = "disabled";
  586. };
  587. ppmu_cpu: ppmu_cpu@106c0000 {
  588. compatible = "samsung,exynos-ppmu";
  589. reg = <0x106c0000 0x2000>;
  590. status = "disabled";
  591. };
  592. ppmu_rightbus: ppmu_rightbus@112a0000 {
  593. compatible = "samsung,exynos-ppmu";
  594. reg = <0x112a0000 0x2000>;
  595. clocks = <&cmu CLK_PPMURIGHT>;
  596. clock-names = "ppmu";
  597. status = "disabled";
  598. };
  599. ppmu_leftbus: ppmu_leftbus0@116a0000 {
  600. compatible = "samsung,exynos-ppmu";
  601. reg = <0x116a0000 0x2000>;
  602. clocks = <&cmu CLK_PPMULEFT>;
  603. clock-names = "ppmu";
  604. status = "disabled";
  605. };
  606. ppmu_camif: ppmu_camif@11ac0000 {
  607. compatible = "samsung,exynos-ppmu";
  608. reg = <0x11ac0000 0x2000>;
  609. clocks = <&cmu CLK_PPMUCAMIF>;
  610. clock-names = "ppmu";
  611. status = "disabled";
  612. };
  613. ppmu_lcd0: ppmu_lcd0@11e40000 {
  614. compatible = "samsung,exynos-ppmu";
  615. reg = <0x11e40000 0x2000>;
  616. clocks = <&cmu CLK_PPMULCD0>;
  617. clock-names = "ppmu";
  618. status = "disabled";
  619. };
  620. ppmu_fsys: ppmu_fsys@12630000 {
  621. compatible = "samsung,exynos-ppmu";
  622. reg = <0x12630000 0x2000>;
  623. clocks = <&cmu CLK_PPMUFILE>;
  624. clock-names = "ppmu";
  625. status = "disabled";
  626. };
  627. ppmu_g3d: ppmu_g3d@13220000 {
  628. compatible = "samsung,exynos-ppmu";
  629. reg = <0x13220000 0x2000>;
  630. clocks = <&cmu CLK_PPMUG3D>;
  631. clock-names = "ppmu";
  632. status = "disabled";
  633. };
  634. ppmu_mfc: ppmu_mfc@13660000 {
  635. compatible = "samsung,exynos-ppmu";
  636. reg = <0x13660000 0x2000>;
  637. clocks = <&cmu CLK_PPMUMFC_L>;
  638. clock-names = "ppmu";
  639. status = "disabled";
  640. };
  641. bus_dmc: bus_dmc {
  642. compatible = "samsung,exynos-bus";
  643. clocks = <&cmu_dmc CLK_DIV_DMC>;
  644. clock-names = "bus";
  645. operating-points-v2 = <&bus_dmc_opp_table>;
  646. status = "disabled";
  647. };
  648. bus_dmc_opp_table: opp_table1 {
  649. compatible = "operating-points-v2";
  650. opp-shared;
  651. opp@50000000 {
  652. opp-hz = /bits/ 64 <50000000>;
  653. opp-microvolt = <800000>;
  654. };
  655. opp@100000000 {
  656. opp-hz = /bits/ 64 <100000000>;
  657. opp-microvolt = <800000>;
  658. };
  659. opp@134000000 {
  660. opp-hz = /bits/ 64 <134000000>;
  661. opp-microvolt = <800000>;
  662. };
  663. opp@200000000 {
  664. opp-hz = /bits/ 64 <200000000>;
  665. opp-microvolt = <825000>;
  666. };
  667. opp@400000000 {
  668. opp-hz = /bits/ 64 <400000000>;
  669. opp-microvolt = <875000>;
  670. };
  671. };
  672. bus_leftbus: bus_leftbus {
  673. compatible = "samsung,exynos-bus";
  674. clocks = <&cmu CLK_DIV_GDL>;
  675. clock-names = "bus";
  676. operating-points-v2 = <&bus_leftbus_opp_table>;
  677. status = "disabled";
  678. };
  679. bus_rightbus: bus_rightbus {
  680. compatible = "samsung,exynos-bus";
  681. clocks = <&cmu CLK_DIV_GDR>;
  682. clock-names = "bus";
  683. operating-points-v2 = <&bus_leftbus_opp_table>;
  684. status = "disabled";
  685. };
  686. bus_lcd0: bus_lcd0 {
  687. compatible = "samsung,exynos-bus";
  688. clocks = <&cmu CLK_DIV_ACLK_160>;
  689. clock-names = "bus";
  690. operating-points-v2 = <&bus_leftbus_opp_table>;
  691. status = "disabled";
  692. };
  693. bus_fsys: bus_fsys {
  694. compatible = "samsung,exynos-bus";
  695. clocks = <&cmu CLK_DIV_ACLK_200>;
  696. clock-names = "bus";
  697. operating-points-v2 = <&bus_leftbus_opp_table>;
  698. status = "disabled";
  699. };
  700. bus_mcuisp: bus_mcuisp {
  701. compatible = "samsung,exynos-bus";
  702. clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
  703. clock-names = "bus";
  704. operating-points-v2 = <&bus_mcuisp_opp_table>;
  705. status = "disabled";
  706. };
  707. bus_isp: bus_isp {
  708. compatible = "samsung,exynos-bus";
  709. clocks = <&cmu CLK_DIV_ACLK_266>;
  710. clock-names = "bus";
  711. operating-points-v2 = <&bus_isp_opp_table>;
  712. status = "disabled";
  713. };
  714. bus_peril: bus_peril {
  715. compatible = "samsung,exynos-bus";
  716. clocks = <&cmu CLK_DIV_ACLK_100>;
  717. clock-names = "bus";
  718. operating-points-v2 = <&bus_peril_opp_table>;
  719. status = "disabled";
  720. };
  721. bus_mfc: bus_mfc {
  722. compatible = "samsung,exynos-bus";
  723. clocks = <&cmu CLK_SCLK_MFC>;
  724. clock-names = "bus";
  725. operating-points-v2 = <&bus_leftbus_opp_table>;
  726. status = "disabled";
  727. };
  728. bus_leftbus_opp_table: opp_table2 {
  729. compatible = "operating-points-v2";
  730. opp-shared;
  731. opp@50000000 {
  732. opp-hz = /bits/ 64 <50000000>;
  733. opp-microvolt = <900000>;
  734. };
  735. opp@80000000 {
  736. opp-hz = /bits/ 64 <80000000>;
  737. opp-microvolt = <900000>;
  738. };
  739. opp@100000000 {
  740. opp-hz = /bits/ 64 <100000000>;
  741. opp-microvolt = <1000000>;
  742. };
  743. opp@134000000 {
  744. opp-hz = /bits/ 64 <134000000>;
  745. opp-microvolt = <1000000>;
  746. };
  747. opp@200000000 {
  748. opp-hz = /bits/ 64 <200000000>;
  749. opp-microvolt = <1000000>;
  750. };
  751. };
  752. bus_mcuisp_opp_table: opp_table3 {
  753. compatible = "operating-points-v2";
  754. opp-shared;
  755. opp@50000000 {
  756. opp-hz = /bits/ 64 <50000000>;
  757. };
  758. opp@80000000 {
  759. opp-hz = /bits/ 64 <80000000>;
  760. };
  761. opp@100000000 {
  762. opp-hz = /bits/ 64 <100000000>;
  763. };
  764. opp@200000000 {
  765. opp-hz = /bits/ 64 <200000000>;
  766. };
  767. opp@400000000 {
  768. opp-hz = /bits/ 64 <400000000>;
  769. };
  770. };
  771. bus_isp_opp_table: opp_table4 {
  772. compatible = "operating-points-v2";
  773. opp-shared;
  774. opp@50000000 {
  775. opp-hz = /bits/ 64 <50000000>;
  776. };
  777. opp@80000000 {
  778. opp-hz = /bits/ 64 <80000000>;
  779. };
  780. opp@100000000 {
  781. opp-hz = /bits/ 64 <100000000>;
  782. };
  783. opp@200000000 {
  784. opp-hz = /bits/ 64 <200000000>;
  785. };
  786. opp@300000000 {
  787. opp-hz = /bits/ 64 <300000000>;
  788. };
  789. };
  790. bus_peril_opp_table: opp_table5 {
  791. compatible = "operating-points-v2";
  792. opp-shared;
  793. opp@50000000 {
  794. opp-hz = /bits/ 64 <50000000>;
  795. };
  796. opp@80000000 {
  797. opp-hz = /bits/ 64 <80000000>;
  798. };
  799. opp@100000000 {
  800. opp-hz = /bits/ 64 <100000000>;
  801. };
  802. };
  803. };
  804. };
  805. #include "exynos3250-pinctrl.dtsi"