dm816x.dtsi 12 KB

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  1. /*
  2. * This file is licensed under the terms of the GNU General Public License
  3. * version 2. This program is licensed "as is" without any warranty of any
  4. * kind, whether express or implied.
  5. */
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/pinctrl/omap.h>
  8. / {
  9. compatible = "ti,dm816";
  10. interrupt-parent = <&intc>;
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. chosen { };
  14. aliases {
  15. i2c0 = &i2c1;
  16. i2c1 = &i2c2;
  17. serial0 = &uart1;
  18. serial1 = &uart2;
  19. serial2 = &uart3;
  20. ethernet0 = &eth0;
  21. ethernet1 = &eth1;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. cpu@0 {
  27. compatible = "arm,cortex-a8";
  28. device_type = "cpu";
  29. reg = <0>;
  30. };
  31. };
  32. pmu {
  33. compatible = "arm,cortex-a8-pmu";
  34. interrupts = <3>;
  35. };
  36. /*
  37. * The soc node represents the soc top level view. It is used for IPs
  38. * that are not memory mapped in the MPU view or for the MPU itself.
  39. */
  40. soc {
  41. compatible = "ti,omap-infra";
  42. mpu {
  43. compatible = "ti,omap3-mpu";
  44. ti,hwmods = "mpu";
  45. };
  46. };
  47. /*
  48. * XXX: Use a flat representation of the dm816x interconnect.
  49. * The real dm816x interconnect network is quite complex. Since
  50. * it will not bring real advantage to represent that in DT
  51. * for the moment, just use a fake OCP bus entry to represent
  52. * the whole bus hierarchy.
  53. */
  54. ocp {
  55. compatible = "simple-bus";
  56. reg = <0x44000000 0x10000>;
  57. interrupts = <9 10>;
  58. #address-cells = <1>;
  59. #size-cells = <1>;
  60. ranges;
  61. prcm: prcm@48180000 {
  62. compatible = "ti,dm816-prcm";
  63. reg = <0x48180000 0x4000>;
  64. prcm_clocks: clocks {
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. };
  68. prcm_clockdomains: clockdomains {
  69. };
  70. };
  71. scrm: scrm@48140000 {
  72. compatible = "ti,dm816-scrm", "simple-bus";
  73. reg = <0x48140000 0x21000>;
  74. #address-cells = <1>;
  75. #size-cells = <1>;
  76. ranges = <0 0x48140000 0x21000>;
  77. dm816x_pinmux: pinmux@800 {
  78. compatible = "pinctrl-single";
  79. reg = <0x800 0x50a>;
  80. #address-cells = <1>;
  81. #size-cells = <0>;
  82. pinctrl-single,register-width = <16>;
  83. pinctrl-single,function-mask = <0xf>;
  84. };
  85. /* Device Configuration Registers */
  86. scm_conf: syscon@600 {
  87. compatible = "syscon", "simple-bus";
  88. reg = <0x600 0x110>;
  89. #address-cells = <1>;
  90. #size-cells = <1>;
  91. ranges = <0 0x600 0x110>;
  92. usb_phy0: usb-phy@20 {
  93. compatible = "ti,dm8168-usb-phy";
  94. reg = <0x20 0x8>;
  95. reg-names = "phy";
  96. clocks = <&main_fapll 6>;
  97. clock-names = "refclk";
  98. #phy-cells = <0>;
  99. syscon = <&scm_conf>;
  100. };
  101. usb_phy1: usb-phy@28 {
  102. compatible = "ti,dm8168-usb-phy";
  103. reg = <0x28 0x8>;
  104. reg-names = "phy";
  105. clocks = <&main_fapll 6>;
  106. clock-names = "refclk";
  107. #phy-cells = <0>;
  108. syscon = <&scm_conf>;
  109. };
  110. };
  111. scrm_clocks: clocks {
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. };
  115. scrm_clockdomains: clockdomains {
  116. };
  117. };
  118. edma: edma@49000000 {
  119. compatible = "ti,edma3";
  120. ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
  121. reg = <0x49000000 0x10000>,
  122. <0x44e10f90 0x40>;
  123. interrupts = <12 13 14>;
  124. #dma-cells = <1>;
  125. };
  126. elm: elm@48080000 {
  127. compatible = "ti,816-elm";
  128. ti,hwmods = "elm";
  129. reg = <0x48080000 0x2000>;
  130. interrupts = <4>;
  131. };
  132. gpio1: gpio@48032000 {
  133. compatible = "ti,omap4-gpio";
  134. ti,hwmods = "gpio1";
  135. ti,gpio-always-on;
  136. reg = <0x48032000 0x1000>;
  137. interrupts = <96>;
  138. gpio-controller;
  139. #gpio-cells = <2>;
  140. interrupt-controller;
  141. #interrupt-cells = <2>;
  142. };
  143. gpio2: gpio@4804c000 {
  144. compatible = "ti,omap4-gpio";
  145. ti,hwmods = "gpio2";
  146. ti,gpio-always-on;
  147. reg = <0x4804c000 0x1000>;
  148. interrupts = <98>;
  149. gpio-controller;
  150. #gpio-cells = <2>;
  151. interrupt-controller;
  152. #interrupt-cells = <2>;
  153. };
  154. gpmc: gpmc@50000000 {
  155. compatible = "ti,am3352-gpmc";
  156. ti,hwmods = "gpmc";
  157. reg = <0x50000000 0x2000>;
  158. #address-cells = <2>;
  159. #size-cells = <1>;
  160. interrupts = <100>;
  161. dmas = <&edma 52>;
  162. dma-names = "rxtx";
  163. gpmc,num-cs = <6>;
  164. gpmc,num-waitpins = <2>;
  165. interrupt-controller;
  166. #interrupt-cells = <2>;
  167. gpio-controller;
  168. #gpio-cells = <2>;
  169. };
  170. i2c1: i2c@48028000 {
  171. compatible = "ti,omap4-i2c";
  172. ti,hwmods = "i2c1";
  173. reg = <0x48028000 0x1000>;
  174. #address-cells = <1>;
  175. #size-cells = <0>;
  176. interrupts = <70>;
  177. dmas = <&edma 58 &edma 59>;
  178. dma-names = "tx", "rx";
  179. };
  180. i2c2: i2c@4802a000 {
  181. compatible = "ti,omap4-i2c";
  182. ti,hwmods = "i2c2";
  183. reg = <0x4802a000 0x1000>;
  184. #address-cells = <1>;
  185. #size-cells = <0>;
  186. interrupts = <71>;
  187. dmas = <&edma 60 &edma 61>;
  188. dma-names = "tx", "rx";
  189. };
  190. intc: interrupt-controller@48200000 {
  191. compatible = "ti,dm816-intc";
  192. interrupt-controller;
  193. #interrupt-cells = <1>;
  194. reg = <0x48200000 0x1000>;
  195. };
  196. rtc: rtc@480c0000 {
  197. compatible = "ti,am3352-rtc", "ti,da830-rtc";
  198. reg = <0x480c0000 0x1000>;
  199. interrupts = <75 76>;
  200. ti,hwmods = "rtc";
  201. };
  202. mailbox: mailbox@480c8000 {
  203. compatible = "ti,omap4-mailbox";
  204. reg = <0x480c8000 0x2000>;
  205. interrupts = <77>;
  206. ti,hwmods = "mailbox";
  207. #mbox-cells = <1>;
  208. ti,mbox-num-users = <4>;
  209. ti,mbox-num-fifos = <12>;
  210. mbox_dsp: mbox_dsp {
  211. ti,mbox-tx = <3 0 0>;
  212. ti,mbox-rx = <0 0 0>;
  213. };
  214. };
  215. spinbox: spinbox@480ca000 {
  216. compatible = "ti,omap4-hwspinlock";
  217. reg = <0x480ca000 0x2000>;
  218. ti,hwmods = "spinbox";
  219. #hwlock-cells = <1>;
  220. };
  221. mdio: mdio@4a100800 {
  222. compatible = "ti,davinci_mdio";
  223. #address-cells = <1>;
  224. #size-cells = <0>;
  225. reg = <0x4a100800 0x100>;
  226. ti,hwmods = "davinci_mdio";
  227. bus_freq = <1000000>;
  228. phy0: ethernet-phy@0 {
  229. reg = <1>;
  230. };
  231. phy1: ethernet-phy@1 {
  232. reg = <2>;
  233. };
  234. };
  235. eth0: ethernet@4a100000 {
  236. compatible = "ti,dm816-emac";
  237. ti,hwmods = "emac0";
  238. reg = <0x4a100000 0x800
  239. 0x4a100900 0x3700>;
  240. clocks = <&sysclk24_ck>;
  241. syscon = <&scm_conf>;
  242. ti,davinci-ctrl-reg-offset = <0>;
  243. ti,davinci-ctrl-mod-reg-offset = <0x900>;
  244. ti,davinci-ctrl-ram-offset = <0x2000>;
  245. ti,davinci-ctrl-ram-size = <0x2000>;
  246. interrupts = <40 41 42 43>;
  247. phy-handle = <&phy0>;
  248. };
  249. eth1: ethernet@4a120000 {
  250. compatible = "ti,dm816-emac";
  251. ti,hwmods = "emac1";
  252. reg = <0x4a120000 0x4000>;
  253. clocks = <&sysclk24_ck>;
  254. syscon = <&scm_conf>;
  255. ti,davinci-ctrl-reg-offset = <0>;
  256. ti,davinci-ctrl-mod-reg-offset = <0x900>;
  257. ti,davinci-ctrl-ram-offset = <0x2000>;
  258. ti,davinci-ctrl-ram-size = <0x2000>;
  259. interrupts = <44 45 46 47>;
  260. phy-handle = <&phy1>;
  261. };
  262. mcspi1: spi@48030000 {
  263. compatible = "ti,omap4-mcspi";
  264. reg = <0x48030000 0x1000>;
  265. #address-cells = <1>;
  266. #size-cells = <0>;
  267. interrupts = <65>;
  268. ti,spi-num-cs = <4>;
  269. ti,hwmods = "mcspi1";
  270. dmas = <&edma 16 &edma 17
  271. &edma 18 &edma 19
  272. &edma 20 &edma 21
  273. &edma 22 &edma 23>;
  274. dma-names = "tx0", "rx0", "tx1", "rx1",
  275. "tx2", "rx2", "tx3", "rx3";
  276. };
  277. mmc1: mmc@48060000 {
  278. compatible = "ti,omap4-hsmmc";
  279. reg = <0x48060000 0x11000>;
  280. ti,hwmods = "mmc1";
  281. interrupts = <64>;
  282. dmas = <&edma 24 &edma 25>;
  283. dma-names = "tx", "rx";
  284. };
  285. timer1: timer@4802e000 {
  286. compatible = "ti,dm816-timer";
  287. reg = <0x4802e000 0x2000>;
  288. interrupts = <67>;
  289. ti,hwmods = "timer1";
  290. ti,timer-alwon;
  291. };
  292. timer2: timer@48040000 {
  293. compatible = "ti,dm816-timer";
  294. reg = <0x48040000 0x2000>;
  295. interrupts = <68>;
  296. ti,hwmods = "timer2";
  297. };
  298. timer3: timer@48042000 {
  299. compatible = "ti,dm816-timer";
  300. reg = <0x48042000 0x2000>;
  301. interrupts = <69>;
  302. ti,hwmods = "timer3";
  303. };
  304. timer4: timer@48044000 {
  305. compatible = "ti,dm816-timer";
  306. reg = <0x48044000 0x2000>;
  307. interrupts = <92>;
  308. ti,hwmods = "timer4";
  309. ti,timer-pwm;
  310. };
  311. timer5: timer@48046000 {
  312. compatible = "ti,dm816-timer";
  313. reg = <0x48046000 0x2000>;
  314. interrupts = <93>;
  315. ti,hwmods = "timer5";
  316. ti,timer-pwm;
  317. };
  318. timer6: timer@48048000 {
  319. compatible = "ti,dm816-timer";
  320. reg = <0x48048000 0x2000>;
  321. interrupts = <94>;
  322. ti,hwmods = "timer6";
  323. ti,timer-pwm;
  324. };
  325. timer7: timer@4804a000 {
  326. compatible = "ti,dm816-timer";
  327. reg = <0x4804a000 0x2000>;
  328. interrupts = <95>;
  329. ti,hwmods = "timer7";
  330. ti,timer-pwm;
  331. };
  332. uart1: uart@48020000 {
  333. compatible = "ti,am3352-uart", "ti,omap3-uart";
  334. ti,hwmods = "uart1";
  335. reg = <0x48020000 0x2000>;
  336. clock-frequency = <48000000>;
  337. interrupts = <72>;
  338. dmas = <&edma 26 &edma 27>;
  339. dma-names = "tx", "rx";
  340. };
  341. uart2: uart@48022000 {
  342. compatible = "ti,am3352-uart", "ti,omap3-uart";
  343. ti,hwmods = "uart2";
  344. reg = <0x48022000 0x2000>;
  345. clock-frequency = <48000000>;
  346. interrupts = <73>;
  347. dmas = <&edma 28 &edma 29>;
  348. dma-names = "tx", "rx";
  349. };
  350. uart3: uart@48024000 {
  351. compatible = "ti,am3352-uart", "ti,omap3-uart";
  352. ti,hwmods = "uart3";
  353. reg = <0x48024000 0x2000>;
  354. clock-frequency = <48000000>;
  355. interrupts = <74>;
  356. dmas = <&edma 30 &edma 31>;
  357. dma-names = "tx", "rx";
  358. };
  359. /* NOTE: USB needs a transceiver driver for phys to work */
  360. usb: usb_otg_hs@47401000 {
  361. compatible = "ti,am33xx-usb";
  362. reg = <0x47401000 0x400000>;
  363. ranges;
  364. #address-cells = <1>;
  365. #size-cells = <1>;
  366. ti,hwmods = "usb_otg_hs";
  367. usb0: usb@47401000 {
  368. compatible = "ti,musb-dm816";
  369. reg = <0x47401400 0x400
  370. 0x47401000 0x200>;
  371. reg-names = "mc", "control";
  372. interrupts = <18>;
  373. interrupt-names = "mc";
  374. dr_mode = "host";
  375. interface-type = <0>;
  376. phys = <&usb_phy0>;
  377. phy-names = "usb2-phy";
  378. mentor,multipoint = <1>;
  379. mentor,num-eps = <16>;
  380. mentor,ram-bits = <12>;
  381. mentor,power = <500>;
  382. dmas = <&cppi41dma 0 0 &cppi41dma 1 0
  383. &cppi41dma 2 0 &cppi41dma 3 0
  384. &cppi41dma 4 0 &cppi41dma 5 0
  385. &cppi41dma 6 0 &cppi41dma 7 0
  386. &cppi41dma 8 0 &cppi41dma 9 0
  387. &cppi41dma 10 0 &cppi41dma 11 0
  388. &cppi41dma 12 0 &cppi41dma 13 0
  389. &cppi41dma 14 0 &cppi41dma 0 1
  390. &cppi41dma 1 1 &cppi41dma 2 1
  391. &cppi41dma 3 1 &cppi41dma 4 1
  392. &cppi41dma 5 1 &cppi41dma 6 1
  393. &cppi41dma 7 1 &cppi41dma 8 1
  394. &cppi41dma 9 1 &cppi41dma 10 1
  395. &cppi41dma 11 1 &cppi41dma 12 1
  396. &cppi41dma 13 1 &cppi41dma 14 1>;
  397. dma-names =
  398. "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
  399. "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
  400. "rx14", "rx15",
  401. "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
  402. "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
  403. "tx14", "tx15";
  404. };
  405. usb1: usb@47401800 {
  406. compatible = "ti,musb-dm816";
  407. reg = <0x47401c00 0x400
  408. 0x47401800 0x200>;
  409. reg-names = "mc", "control";
  410. interrupts = <19>;
  411. interrupt-names = "mc";
  412. dr_mode = "host";
  413. interface-type = <0>;
  414. phys = <&usb_phy1>;
  415. phy-names = "usb2-phy";
  416. mentor,multipoint = <1>;
  417. mentor,num-eps = <16>;
  418. mentor,ram-bits = <12>;
  419. mentor,power = <500>;
  420. dmas = <&cppi41dma 15 0 &cppi41dma 16 0
  421. &cppi41dma 17 0 &cppi41dma 18 0
  422. &cppi41dma 19 0 &cppi41dma 20 0
  423. &cppi41dma 21 0 &cppi41dma 22 0
  424. &cppi41dma 23 0 &cppi41dma 24 0
  425. &cppi41dma 25 0 &cppi41dma 26 0
  426. &cppi41dma 27 0 &cppi41dma 28 0
  427. &cppi41dma 29 0 &cppi41dma 15 1
  428. &cppi41dma 16 1 &cppi41dma 17 1
  429. &cppi41dma 18 1 &cppi41dma 19 1
  430. &cppi41dma 20 1 &cppi41dma 21 1
  431. &cppi41dma 22 1 &cppi41dma 23 1
  432. &cppi41dma 24 1 &cppi41dma 25 1
  433. &cppi41dma 26 1 &cppi41dma 27 1
  434. &cppi41dma 28 1 &cppi41dma 29 1>;
  435. dma-names =
  436. "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
  437. "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
  438. "rx14", "rx15",
  439. "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
  440. "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
  441. "tx14", "tx15";
  442. };
  443. cppi41dma: dma-controller@47402000 {
  444. compatible = "ti,am3359-cppi41";
  445. reg = <0x47400000 0x1000
  446. 0x47402000 0x1000
  447. 0x47403000 0x1000
  448. 0x47404000 0x4000>;
  449. reg-names = "glue", "controller", "scheduler", "queuemgr";
  450. interrupts = <17>;
  451. interrupt-names = "glue";
  452. #dma-cells = <2>;
  453. #dma-channels = <30>;
  454. #dma-requests = <256>;
  455. };
  456. };
  457. wd_timer2: wd_timer@480c2000 {
  458. compatible = "ti,omap3-wdt";
  459. ti,hwmods = "wd_timer";
  460. reg = <0x480c2000 0x1000>;
  461. interrupts = <0>;
  462. };
  463. };
  464. };
  465. #include "dm816x-clocks.dtsi"