bcm23550.dtsi 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416
  1. /*
  2. * BSD LICENSE
  3. *
  4. * Copyright(c) 2016 Broadcom. All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. *
  10. * * Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions and the following disclaimer.
  12. * * Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in
  14. * the documentation and/or other materials provided with the
  15. * distribution.
  16. * * Neither the name of Broadcom Corporation nor the names of its
  17. * contributors may be used to endorse or promote products derived
  18. * from this software without specific prior written permission.
  19. *
  20. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31. */
  32. #include <dt-bindings/interrupt-controller/arm-gic.h>
  33. #include <dt-bindings/interrupt-controller/irq.h>
  34. /* BCM23550 and BCM21664 have almost identical clocks */
  35. #include "dt-bindings/clock/bcm21664.h"
  36. #include "skeleton.dtsi"
  37. / {
  38. model = "BCM23550 SoC";
  39. compatible = "brcm,bcm23550";
  40. interrupt-parent = <&gic>;
  41. cpus {
  42. #address-cells = <1>;
  43. #size-cells = <0>;
  44. cpu0: cpu@0 {
  45. device_type = "cpu";
  46. compatible = "arm,cortex-a7";
  47. reg = <0>;
  48. clock-frequency = <1000000000>;
  49. };
  50. cpu1: cpu@1 {
  51. device_type = "cpu";
  52. compatible = "arm,cortex-a7";
  53. enable-method = "brcm,bcm23550";
  54. secondary-boot-reg = <0x35004178>;
  55. reg = <1>;
  56. clock-frequency = <1000000000>;
  57. };
  58. cpu2: cpu@2 {
  59. device_type = "cpu";
  60. compatible = "arm,cortex-a7";
  61. enable-method = "brcm,bcm23550";
  62. secondary-boot-reg = <0x35004178>;
  63. reg = <2>;
  64. clock-frequency = <1000000000>;
  65. };
  66. cpu3: cpu@3 {
  67. device_type = "cpu";
  68. compatible = "arm,cortex-a7";
  69. enable-method = "brcm,bcm23550";
  70. secondary-boot-reg = <0x35004178>;
  71. reg = <3>;
  72. clock-frequency = <1000000000>;
  73. };
  74. };
  75. /* Hub bus */
  76. hub@34000000 {
  77. compatible = "simple-bus";
  78. ranges = <0 0x34000000 0x102f83ac>;
  79. #address-cells = <1>;
  80. #size-cells = <1>;
  81. smc@4e000 {
  82. compatible = "brcm,bcm23550-smc", "brcm,kona-smc";
  83. reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
  84. };
  85. resetmgr: reset-controller@1001f00 {
  86. compatible = "brcm,bcm21664-resetmgr";
  87. reg = <0x01001f00 0x24>;
  88. };
  89. gpio: gpio@1003000 {
  90. compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio";
  91. reg = <0x01003000 0x524>;
  92. interrupts =
  93. <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
  94. GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
  95. GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
  96. GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  97. #gpio-cells = <2>;
  98. #interrupt-cells = <2>;
  99. gpio-controller;
  100. interrupt-controller;
  101. };
  102. timer@1006000 {
  103. compatible = "brcm,kona-timer";
  104. reg = <0x01006000 0x1c>;
  105. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  106. clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
  107. };
  108. };
  109. /* Slaves bus */
  110. slaves@3e000000 {
  111. compatible = "simple-bus";
  112. ranges = <0 0x3e000000 0x0001c070>;
  113. #address-cells = <1>;
  114. #size-cells = <1>;
  115. uartb: serial@0 {
  116. compatible = "snps,dw-apb-uart";
  117. status = "disabled";
  118. reg = <0x00000000 0x118>;
  119. clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
  120. interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  121. reg-shift = <2>;
  122. reg-io-width = <4>;
  123. };
  124. uartb2: serial@1000 {
  125. compatible = "snps,dw-apb-uart";
  126. status = "disabled";
  127. reg = <0x00001000 0x118>;
  128. clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
  129. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  130. reg-shift = <2>;
  131. reg-io-width = <4>;
  132. };
  133. uartb3: serial@2000 {
  134. compatible = "snps,dw-apb-uart";
  135. status = "disabled";
  136. reg = <0x00002000 0x118>;
  137. clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
  138. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  139. reg-shift = <2>;
  140. reg-io-width = <4>;
  141. };
  142. bsc1: i2c@16000 {
  143. compatible = "brcm,kona-i2c";
  144. reg = <0x00016000 0x70>;
  145. interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  146. #address-cells = <1>;
  147. #size-cells = <0>;
  148. clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
  149. status = "disabled";
  150. };
  151. bsc2: i2c@17000 {
  152. compatible = "brcm,kona-i2c";
  153. reg = <0x00017000 0x70>;
  154. interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
  155. #address-cells = <1>;
  156. #size-cells = <0>;
  157. clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
  158. status = "disabled";
  159. };
  160. bsc3: i2c@18000 {
  161. compatible = "brcm,kona-i2c";
  162. reg = <0x00018000 0x70>;
  163. interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
  164. #address-cells = <1>;
  165. #size-cells = <0>;
  166. clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
  167. status = "disabled";
  168. };
  169. bsc4: i2c@1c000 {
  170. compatible = "brcm,kona-i2c";
  171. reg = <0x0001c000 0x70>;
  172. interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
  173. #address-cells = <1>;
  174. #size-cells = <0>;
  175. clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
  176. status = "disabled";
  177. };
  178. };
  179. /* Apps bus */
  180. apps@3e300000 {
  181. compatible = "simple-bus";
  182. ranges = <0 0x3e300000 0x01b77000>;
  183. #address-cells = <1>;
  184. #size-cells = <1>;
  185. usbotg: usb@e20000 {
  186. compatible = "snps,dwc2";
  187. reg = <0x00e20000 0x10000>;
  188. interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
  189. clocks = <&usb_otg_ahb_clk>;
  190. clock-names = "otg";
  191. phys = <&usbphy>;
  192. phy-names = "usb2-phy";
  193. status = "disabled";
  194. };
  195. usbphy: usb-phy@e30000 {
  196. compatible = "brcm,kona-usb2-phy";
  197. reg = <0x00e30000 0x28>;
  198. #phy-cells = <0>;
  199. status = "disabled";
  200. };
  201. sdio1: sdio@e80000 {
  202. compatible = "brcm,kona-sdhci";
  203. reg = <0x00e80000 0x801c>;
  204. interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  205. clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
  206. status = "disabled";
  207. };
  208. sdio2: sdio@e90000 {
  209. compatible = "brcm,kona-sdhci";
  210. reg = <0x00e90000 0x801c>;
  211. interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  212. clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
  213. status = "disabled";
  214. };
  215. sdio3: sdio@ea0000 {
  216. compatible = "brcm,kona-sdhci";
  217. reg = <0x00ea0000 0x801c>;
  218. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  219. clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
  220. status = "disabled";
  221. };
  222. sdio4: sdio@eb0000 {
  223. compatible = "brcm,kona-sdhci";
  224. reg = <0x00eb0000 0x801c>;
  225. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  226. clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
  227. status = "disabled";
  228. };
  229. cdc: cdc@1b0e000 {
  230. compatible = "brcm,bcm23550-cdc";
  231. reg = <0x01b0e000 0x78>;
  232. };
  233. gic: interrupt-controller@1b21000 {
  234. compatible = "arm,cortex-a9-gic";
  235. #interrupt-cells = <3>;
  236. #address-cells = <0>;
  237. interrupt-controller;
  238. reg = <0x01b21000 0x1000>,
  239. <0x01b22000 0x1000>;
  240. };
  241. };
  242. clocks {
  243. #address-cells = <1>;
  244. #size-cells = <1>;
  245. ranges;
  246. /*
  247. * Fixed clocks are defined before CCUs whose
  248. * clocks may depend on them.
  249. */
  250. ref_32k_clk: ref_32k {
  251. #clock-cells = <0>;
  252. compatible = "fixed-clock";
  253. clock-frequency = <32768>;
  254. };
  255. bbl_32k_clk: bbl_32k {
  256. #clock-cells = <0>;
  257. compatible = "fixed-clock";
  258. clock-frequency = <32768>;
  259. };
  260. ref_13m_clk: ref_13m {
  261. #clock-cells = <0>;
  262. compatible = "fixed-clock";
  263. clock-frequency = <13000000>;
  264. };
  265. var_13m_clk: var_13m {
  266. #clock-cells = <0>;
  267. compatible = "fixed-clock";
  268. clock-frequency = <13000000>;
  269. };
  270. dft_19_5m_clk: dft_19_5m {
  271. #clock-cells = <0>;
  272. compatible = "fixed-clock";
  273. clock-frequency = <19500000>;
  274. };
  275. ref_crystal_clk: ref_crystal {
  276. #clock-cells = <0>;
  277. compatible = "fixed-clock";
  278. clock-frequency = <26000000>;
  279. };
  280. ref_52m_clk: ref_52m {
  281. #clock-cells = <0>;
  282. compatible = "fixed-clock";
  283. clock-frequency = <52000000>;
  284. };
  285. var_52m_clk: var_52m {
  286. #clock-cells = <0>;
  287. compatible = "fixed-clock";
  288. clock-frequency = <52000000>;
  289. };
  290. usb_otg_ahb_clk: usb_otg_ahb {
  291. #clock-cells = <0>;
  292. compatible = "fixed-clock";
  293. clock-frequency = <52000000>;
  294. };
  295. ref_96m_clk: ref_96m {
  296. #clock-cells = <0>;
  297. compatible = "fixed-clock";
  298. clock-frequency = <96000000>;
  299. };
  300. var_96m_clk: var_96m {
  301. #clock-cells = <0>;
  302. compatible = "fixed-clock";
  303. clock-frequency = <96000000>;
  304. };
  305. ref_104m_clk: ref_104m {
  306. #clock-cells = <0>;
  307. compatible = "fixed-clock";
  308. clock-frequency = <104000000>;
  309. };
  310. var_104m_clk: var_104m {
  311. #clock-cells = <0>;
  312. compatible = "fixed-clock";
  313. clock-frequency = <104000000>;
  314. };
  315. ref_156m_clk: ref_156m {
  316. #clock-cells = <0>;
  317. compatible = "fixed-clock";
  318. clock-frequency = <156000000>;
  319. };
  320. var_156m_clk: var_156m {
  321. #clock-cells = <0>;
  322. compatible = "fixed-clock";
  323. clock-frequency = <156000000>;
  324. };
  325. root_ccu: root_ccu {
  326. compatible = BCM21664_DT_ROOT_CCU_COMPAT;
  327. reg = <0x35001000 0x0f00>;
  328. #clock-cells = <1>;
  329. clock-output-names = "frac_1m";
  330. };
  331. aon_ccu: aon_ccu {
  332. compatible = BCM21664_DT_AON_CCU_COMPAT;
  333. reg = <0x35002000 0x0f00>;
  334. #clock-cells = <1>;
  335. clock-output-names = "hub_timer";
  336. };
  337. slave_ccu: slave_ccu {
  338. compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
  339. reg = <0x3e011000 0x0f00>;
  340. #clock-cells = <1>;
  341. clock-output-names = "uartb",
  342. "uartb2",
  343. "uartb3",
  344. "bsc1",
  345. "bsc2",
  346. "bsc3",
  347. "bsc4";
  348. };
  349. master_ccu: master_ccu {
  350. compatible = BCM21664_DT_MASTER_CCU_COMPAT;
  351. reg = <0x3f001000 0x0f00>;
  352. #clock-cells = <1>;
  353. clock-output-names = "sdio1",
  354. "sdio2",
  355. "sdio3",
  356. "sdio4",
  357. "sdio1_sleep",
  358. "sdio2_sleep",
  359. "sdio3_sleep",
  360. "sdio4_sleep";
  361. };
  362. };
  363. };