bcm-cygnus.dtsi 9.7 KB

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  1. /*
  2. * BSD LICENSE
  3. *
  4. * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. *
  10. * * Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions and the following disclaimer.
  12. * * Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in
  14. * the documentation and/or other materials provided with the
  15. * distribution.
  16. * * Neither the name of Broadcom Corporation nor the names of its
  17. * contributors may be used to endorse or promote products derived
  18. * from this software without specific prior written permission.
  19. *
  20. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31. */
  32. #include <dt-bindings/interrupt-controller/arm-gic.h>
  33. #include <dt-bindings/interrupt-controller/irq.h>
  34. #include <dt-bindings/clock/bcm-cygnus.h>
  35. #include "skeleton.dtsi"
  36. / {
  37. compatible = "brcm,cygnus";
  38. model = "Broadcom Cygnus SoC";
  39. interrupt-parent = <&gic>;
  40. cpus {
  41. #address-cells = <1>;
  42. #size-cells = <0>;
  43. cpu@0 {
  44. device_type = "cpu";
  45. compatible = "arm,cortex-a9";
  46. next-level-cache = <&L2>;
  47. reg = <0x0>;
  48. };
  49. };
  50. /include/ "bcm-cygnus-clock.dtsi"
  51. core {
  52. compatible = "simple-bus";
  53. ranges = <0x00000000 0x19000000 0x1000000>;
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. timer@20200 {
  57. compatible = "arm,cortex-a9-global-timer";
  58. reg = <0x20200 0x100>;
  59. interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  60. clocks = <&periph_clk>;
  61. };
  62. gic: interrupt-controller@21000 {
  63. compatible = "arm,cortex-a9-gic";
  64. #interrupt-cells = <3>;
  65. #address-cells = <0>;
  66. interrupt-controller;
  67. reg = <0x21000 0x1000>,
  68. <0x20100 0x100>;
  69. };
  70. L2: l2-cache {
  71. compatible = "arm,pl310-cache";
  72. reg = <0x22000 0x1000>;
  73. cache-unified;
  74. cache-level = <2>;
  75. };
  76. };
  77. axi {
  78. compatible = "simple-bus";
  79. ranges;
  80. #address-cells = <1>;
  81. #size-cells = <1>;
  82. pcie_phy: phy@0301d0a0 {
  83. compatible = "brcm,cygnus-pcie-phy";
  84. reg = <0x0301d0a0 0x14>;
  85. #address-cells = <1>;
  86. #size-cells = <0>;
  87. pcie0_phy: phy@0 {
  88. reg = <0>;
  89. #phy-cells = <0>;
  90. };
  91. pcie1_phy: phy@1 {
  92. reg = <1>;
  93. #phy-cells = <0>;
  94. };
  95. };
  96. pinctrl: pinctrl@0x0301d0c8 {
  97. compatible = "brcm,cygnus-pinmux";
  98. reg = <0x0301d0c8 0x30>,
  99. <0x0301d24c 0x2c>;
  100. };
  101. gpio_crmu: gpio@03024800 {
  102. compatible = "brcm,cygnus-crmu-gpio";
  103. reg = <0x03024800 0x50>,
  104. <0x03024008 0x18>;
  105. ngpios = <6>;
  106. #gpio-cells = <2>;
  107. gpio-controller;
  108. };
  109. i2c0: i2c@18008000 {
  110. compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
  111. reg = <0x18008000 0x100>;
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
  115. clock-frequency = <100000>;
  116. status = "disabled";
  117. };
  118. wdt0: wdt@18009000 {
  119. compatible = "arm,sp805" , "arm,primecell";
  120. reg = <0x18009000 0x1000>;
  121. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  122. clocks = <&axi81_clk>;
  123. clock-names = "apb_pclk";
  124. };
  125. gpio_ccm: gpio@1800a000 {
  126. compatible = "brcm,cygnus-ccm-gpio";
  127. reg = <0x1800a000 0x50>,
  128. <0x0301d164 0x20>;
  129. ngpios = <24>;
  130. #gpio-cells = <2>;
  131. gpio-controller;
  132. interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  133. interrupt-controller;
  134. };
  135. i2c1: i2c@1800b000 {
  136. compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
  137. reg = <0x1800b000 0x100>;
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
  141. clock-frequency = <100000>;
  142. status = "disabled";
  143. };
  144. pcie0: pcie@18012000 {
  145. compatible = "brcm,iproc-pcie";
  146. reg = <0x18012000 0x1000>;
  147. #interrupt-cells = <1>;
  148. interrupt-map-mask = <0 0 0 0>;
  149. interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
  150. linux,pci-domain = <0>;
  151. bus-range = <0x00 0xff>;
  152. #address-cells = <3>;
  153. #size-cells = <2>;
  154. device_type = "pci";
  155. ranges = <0x81000000 0 0 0x28000000 0 0x00010000
  156. 0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
  157. phys = <&pcie0_phy>;
  158. phy-names = "pcie-phy";
  159. status = "disabled";
  160. msi-parent = <&msi0>;
  161. msi0: msi@18012000 {
  162. compatible = "brcm,iproc-msi";
  163. msi-controller;
  164. interrupt-parent = <&gic>;
  165. interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
  166. <GIC_SPI 97 IRQ_TYPE_NONE>,
  167. <GIC_SPI 98 IRQ_TYPE_NONE>,
  168. <GIC_SPI 99 IRQ_TYPE_NONE>;
  169. };
  170. };
  171. pcie1: pcie@18013000 {
  172. compatible = "brcm,iproc-pcie";
  173. reg = <0x18013000 0x1000>;
  174. #interrupt-cells = <1>;
  175. interrupt-map-mask = <0 0 0 0>;
  176. interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
  177. linux,pci-domain = <1>;
  178. bus-range = <0x00 0xff>;
  179. #address-cells = <3>;
  180. #size-cells = <2>;
  181. device_type = "pci";
  182. ranges = <0x81000000 0 0 0x48000000 0 0x00010000
  183. 0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
  184. phys = <&pcie1_phy>;
  185. phy-names = "pcie-phy";
  186. status = "disabled";
  187. msi-parent = <&msi1>;
  188. msi1: msi@18013000 {
  189. compatible = "brcm,iproc-msi";
  190. msi-controller;
  191. interrupt-parent = <&gic>;
  192. interrupts = <GIC_SPI 102 IRQ_TYPE_NONE>,
  193. <GIC_SPI 103 IRQ_TYPE_NONE>,
  194. <GIC_SPI 104 IRQ_TYPE_NONE>,
  195. <GIC_SPI 105 IRQ_TYPE_NONE>;
  196. };
  197. };
  198. uart0: serial@18020000 {
  199. compatible = "snps,dw-apb-uart";
  200. reg = <0x18020000 0x100>;
  201. reg-shift = <2>;
  202. reg-io-width = <4>;
  203. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  204. clocks = <&axi81_clk>;
  205. clock-frequency = <100000000>;
  206. status = "disabled";
  207. };
  208. uart1: serial@18021000 {
  209. compatible = "snps,dw-apb-uart";
  210. reg = <0x18021000 0x100>;
  211. reg-shift = <2>;
  212. reg-io-width = <4>;
  213. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  214. clocks = <&axi81_clk>;
  215. clock-frequency = <100000000>;
  216. status = "disabled";
  217. };
  218. uart2: serial@18022000 {
  219. compatible = "snps,dw-apb-uart";
  220. reg = <0x18020000 0x100>;
  221. reg-shift = <2>;
  222. reg-io-width = <4>;
  223. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  224. clocks = <&axi81_clk>;
  225. clock-frequency = <100000000>;
  226. status = "disabled";
  227. };
  228. uart3: serial@18023000 {
  229. compatible = "snps,dw-apb-uart";
  230. reg = <0x18023000 0x100>;
  231. reg-shift = <2>;
  232. reg-io-width = <4>;
  233. interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  234. clocks = <&axi81_clk>;
  235. clock-frequency = <100000000>;
  236. status = "disabled";
  237. };
  238. nand: nand@18046000 {
  239. compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
  240. reg = <0x18046000 0x600>, <0xf8105408 0x600>,
  241. <0x18046f00 0x20>;
  242. reg-names = "nand", "iproc-idm", "iproc-ext";
  243. interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  244. #address-cells = <1>;
  245. #size-cells = <0>;
  246. brcm,nand-has-wp;
  247. };
  248. gpio_asiu: gpio@180a5000 {
  249. compatible = "brcm,cygnus-asiu-gpio";
  250. reg = <0x180a5000 0x668>;
  251. ngpios = <146>;
  252. #gpio-cells = <2>;
  253. gpio-controller;
  254. interrupt-controller;
  255. interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
  256. gpio-ranges = <&pinctrl 0 42 1>,
  257. <&pinctrl 1 44 3>,
  258. <&pinctrl 4 48 1>,
  259. <&pinctrl 5 50 3>,
  260. <&pinctrl 8 126 1>,
  261. <&pinctrl 9 155 1>,
  262. <&pinctrl 10 152 1>,
  263. <&pinctrl 11 154 1>,
  264. <&pinctrl 12 153 1>,
  265. <&pinctrl 13 127 3>,
  266. <&pinctrl 16 140 1>,
  267. <&pinctrl 17 145 7>,
  268. <&pinctrl 24 130 10>,
  269. <&pinctrl 34 141 4>,
  270. <&pinctrl 38 54 1>,
  271. <&pinctrl 39 56 3>,
  272. <&pinctrl 42 60 3>,
  273. <&pinctrl 45 64 3>,
  274. <&pinctrl 48 68 2>,
  275. <&pinctrl 50 84 6>,
  276. <&pinctrl 56 94 6>,
  277. <&pinctrl 62 72 1>,
  278. <&pinctrl 63 70 1>,
  279. <&pinctrl 64 80 1>,
  280. <&pinctrl 65 74 3>,
  281. <&pinctrl 68 78 1>,
  282. <&pinctrl 69 82 1>,
  283. <&pinctrl 70 156 17>,
  284. <&pinctrl 87 104 12>,
  285. <&pinctrl 99 102 2>,
  286. <&pinctrl 101 90 4>,
  287. <&pinctrl 105 116 6>,
  288. <&pinctrl 111 100 2>,
  289. <&pinctrl 113 122 4>,
  290. <&pinctrl 123 11 1>,
  291. <&pinctrl 124 38 4>,
  292. <&pinctrl 128 43 1>,
  293. <&pinctrl 129 47 1>,
  294. <&pinctrl 130 49 1>,
  295. <&pinctrl 131 53 1>,
  296. <&pinctrl 132 55 1>,
  297. <&pinctrl 133 59 1>,
  298. <&pinctrl 134 63 1>,
  299. <&pinctrl 135 67 1>,
  300. <&pinctrl 136 71 1>,
  301. <&pinctrl 137 73 1>,
  302. <&pinctrl 138 77 1>,
  303. <&pinctrl 139 79 1>,
  304. <&pinctrl 140 81 1>,
  305. <&pinctrl 141 83 1>,
  306. <&pinctrl 142 10 1>;
  307. };
  308. ts_adc_syscon: ts_adc_syscon@180a6000 {
  309. compatible = "brcm,iproc-ts-adc-syscon", "syscon";
  310. reg = <0x180a6000 0xc30>;
  311. };
  312. touchscreen: touchscreen@180a6000 {
  313. compatible = "brcm,iproc-touchscreen";
  314. #address-cells = <1>;
  315. #size-cells = <1>;
  316. ts_syscon = <&ts_adc_syscon>;
  317. clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
  318. clock-names = "tsc_clk";
  319. interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
  320. status = "disabled";
  321. };
  322. adc: adc@180a6000 {
  323. compatible = "brcm,iproc-static-adc";
  324. #io-channel-cells = <1>;
  325. io-channel-ranges;
  326. adc-syscon = <&ts_adc_syscon>;
  327. clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
  328. clock-names = "tsc_clk";
  329. interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
  330. status = "disabled";
  331. };
  332. };
  333. };