at91sam9x5.dtsi 34 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286
  1. /*
  2. * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
  3. * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
  4. * AT91SAM9X25, AT91SAM9X35 SoC
  5. *
  6. * Copyright (C) 2012 Atmel,
  7. * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. #include "skeleton.dtsi"
  12. #include <dt-bindings/dma/at91.h>
  13. #include <dt-bindings/pinctrl/at91.h>
  14. #include <dt-bindings/interrupt-controller/irq.h>
  15. #include <dt-bindings/gpio/gpio.h>
  16. #include <dt-bindings/clock/at91.h>
  17. / {
  18. model = "Atmel AT91SAM9x5 family SoC";
  19. compatible = "atmel,at91sam9x5";
  20. interrupt-parent = <&aic>;
  21. aliases {
  22. serial0 = &dbgu;
  23. serial1 = &usart0;
  24. serial2 = &usart1;
  25. serial3 = &usart2;
  26. gpio0 = &pioA;
  27. gpio1 = &pioB;
  28. gpio2 = &pioC;
  29. gpio3 = &pioD;
  30. tcb0 = &tcb0;
  31. tcb1 = &tcb1;
  32. i2c0 = &i2c0;
  33. i2c1 = &i2c1;
  34. i2c2 = &i2c2;
  35. ssc0 = &ssc0;
  36. pwm0 = &pwm0;
  37. };
  38. cpus {
  39. #address-cells = <0>;
  40. #size-cells = <0>;
  41. cpu {
  42. compatible = "arm,arm926ej-s";
  43. device_type = "cpu";
  44. };
  45. };
  46. memory {
  47. reg = <0x20000000 0x10000000>;
  48. };
  49. clocks {
  50. slow_xtal: slow_xtal {
  51. compatible = "fixed-clock";
  52. #clock-cells = <0>;
  53. clock-frequency = <0>;
  54. };
  55. main_xtal: main_xtal {
  56. compatible = "fixed-clock";
  57. #clock-cells = <0>;
  58. clock-frequency = <0>;
  59. };
  60. adc_op_clk: adc_op_clk{
  61. compatible = "fixed-clock";
  62. #clock-cells = <0>;
  63. clock-frequency = <1000000>;
  64. };
  65. };
  66. sram: sram@00300000 {
  67. compatible = "mmio-sram";
  68. reg = <0x00300000 0x8000>;
  69. };
  70. ahb {
  71. compatible = "simple-bus";
  72. #address-cells = <1>;
  73. #size-cells = <1>;
  74. ranges;
  75. apb {
  76. compatible = "simple-bus";
  77. #address-cells = <1>;
  78. #size-cells = <1>;
  79. ranges;
  80. aic: interrupt-controller@fffff000 {
  81. #interrupt-cells = <3>;
  82. compatible = "atmel,at91rm9200-aic";
  83. interrupt-controller;
  84. reg = <0xfffff000 0x200>;
  85. atmel,external-irqs = <31>;
  86. };
  87. ramc0: ramc@ffffe800 {
  88. compatible = "atmel,at91sam9g45-ddramc";
  89. reg = <0xffffe800 0x200>;
  90. clocks = <&ddrck>;
  91. clock-names = "ddrck";
  92. };
  93. pmc: pmc@fffffc00 {
  94. compatible = "atmel,at91sam9x5-pmc", "syscon";
  95. reg = <0xfffffc00 0x200>;
  96. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  97. interrupt-controller;
  98. #address-cells = <1>;
  99. #size-cells = <0>;
  100. #interrupt-cells = <1>;
  101. main_rc_osc: main_rc_osc {
  102. compatible = "atmel,at91sam9x5-clk-main-rc-osc";
  103. #clock-cells = <0>;
  104. interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
  105. clock-frequency = <12000000>;
  106. clock-accuracy = <50000000>;
  107. };
  108. main_osc: main_osc {
  109. compatible = "atmel,at91rm9200-clk-main-osc";
  110. #clock-cells = <0>;
  111. interrupts-extended = <&pmc AT91_PMC_MOSCS>;
  112. clocks = <&main_xtal>;
  113. };
  114. main: mainck {
  115. compatible = "atmel,at91sam9x5-clk-main";
  116. #clock-cells = <0>;
  117. interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
  118. clocks = <&main_rc_osc>, <&main_osc>;
  119. };
  120. plla: pllack {
  121. compatible = "atmel,at91rm9200-clk-pll";
  122. #clock-cells = <0>;
  123. interrupts-extended = <&pmc AT91_PMC_LOCKA>;
  124. clocks = <&main>;
  125. reg = <0>;
  126. atmel,clk-input-range = <2000000 32000000>;
  127. #atmel,pll-clk-output-range-cells = <4>;
  128. atmel,pll-clk-output-ranges = <745000000 800000000 0 0
  129. 695000000 750000000 1 0
  130. 645000000 700000000 2 0
  131. 595000000 650000000 3 0
  132. 545000000 600000000 0 1
  133. 495000000 555000000 1 1
  134. 445000000 500000000 2 1
  135. 400000000 450000000 3 1>;
  136. };
  137. plladiv: plladivck {
  138. compatible = "atmel,at91sam9x5-clk-plldiv";
  139. #clock-cells = <0>;
  140. clocks = <&plla>;
  141. };
  142. utmi: utmick {
  143. compatible = "atmel,at91sam9x5-clk-utmi";
  144. #clock-cells = <0>;
  145. interrupts-extended = <&pmc AT91_PMC_LOCKU>;
  146. clocks = <&main>;
  147. };
  148. mck: masterck {
  149. compatible = "atmel,at91sam9x5-clk-master";
  150. #clock-cells = <0>;
  151. interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
  152. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
  153. atmel,clk-output-range = <0 133333333>;
  154. atmel,clk-divisors = <1 2 4 3>;
  155. atmel,master-clk-have-div3-pres;
  156. };
  157. usb: usbck {
  158. compatible = "atmel,at91sam9x5-clk-usb";
  159. #clock-cells = <0>;
  160. clocks = <&plladiv>, <&utmi>;
  161. };
  162. prog: progck {
  163. compatible = "atmel,at91sam9x5-clk-programmable";
  164. #address-cells = <1>;
  165. #size-cells = <0>;
  166. interrupt-parent = <&pmc>;
  167. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
  168. prog0: prog0 {
  169. #clock-cells = <0>;
  170. reg = <0>;
  171. interrupts = <AT91_PMC_PCKRDY(0)>;
  172. };
  173. prog1: prog1 {
  174. #clock-cells = <0>;
  175. reg = <1>;
  176. interrupts = <AT91_PMC_PCKRDY(1)>;
  177. };
  178. };
  179. smd: smdclk {
  180. compatible = "atmel,at91sam9x5-clk-smd";
  181. #clock-cells = <0>;
  182. clocks = <&plladiv>, <&utmi>;
  183. };
  184. systemck {
  185. compatible = "atmel,at91rm9200-clk-system";
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. ddrck: ddrck {
  189. #clock-cells = <0>;
  190. reg = <2>;
  191. clocks = <&mck>;
  192. };
  193. smdck: smdck {
  194. #clock-cells = <0>;
  195. reg = <4>;
  196. clocks = <&smd>;
  197. };
  198. uhpck: uhpck {
  199. #clock-cells = <0>;
  200. reg = <6>;
  201. clocks = <&usb>;
  202. };
  203. udpck: udpck {
  204. #clock-cells = <0>;
  205. reg = <7>;
  206. clocks = <&usb>;
  207. };
  208. pck0: pck0 {
  209. #clock-cells = <0>;
  210. reg = <8>;
  211. clocks = <&prog0>;
  212. };
  213. pck1: pck1 {
  214. #clock-cells = <0>;
  215. reg = <9>;
  216. clocks = <&prog1>;
  217. };
  218. };
  219. periphck {
  220. compatible = "atmel,at91sam9x5-clk-peripheral";
  221. #address-cells = <1>;
  222. #size-cells = <0>;
  223. clocks = <&mck>;
  224. pioAB_clk: pioAB_clk {
  225. #clock-cells = <0>;
  226. reg = <2>;
  227. };
  228. pioCD_clk: pioCD_clk {
  229. #clock-cells = <0>;
  230. reg = <3>;
  231. };
  232. smd_clk: smd_clk {
  233. #clock-cells = <0>;
  234. reg = <4>;
  235. };
  236. usart0_clk: usart0_clk {
  237. #clock-cells = <0>;
  238. reg = <5>;
  239. };
  240. usart1_clk: usart1_clk {
  241. #clock-cells = <0>;
  242. reg = <6>;
  243. };
  244. usart2_clk: usart2_clk {
  245. #clock-cells = <0>;
  246. reg = <7>;
  247. };
  248. twi0_clk: twi0_clk {
  249. reg = <9>;
  250. #clock-cells = <0>;
  251. };
  252. twi1_clk: twi1_clk {
  253. #clock-cells = <0>;
  254. reg = <10>;
  255. };
  256. twi2_clk: twi2_clk {
  257. #clock-cells = <0>;
  258. reg = <11>;
  259. };
  260. mci0_clk: mci0_clk {
  261. #clock-cells = <0>;
  262. reg = <12>;
  263. };
  264. spi0_clk: spi0_clk {
  265. #clock-cells = <0>;
  266. reg = <13>;
  267. };
  268. spi1_clk: spi1_clk {
  269. #clock-cells = <0>;
  270. reg = <14>;
  271. };
  272. uart0_clk: uart0_clk {
  273. #clock-cells = <0>;
  274. reg = <15>;
  275. };
  276. uart1_clk: uart1_clk {
  277. #clock-cells = <0>;
  278. reg = <16>;
  279. };
  280. tcb0_clk: tcb0_clk {
  281. #clock-cells = <0>;
  282. reg = <17>;
  283. };
  284. pwm_clk: pwm_clk {
  285. #clock-cells = <0>;
  286. reg = <18>;
  287. };
  288. adc_clk: adc_clk {
  289. #clock-cells = <0>;
  290. reg = <19>;
  291. };
  292. dma0_clk: dma0_clk {
  293. #clock-cells = <0>;
  294. reg = <20>;
  295. };
  296. dma1_clk: dma1_clk {
  297. #clock-cells = <0>;
  298. reg = <21>;
  299. };
  300. uhphs_clk: uhphs_clk {
  301. #clock-cells = <0>;
  302. reg = <22>;
  303. };
  304. udphs_clk: udphs_clk {
  305. #clock-cells = <0>;
  306. reg = <23>;
  307. };
  308. mci1_clk: mci1_clk {
  309. #clock-cells = <0>;
  310. reg = <26>;
  311. };
  312. ssc0_clk: ssc0_clk {
  313. #clock-cells = <0>;
  314. reg = <28>;
  315. };
  316. };
  317. };
  318. rstc@fffffe00 {
  319. compatible = "atmel,at91sam9g45-rstc";
  320. reg = <0xfffffe00 0x10>;
  321. clocks = <&clk32k>;
  322. };
  323. shdwc@fffffe10 {
  324. compatible = "atmel,at91sam9x5-shdwc";
  325. reg = <0xfffffe10 0x10>;
  326. clocks = <&clk32k>;
  327. };
  328. pit: timer@fffffe30 {
  329. compatible = "atmel,at91sam9260-pit";
  330. reg = <0xfffffe30 0xf>;
  331. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  332. clocks = <&mck>;
  333. };
  334. sckc@fffffe50 {
  335. compatible = "atmel,at91sam9x5-sckc";
  336. reg = <0xfffffe50 0x4>;
  337. slow_osc: slow_osc {
  338. compatible = "atmel,at91sam9x5-clk-slow-osc";
  339. #clock-cells = <0>;
  340. clocks = <&slow_xtal>;
  341. };
  342. slow_rc_osc: slow_rc_osc {
  343. compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
  344. #clock-cells = <0>;
  345. clock-frequency = <32768>;
  346. clock-accuracy = <50000000>;
  347. };
  348. clk32k: slck {
  349. compatible = "atmel,at91sam9x5-clk-slow";
  350. #clock-cells = <0>;
  351. clocks = <&slow_rc_osc>, <&slow_osc>;
  352. };
  353. };
  354. tcb0: timer@f8008000 {
  355. compatible = "atmel,at91sam9x5-tcb";
  356. reg = <0xf8008000 0x100>;
  357. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
  358. clocks = <&tcb0_clk>, <&clk32k>;
  359. clock-names = "t0_clk", "slow_clk";
  360. };
  361. tcb1: timer@f800c000 {
  362. compatible = "atmel,at91sam9x5-tcb";
  363. reg = <0xf800c000 0x100>;
  364. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
  365. clocks = <&tcb0_clk>, <&clk32k>;
  366. clock-names = "t0_clk", "slow_clk";
  367. };
  368. dma0: dma-controller@ffffec00 {
  369. compatible = "atmel,at91sam9g45-dma";
  370. reg = <0xffffec00 0x200>;
  371. interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
  372. #dma-cells = <2>;
  373. clocks = <&dma0_clk>;
  374. clock-names = "dma_clk";
  375. };
  376. dma1: dma-controller@ffffee00 {
  377. compatible = "atmel,at91sam9g45-dma";
  378. reg = <0xffffee00 0x200>;
  379. interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
  380. #dma-cells = <2>;
  381. clocks = <&dma1_clk>;
  382. clock-names = "dma_clk";
  383. };
  384. pinctrl@fffff400 {
  385. #address-cells = <1>;
  386. #size-cells = <1>;
  387. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  388. ranges = <0xfffff400 0xfffff400 0x800>;
  389. /* shared pinctrl settings */
  390. dbgu {
  391. pinctrl_dbgu: dbgu-0 {
  392. atmel,pins =
  393. <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
  394. AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */
  395. };
  396. };
  397. usart0 {
  398. pinctrl_usart0: usart0-0 {
  399. atmel,pins =
  400. <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */
  401. AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA1 periph A */
  402. };
  403. pinctrl_usart0_rts: usart0_rts-0 {
  404. atmel,pins =
  405. <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
  406. };
  407. pinctrl_usart0_cts: usart0_cts-0 {
  408. atmel,pins =
  409. <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
  410. };
  411. pinctrl_usart0_sck: usart0_sck-0 {
  412. atmel,pins =
  413. <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */
  414. };
  415. };
  416. usart1 {
  417. pinctrl_usart1: usart1-0 {
  418. atmel,pins =
  419. <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */
  420. AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */
  421. };
  422. pinctrl_usart1_rts: usart1_rts-0 {
  423. atmel,pins =
  424. <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */
  425. };
  426. pinctrl_usart1_cts: usart1_cts-0 {
  427. atmel,pins =
  428. <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */
  429. };
  430. pinctrl_usart1_sck: usart1_sck-0 {
  431. atmel,pins =
  432. <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */
  433. };
  434. };
  435. usart2 {
  436. pinctrl_usart2: usart2-0 {
  437. atmel,pins =
  438. <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
  439. AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */
  440. };
  441. pinctrl_usart2_rts: usart2_rts-0 {
  442. atmel,pins =
  443. <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
  444. };
  445. pinctrl_usart2_cts: usart2_cts-0 {
  446. atmel,pins =
  447. <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
  448. };
  449. pinctrl_usart2_sck: usart2_sck-0 {
  450. atmel,pins =
  451. <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */
  452. };
  453. };
  454. uart0 {
  455. pinctrl_uart0: uart0-0 {
  456. atmel,pins =
  457. <AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC8 periph C */
  458. AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC9 periph C with pullup */
  459. };
  460. };
  461. uart1 {
  462. pinctrl_uart1: uart1-0 {
  463. atmel,pins =
  464. <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC16 periph C */
  465. AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC17 periph C with pullup */
  466. };
  467. };
  468. nand {
  469. pinctrl_nand: nand-0 {
  470. atmel,pins =
  471. <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */
  472. AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */
  473. AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */
  474. AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */
  475. AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */
  476. AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */
  477. AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */
  478. AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */
  479. AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */
  480. AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */
  481. AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */
  482. AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */
  483. AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */
  484. AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */
  485. };
  486. pinctrl_nand_16bits: nand_16bits-0 {
  487. atmel,pins =
  488. <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */
  489. AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */
  490. AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */
  491. AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */
  492. AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */
  493. AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */
  494. AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */
  495. AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */
  496. };
  497. };
  498. mmc0 {
  499. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  500. atmel,pins =
  501. <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
  502. AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
  503. AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
  504. };
  505. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  506. atmel,pins =
  507. <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
  508. AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
  509. AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
  510. };
  511. };
  512. mmc1 {
  513. pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
  514. atmel,pins =
  515. <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA13 periph B */
  516. AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
  517. AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA11 periph B with pullup */
  518. };
  519. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  520. atmel,pins =
  521. <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */
  522. AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */
  523. AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA4 periph B with pullup */
  524. };
  525. };
  526. ssc0 {
  527. pinctrl_ssc0_tx: ssc0_tx-0 {
  528. atmel,pins =
  529. <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
  530. AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
  531. AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
  532. };
  533. pinctrl_ssc0_rx: ssc0_rx-0 {
  534. atmel,pins =
  535. <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
  536. AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
  537. AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
  538. };
  539. };
  540. spi0 {
  541. pinctrl_spi0: spi0-0 {
  542. atmel,pins =
  543. <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
  544. AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
  545. AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
  546. };
  547. };
  548. spi1 {
  549. pinctrl_spi1: spi1-0 {
  550. atmel,pins =
  551. <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
  552. AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
  553. AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
  554. };
  555. };
  556. i2c0 {
  557. pinctrl_i2c0: i2c0-0 {
  558. atmel,pins =
  559. <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A I2C0 data */
  560. AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */
  561. };
  562. };
  563. i2c1 {
  564. pinctrl_i2c1: i2c1-0 {
  565. atmel,pins =
  566. <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */
  567. AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC1 periph C I2C1 clock */
  568. };
  569. };
  570. i2c2 {
  571. pinctrl_i2c2: i2c2-0 {
  572. atmel,pins =
  573. <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B I2C2 data */
  574. AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B I2C2 clock */
  575. };
  576. };
  577. i2c_gpio0 {
  578. pinctrl_i2c_gpio0: i2c_gpio0-0 {
  579. atmel,pins =
  580. <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */
  581. AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA31 gpio multidrive I2C0 clock */
  582. };
  583. };
  584. i2c_gpio1 {
  585. pinctrl_i2c_gpio1: i2c_gpio1-0 {
  586. atmel,pins =
  587. <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */
  588. AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PC1 gpio multidrive I2C1 clock */
  589. };
  590. };
  591. i2c_gpio2 {
  592. pinctrl_i2c_gpio2: i2c_gpio2-0 {
  593. atmel,pins =
  594. <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C2 data */
  595. AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C2 clock */
  596. };
  597. };
  598. pwm0 {
  599. pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
  600. atmel,pins =
  601. <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  602. };
  603. pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 {
  604. atmel,pins =
  605. <AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  606. };
  607. pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 {
  608. atmel,pins =
  609. <AT91_PIOC 18 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  610. };
  611. pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
  612. atmel,pins =
  613. <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  614. };
  615. pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 {
  616. atmel,pins =
  617. <AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  618. };
  619. pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 {
  620. atmel,pins =
  621. <AT91_PIOC 19 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  622. };
  623. pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
  624. atmel,pins =
  625. <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  626. };
  627. pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 {
  628. atmel,pins =
  629. <AT91_PIOC 20 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  630. };
  631. pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
  632. atmel,pins =
  633. <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  634. };
  635. pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 {
  636. atmel,pins =
  637. <AT91_PIOC 21 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  638. };
  639. };
  640. tcb0 {
  641. pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
  642. atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  643. };
  644. pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
  645. atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  646. };
  647. pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
  648. atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  649. };
  650. pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
  651. atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  652. };
  653. pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
  654. atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  655. };
  656. pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
  657. atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  658. };
  659. pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
  660. atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  661. };
  662. pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
  663. atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  664. };
  665. pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
  666. atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  667. };
  668. };
  669. tcb1 {
  670. pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
  671. atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  672. };
  673. pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
  674. atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  675. };
  676. pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
  677. atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  678. };
  679. pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
  680. atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  681. };
  682. pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
  683. atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  684. };
  685. pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
  686. atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  687. };
  688. pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
  689. atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  690. };
  691. pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
  692. atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  693. };
  694. pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
  695. atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  696. };
  697. };
  698. pioA: gpio@fffff400 {
  699. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  700. reg = <0xfffff400 0x200>;
  701. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  702. #gpio-cells = <2>;
  703. gpio-controller;
  704. interrupt-controller;
  705. #interrupt-cells = <2>;
  706. clocks = <&pioAB_clk>;
  707. };
  708. pioB: gpio@fffff600 {
  709. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  710. reg = <0xfffff600 0x200>;
  711. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  712. #gpio-cells = <2>;
  713. gpio-controller;
  714. #gpio-lines = <19>;
  715. interrupt-controller;
  716. #interrupt-cells = <2>;
  717. clocks = <&pioAB_clk>;
  718. };
  719. pioC: gpio@fffff800 {
  720. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  721. reg = <0xfffff800 0x200>;
  722. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  723. #gpio-cells = <2>;
  724. gpio-controller;
  725. interrupt-controller;
  726. #interrupt-cells = <2>;
  727. clocks = <&pioCD_clk>;
  728. };
  729. pioD: gpio@fffffa00 {
  730. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  731. reg = <0xfffffa00 0x200>;
  732. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  733. #gpio-cells = <2>;
  734. gpio-controller;
  735. #gpio-lines = <22>;
  736. interrupt-controller;
  737. #interrupt-cells = <2>;
  738. clocks = <&pioCD_clk>;
  739. };
  740. };
  741. ssc0: ssc@f0010000 {
  742. compatible = "atmel,at91sam9g45-ssc";
  743. reg = <0xf0010000 0x4000>;
  744. interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
  745. dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>,
  746. <&dma0 1 AT91_DMA_CFG_PER_ID(14)>;
  747. dma-names = "tx", "rx";
  748. pinctrl-names = "default";
  749. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  750. clocks = <&ssc0_clk>;
  751. clock-names = "pclk";
  752. status = "disabled";
  753. };
  754. mmc0: mmc@f0008000 {
  755. compatible = "atmel,hsmci";
  756. reg = <0xf0008000 0x600>;
  757. interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
  758. dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
  759. dma-names = "rxtx";
  760. pinctrl-names = "default";
  761. clocks = <&mci0_clk>;
  762. clock-names = "mci_clk";
  763. #address-cells = <1>;
  764. #size-cells = <0>;
  765. status = "disabled";
  766. };
  767. mmc1: mmc@f000c000 {
  768. compatible = "atmel,hsmci";
  769. reg = <0xf000c000 0x600>;
  770. interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
  771. dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
  772. dma-names = "rxtx";
  773. pinctrl-names = "default";
  774. clocks = <&mci1_clk>;
  775. clock-names = "mci_clk";
  776. #address-cells = <1>;
  777. #size-cells = <0>;
  778. status = "disabled";
  779. };
  780. dbgu: serial@fffff200 {
  781. compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
  782. reg = <0xfffff200 0x200>;
  783. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  784. pinctrl-names = "default";
  785. pinctrl-0 = <&pinctrl_dbgu>;
  786. dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
  787. <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
  788. dma-names = "tx", "rx";
  789. clocks = <&mck>;
  790. clock-names = "usart";
  791. status = "disabled";
  792. };
  793. usart0: serial@f801c000 {
  794. compatible = "atmel,at91sam9260-usart";
  795. reg = <0xf801c000 0x200>;
  796. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
  797. pinctrl-names = "default";
  798. pinctrl-0 = <&pinctrl_usart0>;
  799. dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,
  800. <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
  801. dma-names = "tx", "rx";
  802. clocks = <&usart0_clk>;
  803. clock-names = "usart";
  804. status = "disabled";
  805. };
  806. usart1: serial@f8020000 {
  807. compatible = "atmel,at91sam9260-usart";
  808. reg = <0xf8020000 0x200>;
  809. interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
  810. pinctrl-names = "default";
  811. pinctrl-0 = <&pinctrl_usart1>;
  812. dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,
  813. <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
  814. dma-names = "tx", "rx";
  815. clocks = <&usart1_clk>;
  816. clock-names = "usart";
  817. status = "disabled";
  818. };
  819. usart2: serial@f8024000 {
  820. compatible = "atmel,at91sam9260-usart";
  821. reg = <0xf8024000 0x200>;
  822. interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
  823. pinctrl-names = "default";
  824. pinctrl-0 = <&pinctrl_usart2>;
  825. dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,
  826. <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
  827. dma-names = "tx", "rx";
  828. clocks = <&usart2_clk>;
  829. clock-names = "usart";
  830. status = "disabled";
  831. };
  832. i2c0: i2c@f8010000 {
  833. compatible = "atmel,at91sam9x5-i2c";
  834. reg = <0xf8010000 0x100>;
  835. interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
  836. dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,
  837. <&dma0 1 AT91_DMA_CFG_PER_ID(8)>;
  838. dma-names = "tx", "rx";
  839. #address-cells = <1>;
  840. #size-cells = <0>;
  841. pinctrl-names = "default";
  842. pinctrl-0 = <&pinctrl_i2c0>;
  843. clocks = <&twi0_clk>;
  844. status = "disabled";
  845. };
  846. i2c1: i2c@f8014000 {
  847. compatible = "atmel,at91sam9x5-i2c";
  848. reg = <0xf8014000 0x100>;
  849. interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
  850. dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,
  851. <&dma1 1 AT91_DMA_CFG_PER_ID(6)>;
  852. dma-names = "tx", "rx";
  853. #address-cells = <1>;
  854. #size-cells = <0>;
  855. pinctrl-names = "default";
  856. pinctrl-0 = <&pinctrl_i2c1>;
  857. clocks = <&twi1_clk>;
  858. status = "disabled";
  859. };
  860. i2c2: i2c@f8018000 {
  861. compatible = "atmel,at91sam9x5-i2c";
  862. reg = <0xf8018000 0x100>;
  863. interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
  864. dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,
  865. <&dma0 1 AT91_DMA_CFG_PER_ID(10)>;
  866. dma-names = "tx", "rx";
  867. #address-cells = <1>;
  868. #size-cells = <0>;
  869. pinctrl-names = "default";
  870. pinctrl-0 = <&pinctrl_i2c2>;
  871. clocks = <&twi2_clk>;
  872. status = "disabled";
  873. };
  874. uart0: serial@f8040000 {
  875. compatible = "atmel,at91sam9260-usart";
  876. reg = <0xf8040000 0x200>;
  877. interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
  878. pinctrl-names = "default";
  879. pinctrl-0 = <&pinctrl_uart0>;
  880. clocks = <&uart0_clk>;
  881. clock-names = "usart";
  882. status = "disabled";
  883. };
  884. uart1: serial@f8044000 {
  885. compatible = "atmel,at91sam9260-usart";
  886. reg = <0xf8044000 0x200>;
  887. interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
  888. pinctrl-names = "default";
  889. pinctrl-0 = <&pinctrl_uart1>;
  890. clocks = <&uart1_clk>;
  891. clock-names = "usart";
  892. status = "disabled";
  893. };
  894. adc0: adc@f804c000 {
  895. #address-cells = <1>;
  896. #size-cells = <0>;
  897. compatible = "atmel,at91sam9x5-adc";
  898. reg = <0xf804c000 0x100>;
  899. interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
  900. clocks = <&adc_clk>,
  901. <&adc_op_clk>;
  902. clock-names = "adc_clk", "adc_op_clk";
  903. atmel,adc-use-external-triggers;
  904. atmel,adc-channels-used = <0xffff>;
  905. atmel,adc-vref = <3300>;
  906. atmel,adc-startup-time = <40>;
  907. atmel,adc-sample-hold-time = <11>;
  908. atmel,adc-res = <8 10>;
  909. atmel,adc-res-names = "lowres", "highres";
  910. atmel,adc-use-res = "highres";
  911. trigger0 {
  912. trigger-name = "external-rising";
  913. trigger-value = <0x1>;
  914. trigger-external;
  915. };
  916. trigger1 {
  917. trigger-name = "external-falling";
  918. trigger-value = <0x2>;
  919. trigger-external;
  920. };
  921. trigger2 {
  922. trigger-name = "external-any";
  923. trigger-value = <0x3>;
  924. trigger-external;
  925. };
  926. trigger3 {
  927. trigger-name = "continuous";
  928. trigger-value = <0x6>;
  929. };
  930. };
  931. spi0: spi@f0000000 {
  932. #address-cells = <1>;
  933. #size-cells = <0>;
  934. compatible = "atmel,at91rm9200-spi";
  935. reg = <0xf0000000 0x100>;
  936. interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
  937. dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,
  938. <&dma0 1 AT91_DMA_CFG_PER_ID(2)>;
  939. dma-names = "tx", "rx";
  940. pinctrl-names = "default";
  941. pinctrl-0 = <&pinctrl_spi0>;
  942. clocks = <&spi0_clk>;
  943. clock-names = "spi_clk";
  944. status = "disabled";
  945. };
  946. spi1: spi@f0004000 {
  947. #address-cells = <1>;
  948. #size-cells = <0>;
  949. compatible = "atmel,at91rm9200-spi";
  950. reg = <0xf0004000 0x100>;
  951. interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
  952. dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,
  953. <&dma1 1 AT91_DMA_CFG_PER_ID(2)>;
  954. dma-names = "tx", "rx";
  955. pinctrl-names = "default";
  956. pinctrl-0 = <&pinctrl_spi1>;
  957. clocks = <&spi1_clk>;
  958. clock-names = "spi_clk";
  959. status = "disabled";
  960. };
  961. usb2: gadget@f803c000 {
  962. #address-cells = <1>;
  963. #size-cells = <0>;
  964. compatible = "atmel,at91sam9g45-udc";
  965. reg = <0x00500000 0x80000
  966. 0xf803c000 0x400>;
  967. interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
  968. clocks = <&utmi>, <&udphs_clk>;
  969. clock-names = "hclk", "pclk";
  970. status = "disabled";
  971. ep@0 {
  972. reg = <0>;
  973. atmel,fifo-size = <64>;
  974. atmel,nb-banks = <1>;
  975. };
  976. ep@1 {
  977. reg = <1>;
  978. atmel,fifo-size = <1024>;
  979. atmel,nb-banks = <2>;
  980. atmel,can-dma;
  981. atmel,can-isoc;
  982. };
  983. ep@2 {
  984. reg = <2>;
  985. atmel,fifo-size = <1024>;
  986. atmel,nb-banks = <2>;
  987. atmel,can-dma;
  988. atmel,can-isoc;
  989. };
  990. ep@3 {
  991. reg = <3>;
  992. atmel,fifo-size = <1024>;
  993. atmel,nb-banks = <3>;
  994. atmel,can-dma;
  995. };
  996. ep@4 {
  997. reg = <4>;
  998. atmel,fifo-size = <1024>;
  999. atmel,nb-banks = <3>;
  1000. atmel,can-dma;
  1001. };
  1002. ep@5 {
  1003. reg = <5>;
  1004. atmel,fifo-size = <1024>;
  1005. atmel,nb-banks = <3>;
  1006. atmel,can-dma;
  1007. atmel,can-isoc;
  1008. };
  1009. ep@6 {
  1010. reg = <6>;
  1011. atmel,fifo-size = <1024>;
  1012. atmel,nb-banks = <3>;
  1013. atmel,can-dma;
  1014. atmel,can-isoc;
  1015. };
  1016. };
  1017. watchdog@fffffe40 {
  1018. compatible = "atmel,at91sam9260-wdt";
  1019. reg = <0xfffffe40 0x10>;
  1020. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  1021. clocks = <&clk32k>;
  1022. atmel,watchdog-type = "hardware";
  1023. atmel,reset-type = "all";
  1024. atmel,dbg-halt;
  1025. status = "disabled";
  1026. };
  1027. rtc@fffffeb0 {
  1028. compatible = "atmel,at91sam9x5-rtc";
  1029. reg = <0xfffffeb0 0x40>;
  1030. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  1031. clocks = <&clk32k>;
  1032. status = "disabled";
  1033. };
  1034. pwm0: pwm@f8034000 {
  1035. compatible = "atmel,at91sam9rl-pwm";
  1036. reg = <0xf8034000 0x300>;
  1037. interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
  1038. clocks = <&pwm_clk>;
  1039. #pwm-cells = <3>;
  1040. status = "disabled";
  1041. };
  1042. };
  1043. nand0: nand@40000000 {
  1044. compatible = "atmel,at91rm9200-nand";
  1045. #address-cells = <1>;
  1046. #size-cells = <1>;
  1047. reg = <0x40000000 0x10000000
  1048. 0xffffe000 0x600 /* PMECC Registers */
  1049. 0xffffe600 0x200 /* PMECC Error Location Registers */
  1050. 0x00108000 0x18000 /* PMECC looup table in ROM code */
  1051. >;
  1052. atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
  1053. atmel,nand-addr-offset = <21>;
  1054. atmel,nand-cmd-offset = <22>;
  1055. atmel,nand-has-dma;
  1056. pinctrl-names = "default";
  1057. pinctrl-0 = <&pinctrl_nand>;
  1058. gpios = <&pioD 5 GPIO_ACTIVE_HIGH
  1059. &pioD 4 GPIO_ACTIVE_HIGH
  1060. 0
  1061. >;
  1062. status = "disabled";
  1063. };
  1064. usb0: ohci@00600000 {
  1065. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  1066. reg = <0x00600000 0x100000>;
  1067. interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
  1068. clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
  1069. clock-names = "ohci_clk", "hclk", "uhpck";
  1070. status = "disabled";
  1071. };
  1072. usb1: ehci@00700000 {
  1073. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  1074. reg = <0x00700000 0x100000>;
  1075. interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
  1076. clocks = <&utmi>, <&uhphs_clk>;
  1077. clock-names = "usb_clk", "ehci_clk";
  1078. status = "disabled";
  1079. };
  1080. };
  1081. i2c-gpio-0 {
  1082. compatible = "i2c-gpio";
  1083. gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
  1084. &pioA 31 GPIO_ACTIVE_HIGH /* scl */
  1085. >;
  1086. i2c-gpio,sda-open-drain;
  1087. i2c-gpio,scl-open-drain;
  1088. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  1089. #address-cells = <1>;
  1090. #size-cells = <0>;
  1091. pinctrl-names = "default";
  1092. pinctrl-0 = <&pinctrl_i2c_gpio0>;
  1093. status = "disabled";
  1094. };
  1095. i2c-gpio-1 {
  1096. compatible = "i2c-gpio";
  1097. gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
  1098. &pioC 1 GPIO_ACTIVE_HIGH /* scl */
  1099. >;
  1100. i2c-gpio,sda-open-drain;
  1101. i2c-gpio,scl-open-drain;
  1102. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  1103. #address-cells = <1>;
  1104. #size-cells = <0>;
  1105. pinctrl-names = "default";
  1106. pinctrl-0 = <&pinctrl_i2c_gpio1>;
  1107. status = "disabled";
  1108. };
  1109. i2c-gpio-2 {
  1110. compatible = "i2c-gpio";
  1111. gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
  1112. &pioB 5 GPIO_ACTIVE_HIGH /* scl */
  1113. >;
  1114. i2c-gpio,sda-open-drain;
  1115. i2c-gpio,scl-open-drain;
  1116. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  1117. #address-cells = <1>;
  1118. #size-cells = <0>;
  1119. pinctrl-names = "default";
  1120. pinctrl-0 = <&pinctrl_i2c_gpio2>;
  1121. status = "disabled";
  1122. };
  1123. };