at91sam9rl.dtsi 27 KB

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  1. /*
  2. * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
  3. *
  4. * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
  5. *
  6. * Licensed under GPLv2 or later.
  7. */
  8. #include "skeleton.dtsi"
  9. #include <dt-bindings/pinctrl/at91.h>
  10. #include <dt-bindings/clock/at91.h>
  11. #include <dt-bindings/interrupt-controller/irq.h>
  12. #include <dt-bindings/gpio/gpio.h>
  13. #include <dt-bindings/pwm/pwm.h>
  14. / {
  15. model = "Atmel AT91SAM9RL family SoC";
  16. compatible = "atmel,at91sam9rl", "atmel,at91sam9";
  17. interrupt-parent = <&aic>;
  18. aliases {
  19. serial0 = &dbgu;
  20. serial1 = &usart0;
  21. serial2 = &usart1;
  22. serial3 = &usart2;
  23. serial4 = &usart3;
  24. gpio0 = &pioA;
  25. gpio1 = &pioB;
  26. gpio2 = &pioC;
  27. gpio3 = &pioD;
  28. tcb0 = &tcb0;
  29. i2c0 = &i2c0;
  30. i2c1 = &i2c1;
  31. ssc0 = &ssc0;
  32. ssc1 = &ssc1;
  33. pwm0 = &pwm0;
  34. };
  35. cpus {
  36. #address-cells = <0>;
  37. #size-cells = <0>;
  38. cpu {
  39. compatible = "arm,arm926ej-s";
  40. device_type = "cpu";
  41. };
  42. };
  43. memory {
  44. reg = <0x20000000 0x04000000>;
  45. };
  46. clocks {
  47. slow_xtal: slow_xtal {
  48. compatible = "fixed-clock";
  49. #clock-cells = <0>;
  50. clock-frequency = <0>;
  51. };
  52. main_xtal: main_xtal {
  53. compatible = "fixed-clock";
  54. #clock-cells = <0>;
  55. clock-frequency = <0>;
  56. };
  57. adc_op_clk: adc_op_clk{
  58. compatible = "fixed-clock";
  59. #clock-cells = <0>;
  60. clock-frequency = <1000000>;
  61. };
  62. };
  63. sram: sram@00300000 {
  64. compatible = "mmio-sram";
  65. reg = <0x00300000 0x10000>;
  66. };
  67. ahb {
  68. compatible = "simple-bus";
  69. #address-cells = <1>;
  70. #size-cells = <1>;
  71. ranges;
  72. fb0: fb@00500000 {
  73. compatible = "atmel,at91sam9rl-lcdc";
  74. reg = <0x00500000 0x1000>;
  75. interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
  76. pinctrl-names = "default";
  77. pinctrl-0 = <&pinctrl_fb>;
  78. clocks = <&lcd_clk>, <&lcd_clk>;
  79. clock-names = "hclk", "lcdc_clk";
  80. status = "disabled";
  81. };
  82. nand0: nand@40000000 {
  83. compatible = "atmel,at91rm9200-nand";
  84. #address-cells = <1>;
  85. #size-cells = <1>;
  86. reg = <0x40000000 0x10000000>,
  87. <0xffffe800 0x200>;
  88. atmel,nand-addr-offset = <21>;
  89. atmel,nand-cmd-offset = <22>;
  90. atmel,nand-has-dma;
  91. pinctrl-names = "default";
  92. pinctrl-0 = <&pinctrl_nand>;
  93. gpios = <&pioD 17 GPIO_ACTIVE_HIGH>,
  94. <&pioB 6 GPIO_ACTIVE_HIGH>,
  95. <0>;
  96. status = "disabled";
  97. };
  98. apb {
  99. compatible = "simple-bus";
  100. #address-cells = <1>;
  101. #size-cells = <1>;
  102. ranges;
  103. tcb0: timer@fffa0000 {
  104. compatible = "atmel,at91rm9200-tcb";
  105. reg = <0xfffa0000 0x100>;
  106. interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
  107. <17 IRQ_TYPE_LEVEL_HIGH 0>,
  108. <18 IRQ_TYPE_LEVEL_HIGH 0>;
  109. clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
  110. clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
  111. };
  112. mmc0: mmc@fffa4000 {
  113. compatible = "atmel,hsmci";
  114. reg = <0xfffa4000 0x600>;
  115. interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
  116. #address-cells = <1>;
  117. #size-cells = <0>;
  118. pinctrl-names = "default";
  119. clocks = <&mci0_clk>;
  120. clock-names = "mci_clk";
  121. status = "disabled";
  122. };
  123. i2c0: i2c@fffa8000 {
  124. compatible = "atmel,at91sam9260-i2c";
  125. reg = <0xfffa8000 0x100>;
  126. interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
  127. #address-cells = <1>;
  128. #size-cells = <0>;
  129. clocks = <&twi0_clk>;
  130. status = "disabled";
  131. };
  132. i2c1: i2c@fffac000 {
  133. compatible = "atmel,at91sam9260-i2c";
  134. reg = <0xfffac000 0x100>;
  135. interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
  136. #address-cells = <1>;
  137. #size-cells = <0>;
  138. status = "disabled";
  139. };
  140. usart0: serial@fffb0000 {
  141. compatible = "atmel,at91sam9260-usart";
  142. reg = <0xfffb0000 0x200>;
  143. interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
  144. atmel,use-dma-rx;
  145. atmel,use-dma-tx;
  146. pinctrl-names = "default";
  147. pinctrl-0 = <&pinctrl_usart0>;
  148. clocks = <&usart0_clk>;
  149. clock-names = "usart";
  150. status = "disabled";
  151. };
  152. usart1: serial@fffb4000 {
  153. compatible = "atmel,at91sam9260-usart";
  154. reg = <0xfffb4000 0x200>;
  155. interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
  156. atmel,use-dma-rx;
  157. atmel,use-dma-tx;
  158. pinctrl-names = "default";
  159. pinctrl-0 = <&pinctrl_usart1>;
  160. clocks = <&usart1_clk>;
  161. clock-names = "usart";
  162. status = "disabled";
  163. };
  164. usart2: serial@fffb8000 {
  165. compatible = "atmel,at91sam9260-usart";
  166. reg = <0xfffb8000 0x200>;
  167. interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
  168. atmel,use-dma-rx;
  169. atmel,use-dma-tx;
  170. pinctrl-names = "default";
  171. pinctrl-0 = <&pinctrl_usart2>;
  172. clocks = <&usart2_clk>;
  173. clock-names = "usart";
  174. status = "disabled";
  175. };
  176. usart3: serial@fffbc000 {
  177. compatible = "atmel,at91sam9260-usart";
  178. reg = <0xfffbc000 0x200>;
  179. interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
  180. atmel,use-dma-rx;
  181. atmel,use-dma-tx;
  182. pinctrl-names = "default";
  183. pinctrl-0 = <&pinctrl_usart3>;
  184. clocks = <&usart3_clk>;
  185. clock-names = "usart";
  186. status = "disabled";
  187. };
  188. ssc0: ssc@fffc0000 {
  189. compatible = "atmel,at91sam9rl-ssc";
  190. reg = <0xfffc0000 0x4000>;
  191. interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
  192. pinctrl-names = "default";
  193. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  194. status = "disabled";
  195. };
  196. ssc1: ssc@fffc4000 {
  197. compatible = "atmel,at91sam9rl-ssc";
  198. reg = <0xfffc4000 0x4000>;
  199. interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
  200. pinctrl-names = "default";
  201. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  202. status = "disabled";
  203. };
  204. pwm0: pwm@fffc8000 {
  205. compatible = "atmel,at91sam9rl-pwm";
  206. reg = <0xfffc8000 0x300>;
  207. interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
  208. #pwm-cells = <3>;
  209. clocks = <&pwm_clk>;
  210. clock-names = "pwm_clk";
  211. status = "disabled";
  212. };
  213. spi0: spi@fffcc000 {
  214. #address-cells = <1>;
  215. #size-cells = <0>;
  216. compatible = "atmel,at91rm9200-spi";
  217. reg = <0xfffcc000 0x200>;
  218. interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
  219. pinctrl-names = "default";
  220. pinctrl-0 = <&pinctrl_spi0>;
  221. clocks = <&spi0_clk>;
  222. clock-names = "spi_clk";
  223. status = "disabled";
  224. };
  225. adc0: adc@fffd0000 {
  226. #address-cells = <1>;
  227. #size-cells = <0>;
  228. compatible = "atmel,at91sam9rl-adc";
  229. reg = <0xfffd0000 0x100>;
  230. interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
  231. clocks = <&adc_clk>, <&adc_op_clk>;
  232. clock-names = "adc_clk", "adc_op_clk";
  233. atmel,adc-use-external-triggers;
  234. atmel,adc-channels-used = <0x3f>;
  235. atmel,adc-vref = <3300>;
  236. atmel,adc-startup-time = <40>;
  237. atmel,adc-res = <8 10>;
  238. atmel,adc-res-names = "lowres", "highres";
  239. atmel,adc-use-res = "highres";
  240. trigger0 {
  241. trigger-name = "timer-counter-0";
  242. trigger-value = <0x1>;
  243. };
  244. trigger1 {
  245. trigger-name = "timer-counter-1";
  246. trigger-value = <0x3>;
  247. };
  248. trigger2 {
  249. trigger-name = "timer-counter-2";
  250. trigger-value = <0x5>;
  251. };
  252. trigger3 {
  253. trigger-name = "external";
  254. trigger-value = <0x13>;
  255. trigger-external;
  256. };
  257. };
  258. usb0: gadget@fffd4000 {
  259. #address-cells = <1>;
  260. #size-cells = <0>;
  261. compatible = "atmel,at91sam9rl-udc";
  262. reg = <0x00600000 0x100000>,
  263. <0xfffd4000 0x4000>;
  264. interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
  265. clocks = <&udphs_clk>, <&utmi>;
  266. clock-names = "pclk", "hclk";
  267. status = "disabled";
  268. ep@0 {
  269. reg = <0>;
  270. atmel,fifo-size = <64>;
  271. atmel,nb-banks = <1>;
  272. };
  273. ep@1 {
  274. reg = <1>;
  275. atmel,fifo-size = <1024>;
  276. atmel,nb-banks = <2>;
  277. atmel,can-dma;
  278. atmel,can-isoc;
  279. };
  280. ep@2 {
  281. reg = <2>;
  282. atmel,fifo-size = <1024>;
  283. atmel,nb-banks = <2>;
  284. atmel,can-dma;
  285. atmel,can-isoc;
  286. };
  287. ep@3 {
  288. reg = <3>;
  289. atmel,fifo-size = <1024>;
  290. atmel,nb-banks = <3>;
  291. atmel,can-dma;
  292. };
  293. ep@4 {
  294. reg = <4>;
  295. atmel,fifo-size = <1024>;
  296. atmel,nb-banks = <3>;
  297. atmel,can-dma;
  298. };
  299. ep@5 {
  300. reg = <5>;
  301. atmel,fifo-size = <1024>;
  302. atmel,nb-banks = <3>;
  303. atmel,can-dma;
  304. atmel,can-isoc;
  305. };
  306. ep@6 {
  307. reg = <6>;
  308. atmel,fifo-size = <1024>;
  309. atmel,nb-banks = <3>;
  310. atmel,can-dma;
  311. atmel,can-isoc;
  312. };
  313. };
  314. dma0: dma-controller@ffffe600 {
  315. compatible = "atmel,at91sam9rl-dma";
  316. reg = <0xffffe600 0x200>;
  317. interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
  318. #dma-cells = <2>;
  319. clocks = <&dma0_clk>;
  320. clock-names = "dma_clk";
  321. };
  322. ramc0: ramc@ffffea00 {
  323. compatible = "atmel,at91sam9260-sdramc";
  324. reg = <0xffffea00 0x200>;
  325. };
  326. aic: interrupt-controller@fffff000 {
  327. #interrupt-cells = <3>;
  328. compatible = "atmel,at91rm9200-aic";
  329. interrupt-controller;
  330. reg = <0xfffff000 0x200>;
  331. atmel,external-irqs = <31>;
  332. };
  333. dbgu: serial@fffff200 {
  334. compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
  335. reg = <0xfffff200 0x200>;
  336. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  337. pinctrl-names = "default";
  338. pinctrl-0 = <&pinctrl_dbgu>;
  339. clocks = <&mck>;
  340. clock-names = "usart";
  341. status = "disabled";
  342. };
  343. pinctrl@fffff400 {
  344. #address-cells = <1>;
  345. #size-cells = <1>;
  346. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  347. ranges = <0xfffff400 0xfffff400 0x800>;
  348. atmel,mux-mask =
  349. /* A B */
  350. <0xffffffff 0xe05c6738>, /* pioA */
  351. <0xffffffff 0x0000c780>, /* pioB */
  352. <0xffffffff 0xe3ffff0e>, /* pioC */
  353. <0x003fffff 0x0001ff3c>; /* pioD */
  354. /* shared pinctrl settings */
  355. adc0 {
  356. pinctrl_adc0_ts: adc0_ts-0 {
  357. atmel,pins =
  358. <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  359. <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  360. <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  361. <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  362. };
  363. pinctrl_adc0_ad0: adc0_ad0-0 {
  364. atmel,pins = <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  365. };
  366. pinctrl_adc0_ad1: adc0_ad1-0 {
  367. atmel,pins = <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  368. };
  369. pinctrl_adc0_ad2: adc0_ad2-0 {
  370. atmel,pins = <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  371. };
  372. pinctrl_adc0_ad3: adc0_ad3-0 {
  373. atmel,pins = <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  374. };
  375. pinctrl_adc0_ad4: adc0_ad4-0 {
  376. atmel,pins = <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  377. };
  378. pinctrl_adc0_ad5: adc0_ad5-0 {
  379. atmel,pins = <AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  380. };
  381. pinctrl_adc0_adtrg: adc0_adtrg-0 {
  382. atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  383. };
  384. };
  385. dbgu {
  386. pinctrl_dbgu: dbgu-0 {
  387. atmel,pins =
  388. <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  389. <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
  390. };
  391. };
  392. fb {
  393. pinctrl_fb: fb-0 {
  394. atmel,pins =
  395. <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  396. <AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  397. <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  398. <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  399. <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  400. <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  401. <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  402. <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  403. <AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  404. <AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  405. <AT91_PIOC 15 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  406. <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  407. <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  408. <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  409. <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  410. <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  411. <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  412. <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  413. <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  414. <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  415. <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  416. };
  417. };
  418. i2c_gpio0 {
  419. pinctrl_i2c_gpio0: i2c_gpio0-0 {
  420. atmel,pins =
  421. <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>,
  422. <AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
  423. };
  424. };
  425. i2c_gpio1 {
  426. pinctrl_i2c_gpio1: i2c_gpio1-0 {
  427. atmel,pins =
  428. <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>,
  429. <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
  430. };
  431. };
  432. mmc0 {
  433. pinctrl_mmc0_clk: mmc0_clk-0 {
  434. atmel,pins =
  435. <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  436. };
  437. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  438. atmel,pins =
  439. <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
  440. <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
  441. };
  442. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  443. atmel,pins =
  444. <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
  445. <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
  446. <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
  447. };
  448. };
  449. nand {
  450. pinctrl_nand: nand-0 {
  451. atmel,pins =
  452. <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>,
  453. <AT91_PIOB 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
  454. };
  455. pinctrl_nand0_ale_cle: nand_ale_cle-0 {
  456. atmel,pins =
  457. <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  458. <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  459. };
  460. pinctrl_nand0_oe_we: nand_oe_we-0 {
  461. atmel,pins =
  462. <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  463. <AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  464. };
  465. pinctrl_nand0_cs: nand_cs-0 {
  466. atmel,pins =
  467. <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  468. };
  469. };
  470. pwm0 {
  471. pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
  472. atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  473. };
  474. pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 {
  475. atmel,pins = <AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  476. };
  477. pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 {
  478. atmel,pins = <AT91_PIOD 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  479. };
  480. pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
  481. atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  482. };
  483. pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 {
  484. atmel,pins = <AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  485. };
  486. pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 {
  487. atmel,pins = <AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  488. };
  489. pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
  490. atmel,pins = <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  491. };
  492. pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 {
  493. atmel,pins = <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  494. };
  495. pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 {
  496. atmel,pins = <AT91_PIOD 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  497. };
  498. pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
  499. atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  500. };
  501. pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 {
  502. atmel,pins = <AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  503. };
  504. };
  505. spi0 {
  506. pinctrl_spi0: spi0-0 {
  507. atmel,pins =
  508. <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  509. <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  510. <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  511. };
  512. };
  513. ssc0 {
  514. pinctrl_ssc0_tx: ssc0_tx-0 {
  515. atmel,pins =
  516. <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  517. <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  518. <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  519. };
  520. pinctrl_ssc0_rx: ssc0_rx-0 {
  521. atmel,pins =
  522. <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  523. <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  524. <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  525. };
  526. };
  527. ssc1 {
  528. pinctrl_ssc1_tx: ssc1_tx-0 {
  529. atmel,pins =
  530. <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  531. <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  532. <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  533. };
  534. pinctrl_ssc1_rx: ssc1_rx-0 {
  535. atmel,pins =
  536. <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  537. <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  538. <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  539. };
  540. };
  541. tcb0 {
  542. pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
  543. atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  544. };
  545. pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
  546. atmel,pins = <AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  547. };
  548. pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
  549. atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  550. };
  551. pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
  552. atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  553. };
  554. pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
  555. atmel,pins = <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  556. };
  557. pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
  558. atmel,pins = <AT91_PIOD 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  559. };
  560. pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
  561. atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  562. };
  563. pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
  564. atmel,pins = <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  565. };
  566. pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
  567. atmel,pins = <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  568. };
  569. };
  570. usart0 {
  571. pinctrl_usart0: usart0-0 {
  572. atmel,pins =
  573. <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  574. <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
  575. };
  576. pinctrl_usart0_rts: usart0_rts-0 {
  577. atmel,pins =
  578. <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  579. };
  580. pinctrl_usart0_cts: usart0_cts-0 {
  581. atmel,pins =
  582. <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  583. };
  584. pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
  585. atmel,pins =
  586. <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  587. <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  588. };
  589. pinctrl_usart0_dcd: usart0_dcd-0 {
  590. atmel,pins =
  591. <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  592. };
  593. pinctrl_usart0_ri: usart0_ri-0 {
  594. atmel,pins =
  595. <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  596. };
  597. pinctrl_usart0_sck: usart0_sck-0 {
  598. atmel,pins =
  599. <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  600. };
  601. };
  602. usart1 {
  603. pinctrl_usart1: usart1-0 {
  604. atmel,pins =
  605. <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
  606. <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  607. };
  608. pinctrl_usart1_rts: usart1_rts-0 {
  609. atmel,pins =
  610. <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  611. };
  612. pinctrl_usart1_cts: usart1_cts-0 {
  613. atmel,pins =
  614. <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  615. };
  616. pinctrl_usart1_sck: usart1_sck-0 {
  617. atmel,pins =
  618. <AT91_PIOD 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  619. };
  620. };
  621. usart2 {
  622. pinctrl_usart2: usart2-0 {
  623. atmel,pins =
  624. <AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
  625. <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  626. };
  627. pinctrl_usart2_rts: usart2_rts-0 {
  628. atmel,pins =
  629. <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  630. };
  631. pinctrl_usart2_cts: usart2_cts-0 {
  632. atmel,pins =
  633. <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  634. };
  635. pinctrl_usart2_sck: usart2_sck-0 {
  636. atmel,pins =
  637. <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  638. };
  639. };
  640. usart3 {
  641. pinctrl_usart3: usart3-0 {
  642. atmel,pins =
  643. <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
  644. <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  645. };
  646. pinctrl_usart3_rts: usart3_rts-0 {
  647. atmel,pins =
  648. <AT91_PIOD 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  649. };
  650. pinctrl_usart3_cts: usart3_cts-0 {
  651. atmel,pins =
  652. <AT91_PIOD 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  653. };
  654. pinctrl_usart3_sck: usart3_sck-0 {
  655. atmel,pins =
  656. <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  657. };
  658. };
  659. pioA: gpio@fffff400 {
  660. compatible = "atmel,at91rm9200-gpio";
  661. reg = <0xfffff400 0x200>;
  662. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  663. #gpio-cells = <2>;
  664. gpio-controller;
  665. interrupt-controller;
  666. #interrupt-cells = <2>;
  667. clocks = <&pioA_clk>;
  668. };
  669. pioB: gpio@fffff600 {
  670. compatible = "atmel,at91rm9200-gpio";
  671. reg = <0xfffff600 0x200>;
  672. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  673. #gpio-cells = <2>;
  674. gpio-controller;
  675. interrupt-controller;
  676. #interrupt-cells = <2>;
  677. clocks = <&pioB_clk>;
  678. };
  679. pioC: gpio@fffff800 {
  680. compatible = "atmel,at91rm9200-gpio";
  681. reg = <0xfffff800 0x200>;
  682. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
  683. #gpio-cells = <2>;
  684. gpio-controller;
  685. interrupt-controller;
  686. #interrupt-cells = <2>;
  687. clocks = <&pioC_clk>;
  688. };
  689. pioD: gpio@fffffa00 {
  690. compatible = "atmel,at91rm9200-gpio";
  691. reg = <0xfffffa00 0x200>;
  692. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
  693. #gpio-cells = <2>;
  694. gpio-controller;
  695. interrupt-controller;
  696. #interrupt-cells = <2>;
  697. clocks = <&pioD_clk>;
  698. };
  699. };
  700. pmc: pmc@fffffc00 {
  701. compatible = "atmel,at91sam9g45-pmc", "syscon";
  702. reg = <0xfffffc00 0x100>;
  703. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  704. interrupt-controller;
  705. #address-cells = <1>;
  706. #size-cells = <0>;
  707. #interrupt-cells = <1>;
  708. main: mainck {
  709. compatible = "atmel,at91rm9200-clk-main";
  710. #clock-cells = <0>;
  711. interrupts-extended = <&pmc AT91_PMC_MOSCS>;
  712. clocks = <&main_xtal>;
  713. };
  714. plla: pllack {
  715. compatible = "atmel,at91rm9200-clk-pll";
  716. #clock-cells = <0>;
  717. interrupts-extended = <&pmc AT91_PMC_LOCKA>;
  718. clocks = <&main>;
  719. reg = <0>;
  720. atmel,clk-input-range = <1000000 32000000>;
  721. #atmel,pll-clk-output-range-cells = <3>;
  722. atmel,pll-clk-output-ranges = <80000000 200000000 0>,
  723. <190000000 240000000 2>;
  724. };
  725. utmi: utmick {
  726. compatible = "atmel,at91sam9x5-clk-utmi";
  727. #clock-cells = <0>;
  728. interrupt-parent = <&pmc>;
  729. interrupts = <AT91_PMC_LOCKU>;
  730. clocks = <&main>;
  731. };
  732. mck: masterck {
  733. compatible = "atmel,at91rm9200-clk-master";
  734. #clock-cells = <0>;
  735. interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
  736. clocks = <&clk32k>, <&main>, <&plla>, <&utmi>;
  737. atmel,clk-output-range = <0 94000000>;
  738. atmel,clk-divisors = <1 2 4 0>;
  739. };
  740. prog: progck {
  741. compatible = "atmel,at91rm9200-clk-programmable";
  742. #address-cells = <1>;
  743. #size-cells = <0>;
  744. interrupt-parent = <&pmc>;
  745. clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>;
  746. prog0: prog0 {
  747. #clock-cells = <0>;
  748. reg = <0>;
  749. interrupts = <AT91_PMC_PCKRDY(0)>;
  750. };
  751. prog1: prog1 {
  752. #clock-cells = <0>;
  753. reg = <1>;
  754. interrupts = <AT91_PMC_PCKRDY(1)>;
  755. };
  756. };
  757. systemck {
  758. compatible = "atmel,at91rm9200-clk-system";
  759. #address-cells = <1>;
  760. #size-cells = <0>;
  761. pck0: pck0 {
  762. #clock-cells = <0>;
  763. reg = <8>;
  764. clocks = <&prog0>;
  765. };
  766. pck1: pck1 {
  767. #clock-cells = <0>;
  768. reg = <9>;
  769. clocks = <&prog1>;
  770. };
  771. };
  772. periphck {
  773. compatible = "atmel,at91rm9200-clk-peripheral";
  774. #address-cells = <1>;
  775. #size-cells = <0>;
  776. clocks = <&mck>;
  777. pioA_clk: pioA_clk {
  778. #clock-cells = <0>;
  779. reg = <2>;
  780. };
  781. pioB_clk: pioB_clk {
  782. #clock-cells = <0>;
  783. reg = <3>;
  784. };
  785. pioC_clk: pioC_clk {
  786. #clock-cells = <0>;
  787. reg = <4>;
  788. };
  789. pioD_clk: pioD_clk {
  790. #clock-cells = <0>;
  791. reg = <5>;
  792. };
  793. usart0_clk: usart0_clk {
  794. #clock-cells = <0>;
  795. reg = <6>;
  796. };
  797. usart1_clk: usart1_clk {
  798. #clock-cells = <0>;
  799. reg = <7>;
  800. };
  801. usart2_clk: usart2_clk {
  802. #clock-cells = <0>;
  803. reg = <8>;
  804. };
  805. usart3_clk: usart3_clk {
  806. #clock-cells = <0>;
  807. reg = <9>;
  808. };
  809. mci0_clk: mci0_clk {
  810. #clock-cells = <0>;
  811. reg = <10>;
  812. };
  813. twi0_clk: twi0_clk {
  814. #clock-cells = <0>;
  815. reg = <11>;
  816. };
  817. twi1_clk: twi1_clk {
  818. #clock-cells = <0>;
  819. reg = <12>;
  820. };
  821. spi0_clk: spi0_clk {
  822. #clock-cells = <0>;
  823. reg = <13>;
  824. };
  825. ssc0_clk: ssc0_clk {
  826. #clock-cells = <0>;
  827. reg = <14>;
  828. };
  829. ssc1_clk: ssc1_clk {
  830. #clock-cells = <0>;
  831. reg = <15>;
  832. };
  833. tc0_clk: tc0_clk {
  834. #clock-cells = <0>;
  835. reg = <16>;
  836. };
  837. tc1_clk: tc1_clk {
  838. #clock-cells = <0>;
  839. reg = <17>;
  840. };
  841. tc2_clk: tc2_clk {
  842. #clock-cells = <0>;
  843. reg = <18>;
  844. };
  845. pwm_clk: pwm_clk {
  846. #clock-cells = <0>;
  847. reg = <19>;
  848. };
  849. adc_clk: adc_clk {
  850. #clock-cells = <0>;
  851. reg = <20>;
  852. };
  853. dma0_clk: dma0_clk {
  854. #clock-cells = <0>;
  855. reg = <21>;
  856. };
  857. udphs_clk: udphs_clk {
  858. #clock-cells = <0>;
  859. reg = <22>;
  860. };
  861. lcd_clk: lcd_clk {
  862. #clock-cells = <0>;
  863. reg = <23>;
  864. };
  865. };
  866. };
  867. rstc@fffffd00 {
  868. compatible = "atmel,at91sam9260-rstc";
  869. reg = <0xfffffd00 0x10>;
  870. clocks = <&clk32k>;
  871. };
  872. shdwc@fffffd10 {
  873. compatible = "atmel,at91sam9260-shdwc";
  874. reg = <0xfffffd10 0x10>;
  875. clocks = <&clk32k>;
  876. };
  877. pit: timer@fffffd30 {
  878. compatible = "atmel,at91sam9260-pit";
  879. reg = <0xfffffd30 0xf>;
  880. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  881. clocks = <&mck>;
  882. };
  883. watchdog@fffffd40 {
  884. compatible = "atmel,at91sam9260-wdt";
  885. reg = <0xfffffd40 0x10>;
  886. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  887. clocks = <&clk32k>;
  888. status = "disabled";
  889. };
  890. sckc@fffffd50 {
  891. compatible = "atmel,at91sam9x5-sckc";
  892. reg = <0xfffffd50 0x4>;
  893. slow_osc: slow_osc {
  894. compatible = "atmel,at91sam9x5-clk-slow-osc";
  895. #clock-cells = <0>;
  896. atmel,startup-time-usec = <1200000>;
  897. clocks = <&slow_xtal>;
  898. };
  899. slow_rc_osc: slow_rc_osc {
  900. compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
  901. #clock-cells = <0>;
  902. atmel,startup-time-usec = <75>;
  903. clock-frequency = <32768>;
  904. clock-accuracy = <50000000>;
  905. };
  906. clk32k: slck {
  907. compatible = "atmel,at91sam9x5-clk-slow";
  908. #clock-cells = <0>;
  909. clocks = <&slow_rc_osc &slow_osc>;
  910. };
  911. };
  912. rtc@fffffd20 {
  913. compatible = "atmel,at91sam9260-rtt";
  914. reg = <0xfffffd20 0x10>;
  915. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  916. clocks = <&clk32k>;
  917. status = "disabled";
  918. };
  919. gpbr: syscon@fffffd60 {
  920. compatible = "atmel,at91sam9260-gpbr", "syscon";
  921. reg = <0xfffffd60 0x10>;
  922. status = "disabled";
  923. };
  924. rtc@fffffe00 {
  925. compatible = "atmel,at91rm9200-rtc";
  926. reg = <0xfffffe00 0x40>;
  927. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  928. clocks = <&clk32k>;
  929. status = "disabled";
  930. };
  931. };
  932. };
  933. i2c-gpio-0 {
  934. compatible = "i2c-gpio";
  935. gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */
  936. <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */
  937. i2c-gpio,sda-open-drain;
  938. i2c-gpio,scl-open-drain;
  939. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  940. #address-cells = <1>;
  941. #size-cells = <0>;
  942. pinctrl-names = "default";
  943. pinctrl-0 = <&pinctrl_i2c_gpio0>;
  944. status = "disabled";
  945. };
  946. i2c-gpio-1 {
  947. compatible = "i2c-gpio";
  948. gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */
  949. <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */
  950. i2c-gpio,sda-open-drain;
  951. i2c-gpio,scl-open-drain;
  952. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  953. #address-cells = <1>;
  954. #size-cells = <0>;
  955. pinctrl-names = "default";
  956. pinctrl-0 = <&pinctrl_i2c_gpio1>;
  957. status = "disabled";
  958. };
  959. };