at91rm9200.dtsi 25 KB

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  1. /*
  2. * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
  3. *
  4. * Copyright (C) 2011 Atmel,
  5. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
  6. * 2012 Joachim Eastwood <manabian@gmail.com>
  7. *
  8. * Based on at91sam9260.dtsi
  9. *
  10. * Licensed under GPLv2 or later.
  11. */
  12. #include "skeleton.dtsi"
  13. #include <dt-bindings/pinctrl/at91.h>
  14. #include <dt-bindings/interrupt-controller/irq.h>
  15. #include <dt-bindings/gpio/gpio.h>
  16. #include <dt-bindings/clock/at91.h>
  17. / {
  18. model = "Atmel AT91RM9200 family SoC";
  19. compatible = "atmel,at91rm9200";
  20. interrupt-parent = <&aic>;
  21. aliases {
  22. serial0 = &dbgu;
  23. serial1 = &usart0;
  24. serial2 = &usart1;
  25. serial3 = &usart2;
  26. serial4 = &usart3;
  27. gpio0 = &pioA;
  28. gpio1 = &pioB;
  29. gpio2 = &pioC;
  30. gpio3 = &pioD;
  31. tcb0 = &tcb0;
  32. tcb1 = &tcb1;
  33. i2c0 = &i2c0;
  34. ssc0 = &ssc0;
  35. ssc1 = &ssc1;
  36. ssc2 = &ssc2;
  37. };
  38. cpus {
  39. #address-cells = <0>;
  40. #size-cells = <0>;
  41. cpu {
  42. compatible = "arm,arm920t";
  43. device_type = "cpu";
  44. };
  45. };
  46. memory {
  47. reg = <0x20000000 0x04000000>;
  48. };
  49. clocks {
  50. slow_xtal: slow_xtal {
  51. compatible = "fixed-clock";
  52. #clock-cells = <0>;
  53. clock-frequency = <0>;
  54. };
  55. main_xtal: main_xtal {
  56. compatible = "fixed-clock";
  57. #clock-cells = <0>;
  58. clock-frequency = <0>;
  59. };
  60. };
  61. sram: sram@00200000 {
  62. compatible = "mmio-sram";
  63. reg = <0x00200000 0x4000>;
  64. };
  65. ahb {
  66. compatible = "simple-bus";
  67. #address-cells = <1>;
  68. #size-cells = <1>;
  69. ranges;
  70. apb {
  71. compatible = "simple-bus";
  72. #address-cells = <1>;
  73. #size-cells = <1>;
  74. ranges;
  75. aic: interrupt-controller@fffff000 {
  76. #interrupt-cells = <3>;
  77. compatible = "atmel,at91rm9200-aic";
  78. interrupt-controller;
  79. reg = <0xfffff000 0x200>;
  80. atmel,external-irqs = <25 26 27 28 29 30 31>;
  81. };
  82. ramc0: ramc@ffffff00 {
  83. compatible = "atmel,at91rm9200-sdramc", "syscon";
  84. reg = <0xffffff00 0x100>;
  85. };
  86. pmc: pmc@fffffc00 {
  87. compatible = "atmel,at91rm9200-pmc", "syscon";
  88. reg = <0xfffffc00 0x100>;
  89. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  90. interrupt-controller;
  91. #address-cells = <1>;
  92. #size-cells = <0>;
  93. #interrupt-cells = <1>;
  94. main_osc: main_osc {
  95. compatible = "atmel,at91rm9200-clk-main-osc";
  96. #clock-cells = <0>;
  97. interrupts-extended = <&pmc AT91_PMC_MOSCS>;
  98. clocks = <&main_xtal>;
  99. };
  100. main: mainck {
  101. compatible = "atmel,at91rm9200-clk-main";
  102. #clock-cells = <0>;
  103. clocks = <&main_osc>;
  104. };
  105. plla: pllack {
  106. compatible = "atmel,at91rm9200-clk-pll";
  107. #clock-cells = <0>;
  108. interrupts-extended = <&pmc AT91_PMC_LOCKA>;
  109. clocks = <&main>;
  110. reg = <0>;
  111. atmel,clk-input-range = <1000000 32000000>;
  112. #atmel,pll-clk-output-range-cells = <3>;
  113. atmel,pll-clk-output-ranges = <80000000 160000000 0>,
  114. <150000000 180000000 2>;
  115. };
  116. pllb: pllbck {
  117. compatible = "atmel,at91rm9200-clk-pll";
  118. #clock-cells = <0>;
  119. interrupts-extended = <&pmc AT91_PMC_LOCKB>;
  120. clocks = <&main>;
  121. reg = <1>;
  122. atmel,clk-input-range = <1000000 32000000>;
  123. #atmel,pll-clk-output-range-cells = <3>;
  124. atmel,pll-clk-output-ranges = <80000000 160000000 0>,
  125. <150000000 180000000 2>;
  126. };
  127. mck: masterck {
  128. compatible = "atmel,at91rm9200-clk-master";
  129. #clock-cells = <0>;
  130. interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
  131. clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
  132. atmel,clk-output-range = <0 80000000>;
  133. atmel,clk-divisors = <1 2 3 4>;
  134. };
  135. usb: usbck {
  136. compatible = "atmel,at91rm9200-clk-usb";
  137. #clock-cells = <0>;
  138. atmel,clk-divisors = <1 2 0 0>;
  139. clocks = <&pllb>;
  140. };
  141. prog: progck {
  142. compatible = "atmel,at91rm9200-clk-programmable";
  143. #address-cells = <1>;
  144. #size-cells = <0>;
  145. interrupt-parent = <&pmc>;
  146. clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
  147. prog0: prog0 {
  148. #clock-cells = <0>;
  149. reg = <0>;
  150. interrupts = <AT91_PMC_PCKRDY(0)>;
  151. };
  152. prog1: prog1 {
  153. #clock-cells = <0>;
  154. reg = <1>;
  155. interrupts = <AT91_PMC_PCKRDY(1)>;
  156. };
  157. prog2: prog2 {
  158. #clock-cells = <0>;
  159. reg = <2>;
  160. interrupts = <AT91_PMC_PCKRDY(2)>;
  161. };
  162. prog3: prog3 {
  163. #clock-cells = <0>;
  164. reg = <3>;
  165. interrupts = <AT91_PMC_PCKRDY(3)>;
  166. };
  167. };
  168. systemck {
  169. compatible = "atmel,at91rm9200-clk-system";
  170. #address-cells = <1>;
  171. #size-cells = <0>;
  172. udpck: udpck {
  173. #clock-cells = <0>;
  174. reg = <2>;
  175. clocks = <&usb>;
  176. };
  177. uhpck: uhpck {
  178. #clock-cells = <0>;
  179. reg = <4>;
  180. clocks = <&usb>;
  181. };
  182. pck0: pck0 {
  183. #clock-cells = <0>;
  184. reg = <8>;
  185. clocks = <&prog0>;
  186. };
  187. pck1: pck1 {
  188. #clock-cells = <0>;
  189. reg = <9>;
  190. clocks = <&prog1>;
  191. };
  192. pck2: pck2 {
  193. #clock-cells = <0>;
  194. reg = <10>;
  195. clocks = <&prog2>;
  196. };
  197. pck3: pck3 {
  198. #clock-cells = <0>;
  199. reg = <11>;
  200. clocks = <&prog3>;
  201. };
  202. };
  203. periphck {
  204. compatible = "atmel,at91rm9200-clk-peripheral";
  205. #address-cells = <1>;
  206. #size-cells = <0>;
  207. clocks = <&mck>;
  208. pioA_clk: pioA_clk {
  209. #clock-cells = <0>;
  210. reg = <2>;
  211. };
  212. pioB_clk: pioB_clk {
  213. #clock-cells = <0>;
  214. reg = <3>;
  215. };
  216. pioC_clk: pioC_clk {
  217. #clock-cells = <0>;
  218. reg = <4>;
  219. };
  220. pioD_clk: pioD_clk {
  221. #clock-cells = <0>;
  222. reg = <5>;
  223. };
  224. usart0_clk: usart0_clk {
  225. #clock-cells = <0>;
  226. reg = <6>;
  227. };
  228. usart1_clk: usart1_clk {
  229. #clock-cells = <0>;
  230. reg = <7>;
  231. };
  232. usart2_clk: usart2_clk {
  233. #clock-cells = <0>;
  234. reg = <8>;
  235. };
  236. usart3_clk: usart3_clk {
  237. #clock-cells = <0>;
  238. reg = <9>;
  239. };
  240. mci0_clk: mci0_clk {
  241. #clock-cells = <0>;
  242. reg = <10>;
  243. };
  244. udc_clk: udc_clk {
  245. #clock-cells = <0>;
  246. reg = <11>;
  247. };
  248. twi0_clk: twi0_clk {
  249. reg = <12>;
  250. #clock-cells = <0>;
  251. };
  252. spi0_clk: spi0_clk {
  253. #clock-cells = <0>;
  254. reg = <13>;
  255. };
  256. ssc0_clk: ssc0_clk {
  257. #clock-cells = <0>;
  258. reg = <14>;
  259. };
  260. ssc1_clk: ssc1_clk {
  261. #clock-cells = <0>;
  262. reg = <15>;
  263. };
  264. ssc2_clk: ssc2_clk {
  265. #clock-cells = <0>;
  266. reg = <16>;
  267. };
  268. tc0_clk: tc0_clk {
  269. #clock-cells = <0>;
  270. reg = <17>;
  271. };
  272. tc1_clk: tc1_clk {
  273. #clock-cells = <0>;
  274. reg = <18>;
  275. };
  276. tc2_clk: tc2_clk {
  277. #clock-cells = <0>;
  278. reg = <19>;
  279. };
  280. tc3_clk: tc3_clk {
  281. #clock-cells = <0>;
  282. reg = <20>;
  283. };
  284. tc4_clk: tc4_clk {
  285. #clock-cells = <0>;
  286. reg = <21>;
  287. };
  288. tc5_clk: tc5_clk {
  289. #clock-cells = <0>;
  290. reg = <22>;
  291. };
  292. ohci_clk: ohci_clk {
  293. #clock-cells = <0>;
  294. reg = <23>;
  295. };
  296. macb0_clk: macb0_clk {
  297. #clock-cells = <0>;
  298. reg = <24>;
  299. };
  300. };
  301. };
  302. st: timer@fffffd00 {
  303. compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
  304. reg = <0xfffffd00 0x100>;
  305. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  306. clocks = <&slow_xtal>;
  307. watchdog {
  308. compatible = "atmel,at91rm9200-wdt";
  309. };
  310. };
  311. rtc: rtc@fffffe00 {
  312. compatible = "atmel,at91rm9200-rtc";
  313. reg = <0xfffffe00 0x40>;
  314. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  315. clocks = <&slow_xtal>;
  316. status = "disabled";
  317. };
  318. tcb0: timer@fffa0000 {
  319. compatible = "atmel,at91rm9200-tcb";
  320. reg = <0xfffa0000 0x100>;
  321. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
  322. 18 IRQ_TYPE_LEVEL_HIGH 0
  323. 19 IRQ_TYPE_LEVEL_HIGH 0>;
  324. clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
  325. clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
  326. };
  327. tcb1: timer@fffa4000 {
  328. compatible = "atmel,at91rm9200-tcb";
  329. reg = <0xfffa4000 0x100>;
  330. interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
  331. 21 IRQ_TYPE_LEVEL_HIGH 0
  332. 22 IRQ_TYPE_LEVEL_HIGH 0>;
  333. clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>;
  334. clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
  335. };
  336. i2c0: i2c@fffb8000 {
  337. compatible = "atmel,at91rm9200-i2c";
  338. reg = <0xfffb8000 0x4000>;
  339. interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
  340. pinctrl-names = "default";
  341. pinctrl-0 = <&pinctrl_twi>;
  342. clocks = <&twi0_clk>;
  343. #address-cells = <1>;
  344. #size-cells = <0>;
  345. status = "disabled";
  346. };
  347. mmc0: mmc@fffb4000 {
  348. compatible = "atmel,hsmci";
  349. reg = <0xfffb4000 0x4000>;
  350. interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
  351. clocks = <&mci0_clk>;
  352. clock-names = "mci_clk";
  353. #address-cells = <1>;
  354. #size-cells = <0>;
  355. pinctrl-names = "default";
  356. status = "disabled";
  357. };
  358. ssc0: ssc@fffd0000 {
  359. compatible = "atmel,at91rm9200-ssc";
  360. reg = <0xfffd0000 0x4000>;
  361. interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
  362. pinctrl-names = "default";
  363. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  364. clocks = <&ssc0_clk>;
  365. clock-names = "pclk";
  366. status = "disabled";
  367. };
  368. ssc1: ssc@fffd4000 {
  369. compatible = "atmel,at91rm9200-ssc";
  370. reg = <0xfffd4000 0x4000>;
  371. interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
  372. pinctrl-names = "default";
  373. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  374. clocks = <&ssc1_clk>;
  375. clock-names = "pclk";
  376. status = "disabled";
  377. };
  378. ssc2: ssc@fffd8000 {
  379. compatible = "atmel,at91rm9200-ssc";
  380. reg = <0xfffd8000 0x4000>;
  381. interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
  382. pinctrl-names = "default";
  383. pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
  384. clocks = <&ssc2_clk>;
  385. clock-names = "pclk";
  386. status = "disabled";
  387. };
  388. macb0: ethernet@fffbc000 {
  389. compatible = "cdns,at91rm9200-emac", "cdns,emac";
  390. reg = <0xfffbc000 0x4000>;
  391. interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
  392. phy-mode = "rmii";
  393. pinctrl-names = "default";
  394. pinctrl-0 = <&pinctrl_macb_rmii>;
  395. clocks = <&macb0_clk>;
  396. clock-names = "ether_clk";
  397. status = "disabled";
  398. };
  399. pinctrl@fffff400 {
  400. #address-cells = <1>;
  401. #size-cells = <1>;
  402. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  403. ranges = <0xfffff400 0xfffff400 0x800>;
  404. atmel,mux-mask = <
  405. /* A B */
  406. 0xffffffff 0xffffffff /* pioA */
  407. 0xffffffff 0x083fffff /* pioB */
  408. 0xffff3fff 0x00000000 /* pioC */
  409. 0x03ff87ff 0x0fffff80 /* pioD */
  410. >;
  411. /* shared pinctrl settings */
  412. dbgu {
  413. pinctrl_dbgu: dbgu-0 {
  414. atmel,pins =
  415. <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */
  416. AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */
  417. };
  418. };
  419. uart0 {
  420. pinctrl_uart0: uart0-0 {
  421. atmel,pins =
  422. <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
  423. AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
  424. };
  425. pinctrl_uart0_cts: uart0_cts-0 {
  426. atmel,pins =
  427. <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */
  428. };
  429. pinctrl_uart0_rts: uart0_rts-0 {
  430. atmel,pins =
  431. <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
  432. };
  433. };
  434. uart1 {
  435. pinctrl_uart1: uart1-0 {
  436. atmel,pins =
  437. <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB20 periph A with pullup */
  438. AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
  439. };
  440. pinctrl_uart1_rts: uart1_rts-0 {
  441. atmel,pins =
  442. <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */
  443. };
  444. pinctrl_uart1_cts: uart1_cts-0 {
  445. atmel,pins =
  446. <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
  447. };
  448. pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
  449. atmel,pins =
  450. <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */
  451. AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
  452. };
  453. pinctrl_uart1_dcd: uart1_dcd-0 {
  454. atmel,pins =
  455. <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
  456. };
  457. pinctrl_uart1_ri: uart1_ri-0 {
  458. atmel,pins =
  459. <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
  460. };
  461. };
  462. uart2 {
  463. pinctrl_uart2: uart2-0 {
  464. atmel,pins =
  465. <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA22 periph A */
  466. AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
  467. };
  468. pinctrl_uart2_rts: uart2_rts-0 {
  469. atmel,pins =
  470. <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
  471. };
  472. pinctrl_uart2_cts: uart2_cts-0 {
  473. atmel,pins =
  474. <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */
  475. };
  476. };
  477. uart3 {
  478. pinctrl_uart3: uart3-0 {
  479. atmel,pins =
  480. <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
  481. AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA6 periph B */
  482. };
  483. pinctrl_uart3_rts: uart3_rts-0 {
  484. atmel,pins =
  485. <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
  486. };
  487. pinctrl_uart3_cts: uart3_cts-0 {
  488. atmel,pins =
  489. <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
  490. };
  491. };
  492. nand {
  493. pinctrl_nand: nand-0 {
  494. atmel,pins =
  495. <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC2 gpio RDY pin pull_up */
  496. AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PB1 gpio CD pin pull_up */
  497. };
  498. };
  499. macb {
  500. pinctrl_macb_rmii: macb_rmii-0 {
  501. atmel,pins =
  502. <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A */
  503. AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A */
  504. AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
  505. AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
  506. AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
  507. AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
  508. AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
  509. AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
  510. AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
  511. AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */
  512. };
  513. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  514. atmel,pins =
  515. <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB12 periph B */
  516. AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB13 periph B */
  517. AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B */
  518. AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB15 periph B */
  519. AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB16 periph B */
  520. AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB17 periph B */
  521. AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB18 periph B */
  522. AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */
  523. };
  524. };
  525. mmc0 {
  526. pinctrl_mmc0_clk: mmc0_clk-0 {
  527. atmel,pins =
  528. <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
  529. };
  530. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  531. atmel,pins =
  532. <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
  533. AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA29 periph A with pullup */
  534. };
  535. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  536. atmel,pins =
  537. <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */
  538. AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */
  539. AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PB5 periph B with pullup */
  540. };
  541. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  542. atmel,pins =
  543. <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */
  544. AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA9 periph B with pullup */
  545. };
  546. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  547. atmel,pins =
  548. <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA10 periph B with pullup */
  549. AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
  550. AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA12 periph B with pullup */
  551. };
  552. };
  553. ssc0 {
  554. pinctrl_ssc0_tx: ssc0_tx-0 {
  555. atmel,pins =
  556. <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
  557. AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
  558. AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A */
  559. };
  560. pinctrl_ssc0_rx: ssc0_rx-0 {
  561. atmel,pins =
  562. <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
  563. AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
  564. AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
  565. };
  566. };
  567. ssc1 {
  568. pinctrl_ssc1_tx: ssc1_tx-0 {
  569. atmel,pins =
  570. <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
  571. AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
  572. AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
  573. };
  574. pinctrl_ssc1_rx: ssc1_rx-0 {
  575. atmel,pins =
  576. <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
  577. AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */
  578. AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
  579. };
  580. };
  581. ssc2 {
  582. pinctrl_ssc2_tx: ssc2_tx-0 {
  583. atmel,pins =
  584. <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
  585. AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
  586. AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */
  587. };
  588. pinctrl_ssc2_rx: ssc2_rx-0 {
  589. atmel,pins =
  590. <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
  591. AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
  592. AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
  593. };
  594. };
  595. twi {
  596. pinctrl_twi: twi-0 {
  597. atmel,pins =
  598. <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* PA25 periph A with multi drive */
  599. AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* PA26 periph A with multi drive */
  600. };
  601. pinctrl_twi_gpio: twi_gpio-0 {
  602. atmel,pins =
  603. <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */
  604. AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA26 GPIO with multi drive */
  605. };
  606. };
  607. tcb0 {
  608. pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
  609. atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  610. };
  611. pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
  612. atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  613. };
  614. pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
  615. atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  616. };
  617. pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
  618. atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  619. };
  620. pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
  621. atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  622. };
  623. pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
  624. atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  625. };
  626. pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
  627. atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  628. };
  629. pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
  630. atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  631. };
  632. pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
  633. atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  634. };
  635. };
  636. tcb1 {
  637. pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
  638. atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  639. };
  640. pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
  641. atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  642. };
  643. pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
  644. atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  645. };
  646. pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
  647. atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  648. };
  649. pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
  650. atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  651. };
  652. pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
  653. atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  654. };
  655. pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
  656. atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  657. };
  658. pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
  659. atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  660. };
  661. pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
  662. atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  663. };
  664. };
  665. spi0 {
  666. pinctrl_spi0: spi0-0 {
  667. atmel,pins =
  668. <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
  669. AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */
  670. AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */
  671. };
  672. };
  673. pioA: gpio@fffff400 {
  674. compatible = "atmel,at91rm9200-gpio";
  675. reg = <0xfffff400 0x200>;
  676. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  677. #gpio-cells = <2>;
  678. gpio-controller;
  679. interrupt-controller;
  680. #interrupt-cells = <2>;
  681. clocks = <&pioA_clk>;
  682. };
  683. pioB: gpio@fffff600 {
  684. compatible = "atmel,at91rm9200-gpio";
  685. reg = <0xfffff600 0x200>;
  686. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  687. #gpio-cells = <2>;
  688. gpio-controller;
  689. interrupt-controller;
  690. #interrupt-cells = <2>;
  691. clocks = <&pioB_clk>;
  692. };
  693. pioC: gpio@fffff800 {
  694. compatible = "atmel,at91rm9200-gpio";
  695. reg = <0xfffff800 0x200>;
  696. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
  697. #gpio-cells = <2>;
  698. gpio-controller;
  699. interrupt-controller;
  700. #interrupt-cells = <2>;
  701. clocks = <&pioC_clk>;
  702. };
  703. pioD: gpio@fffffa00 {
  704. compatible = "atmel,at91rm9200-gpio";
  705. reg = <0xfffffa00 0x200>;
  706. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
  707. #gpio-cells = <2>;
  708. gpio-controller;
  709. interrupt-controller;
  710. #interrupt-cells = <2>;
  711. clocks = <&pioD_clk>;
  712. };
  713. };
  714. dbgu: serial@fffff200 {
  715. compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart";
  716. reg = <0xfffff200 0x200>;
  717. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  718. pinctrl-names = "default";
  719. pinctrl-0 = <&pinctrl_dbgu>;
  720. clocks = <&mck>;
  721. clock-names = "usart";
  722. status = "disabled";
  723. };
  724. usart0: serial@fffc0000 {
  725. compatible = "atmel,at91rm9200-usart";
  726. reg = <0xfffc0000 0x200>;
  727. interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
  728. atmel,use-dma-rx;
  729. atmel,use-dma-tx;
  730. pinctrl-names = "default";
  731. pinctrl-0 = <&pinctrl_uart0>;
  732. clocks = <&usart0_clk>;
  733. clock-names = "usart";
  734. status = "disabled";
  735. };
  736. usart1: serial@fffc4000 {
  737. compatible = "atmel,at91rm9200-usart";
  738. reg = <0xfffc4000 0x200>;
  739. interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
  740. atmel,use-dma-rx;
  741. atmel,use-dma-tx;
  742. pinctrl-names = "default";
  743. pinctrl-0 = <&pinctrl_uart1>;
  744. clocks = <&usart1_clk>;
  745. clock-names = "usart";
  746. status = "disabled";
  747. };
  748. usart2: serial@fffc8000 {
  749. compatible = "atmel,at91rm9200-usart";
  750. reg = <0xfffc8000 0x200>;
  751. interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
  752. atmel,use-dma-rx;
  753. atmel,use-dma-tx;
  754. pinctrl-names = "default";
  755. pinctrl-0 = <&pinctrl_uart2>;
  756. clocks = <&usart2_clk>;
  757. clock-names = "usart";
  758. status = "disabled";
  759. };
  760. usart3: serial@fffcc000 {
  761. compatible = "atmel,at91rm9200-usart";
  762. reg = <0xfffcc000 0x200>;
  763. interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
  764. atmel,use-dma-rx;
  765. atmel,use-dma-tx;
  766. pinctrl-names = "default";
  767. pinctrl-0 = <&pinctrl_uart3>;
  768. clocks = <&usart3_clk>;
  769. clock-names = "usart";
  770. status = "disabled";
  771. };
  772. usb1: gadget@fffb0000 {
  773. compatible = "atmel,at91rm9200-udc";
  774. reg = <0xfffb0000 0x4000>;
  775. interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
  776. clocks = <&udc_clk>, <&udpck>;
  777. clock-names = "pclk", "hclk";
  778. status = "disabled";
  779. };
  780. spi0: spi@fffe0000 {
  781. #address-cells = <1>;
  782. #size-cells = <0>;
  783. compatible = "atmel,at91rm9200-spi";
  784. reg = <0xfffe0000 0x200>;
  785. interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
  786. pinctrl-names = "default";
  787. pinctrl-0 = <&pinctrl_spi0>;
  788. clocks = <&spi0_clk>;
  789. clock-names = "spi_clk";
  790. status = "disabled";
  791. };
  792. };
  793. nand0: nand@40000000 {
  794. compatible = "atmel,at91rm9200-nand";
  795. #address-cells = <1>;
  796. #size-cells = <1>;
  797. reg = <0x40000000 0x10000000>;
  798. atmel,nand-addr-offset = <21>;
  799. atmel,nand-cmd-offset = <22>;
  800. pinctrl-names = "default";
  801. pinctrl-0 = <&pinctrl_nand>;
  802. nand-ecc-mode = "soft";
  803. gpios = <&pioC 2 GPIO_ACTIVE_HIGH
  804. 0
  805. &pioB 1 GPIO_ACTIVE_HIGH
  806. >;
  807. status = "disabled";
  808. };
  809. usb0: ohci@00300000 {
  810. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  811. reg = <0x00300000 0x100000>;
  812. interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
  813. clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
  814. clock-names = "ohci_clk", "hclk", "uhpck";
  815. status = "disabled";
  816. };
  817. };
  818. i2c-gpio-0 {
  819. compatible = "i2c-gpio";
  820. gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
  821. &pioA 26 GPIO_ACTIVE_HIGH /* scl */
  822. >;
  823. i2c-gpio,sda-open-drain;
  824. i2c-gpio,scl-open-drain;
  825. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  826. pinctrl-names = "default";
  827. pinctrl-0 = <&pinctrl_twi_gpio>;
  828. #address-cells = <1>;
  829. #size-cells = <0>;
  830. status = "disabled";
  831. };
  832. };