aspeed-g4.dtsi 3.2 KB

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  1. #include "skeleton.dtsi"
  2. / {
  3. model = "Aspeed BMC";
  4. compatible = "aspeed,ast2400";
  5. #address-cells = <1>;
  6. #size-cells = <1>;
  7. interrupt-parent = <&vic>;
  8. cpus {
  9. #address-cells = <1>;
  10. #size-cells = <0>;
  11. cpu@0 {
  12. compatible = "arm,arm926ej-s";
  13. device_type = "cpu";
  14. reg = <0>;
  15. };
  16. };
  17. clocks {
  18. clk_clkin: clk_clkin {
  19. #clock-cells = <0>;
  20. compatible = "fixed-clock";
  21. clock-frequency = <48000000>;
  22. };
  23. };
  24. ahb {
  25. compatible = "simple-bus";
  26. #address-cells = <1>;
  27. #size-cells = <1>;
  28. ranges;
  29. vic: interrupt-controller@1e6c0080 {
  30. compatible = "aspeed,ast2400-vic";
  31. interrupt-controller;
  32. #interrupt-cells = <1>;
  33. valid-sources = <0xffffffff 0x0007ffff>;
  34. reg = <0x1e6c0080 0x80>;
  35. };
  36. apb {
  37. compatible = "simple-bus";
  38. #address-cells = <1>;
  39. #size-cells = <1>;
  40. ranges;
  41. clk_hpll: clk_hpll@1e6e2070 {
  42. #clock-cells = <0>;
  43. compatible = "aspeed,g4-hpll-clock";
  44. reg = <0x1e6e2070 0x4>;
  45. clocks = <&clk_clkin>;
  46. };
  47. clk_apb: clk_apb@1e6e2008 {
  48. #clock-cells = <0>;
  49. compatible = "aspeed,g4-apb-clock";
  50. reg = <0x1e6e2008 0x4>;
  51. clocks = <&clk_hpll>;
  52. };
  53. clk_uart: clk_uart@1e6e2008 {
  54. #clock-cells = <0>;
  55. compatible = "aspeed,uart-clock";
  56. reg = <0x1e6e202c 0x4>;
  57. };
  58. sram@1e720000 {
  59. compatible = "mmio-sram";
  60. reg = <0x1e720000 0x8000>; // 32K
  61. };
  62. timer: timer@1e782000 {
  63. compatible = "aspeed,ast2400-timer";
  64. reg = <0x1e782000 0x90>;
  65. // The moxart_timer driver registers only one
  66. // interrupt and assumes it's for timer 1
  67. //interrupts = <16 17 18 35 36 37 38 39>;
  68. interrupts = <16>;
  69. clocks = <&clk_apb>;
  70. };
  71. wdt1: wdt@1e785000 {
  72. compatible = "aspeed,wdt";
  73. reg = <0x1e785000 0x1c>;
  74. interrupts = <27>;
  75. };
  76. wdt2: wdt@1e785020 {
  77. compatible = "aspeed,wdt";
  78. reg = <0x1e785020 0x1c>;
  79. interrupts = <27>;
  80. clocks = <&clk_apb>;
  81. status = "disabled";
  82. };
  83. uart1: serial@1e783000 {
  84. compatible = "ns16550a";
  85. reg = <0x1e783000 0x1000>;
  86. reg-shift = <2>;
  87. interrupts = <9>;
  88. clocks = <&clk_uart>;
  89. no-loopback-test;
  90. status = "disabled";
  91. };
  92. uart2: serial@1e78d000 {
  93. compatible = "ns16550a";
  94. reg = <0x1e78d000 0x1000>;
  95. reg-shift = <2>;
  96. interrupts = <32>;
  97. clocks = <&clk_uart>;
  98. no-loopback-test;
  99. status = "disabled";
  100. };
  101. uart3: serial@1e78e000 {
  102. compatible = "ns16550a";
  103. reg = <0x1e78e000 0x1000>;
  104. reg-shift = <2>;
  105. interrupts = <33>;
  106. clocks = <&clk_uart>;
  107. no-loopback-test;
  108. status = "disabled";
  109. };
  110. uart4: serial@1e78f000 {
  111. compatible = "ns16550a";
  112. reg = <0x1e78f000 0x1000>;
  113. reg-shift = <2>;
  114. interrupts = <34>;
  115. clocks = <&clk_uart>;
  116. no-loopback-test;
  117. status = "disabled";
  118. };
  119. uart5: serial@1e784000 {
  120. compatible = "ns16550a";
  121. reg = <0x1e784000 0x1000>;
  122. reg-shift = <2>;
  123. interrupts = <10>;
  124. clocks = <&clk_uart>;
  125. current-speed = <38400>;
  126. no-loopback-test;
  127. status = "disabled";
  128. };
  129. uart6: serial@1e787000 {
  130. compatible = "ns16550a";
  131. reg = <0x1e787000 0x1000>;
  132. reg-shift = <2>;
  133. interrupts = <10>;
  134. clocks = <&clk_uart>;
  135. no-loopback-test;
  136. status = "disabled";
  137. };
  138. };
  139. };
  140. };