armada-39x.dtsi 16 KB

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  1. /*
  2. * Device Tree Include file for Marvell Armada 39x family of SoCs.
  3. *
  4. * Copyright (C) 2015 Marvell
  5. *
  6. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  7. *
  8. * This file is dual-licensed: you can use it either under the terms
  9. * of the GPL or the X11 license, at your option. Note that this dual
  10. * licensing only applies to this file, and not this project as a
  11. * whole.
  12. *
  13. * a) This file is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of the
  16. * License, or (at your option) any later version.
  17. *
  18. * This file is distributed in the hope that it will be useful
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * Or, alternatively
  24. *
  25. * b) Permission is hereby granted, free of charge, to any person
  26. * obtaining a copy of this software and associated documentation
  27. * files (the "Software"), to deal in the Software without
  28. * restriction, including without limitation the rights to use
  29. * copy, modify, merge, publish, distribute, sublicense, and/or
  30. * sell copies of the Software, and to permit persons to whom the
  31. * Software is furnished to do so, subject to the following
  32. * conditions:
  33. *
  34. * The above copyright notice and this permission notice shall be
  35. * included in all copies or substantial portions of the Software.
  36. *
  37. * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  38. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  42. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44. * OTHER DEALINGS IN THE SOFTWARE.
  45. */
  46. #include "skeleton.dtsi"
  47. #include <dt-bindings/interrupt-controller/arm-gic.h>
  48. #include <dt-bindings/interrupt-controller/irq.h>
  49. #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  50. / {
  51. model = "Marvell Armada 39x family SoC";
  52. compatible = "marvell,armada390";
  53. aliases {
  54. gpio0 = &gpio0;
  55. gpio1 = &gpio1;
  56. serial0 = &uart0;
  57. serial1 = &uart1;
  58. serial2 = &uart2;
  59. serial3 = &uart3;
  60. };
  61. cpus {
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. enable-method = "marvell,armada-390-smp";
  65. cpu@0 {
  66. device_type = "cpu";
  67. compatible = "arm,cortex-a9";
  68. reg = <0>;
  69. };
  70. cpu@1 {
  71. device_type = "cpu";
  72. compatible = "arm,cortex-a9";
  73. reg = <1>;
  74. };
  75. };
  76. pmu {
  77. compatible = "arm,cortex-a9-pmu";
  78. interrupts-extended = <&mpic 3>;
  79. };
  80. soc {
  81. compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
  82. "simple-bus";
  83. #address-cells = <2>;
  84. #size-cells = <1>;
  85. controller = <&mbusc>;
  86. interrupt-parent = <&gic>;
  87. pcie-mem-aperture = <0xe0000000 0x8000000>;
  88. pcie-io-aperture = <0xe8000000 0x100000>;
  89. bootrom {
  90. compatible = "marvell,bootrom";
  91. reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
  92. };
  93. internal-regs {
  94. compatible = "simple-bus";
  95. #address-cells = <1>;
  96. #size-cells = <1>;
  97. ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
  98. L2: cache-controller@8000 {
  99. compatible = "arm,pl310-cache";
  100. reg = <0x8000 0x1000>;
  101. cache-unified;
  102. cache-level = <2>;
  103. arm,double-linefill-incr = <0>;
  104. arm,double-linefill-wrap = <0>;
  105. arm,double-linefill = <0>;
  106. prefetch-data = <1>;
  107. };
  108. scu@c000 {
  109. compatible = "arm,cortex-a9-scu";
  110. reg = <0xc000 0x100>;
  111. };
  112. timer@c600 {
  113. compatible = "arm,cortex-a9-twd-timer";
  114. reg = <0xc600 0x20>;
  115. interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
  116. clocks = <&coreclk 2>;
  117. };
  118. gic: interrupt-controller@d000 {
  119. compatible = "arm,cortex-a9-gic";
  120. #interrupt-cells = <3>;
  121. #size-cells = <0>;
  122. interrupt-controller;
  123. reg = <0xd000 0x1000>,
  124. <0xc100 0x100>;
  125. };
  126. i2c0: i2c@11000 {
  127. compatible = "marvell,mv64xxx-i2c";
  128. reg = <0x11000 0x20>;
  129. #address-cells = <1>;
  130. #size-cells = <0>;
  131. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  132. timeout-ms = <1000>;
  133. clocks = <&coreclk 0>;
  134. status = "disabled";
  135. };
  136. i2c1: i2c@11100 {
  137. compatible = "marvell,mv64xxx-i2c";
  138. reg = <0x11100 0x20>;
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  142. timeout-ms = <1000>;
  143. clocks = <&coreclk 0>;
  144. status = "disabled";
  145. };
  146. i2c2: i2c@11200 {
  147. compatible = "marvell,mv64xxx-i2c";
  148. reg = <0x11200 0x20>;
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  152. timeout-ms = <1000>;
  153. clocks = <&coreclk 0>;
  154. status = "disabled";
  155. };
  156. i2c3: i2c@11300 {
  157. compatible = "marvell,mv64xxx-i2c";
  158. reg = <0x11300 0x20>;
  159. #address-cells = <1>;
  160. #size-cells = <0>;
  161. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  162. timeout-ms = <1000>;
  163. clocks = <&coreclk 0>;
  164. status = "disabled";
  165. };
  166. uart0: serial@12000 {
  167. compatible = "snps,dw-apb-uart";
  168. reg = <0x12000 0x100>;
  169. reg-shift = <2>;
  170. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  171. reg-io-width = <1>;
  172. clocks = <&coreclk 0>;
  173. status = "disabled";
  174. };
  175. uart1: serial@12100 {
  176. compatible = "snps,dw-apb-uart";
  177. reg = <0x12100 0x100>;
  178. reg-shift = <2>;
  179. interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  180. reg-io-width = <1>;
  181. clocks = <&coreclk 0>;
  182. status = "disabled";
  183. };
  184. uart2: serial@12200 {
  185. compatible = "snps,dw-apb-uart";
  186. reg = <0x12200 0x100>;
  187. reg-shift = <2>;
  188. interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  189. reg-io-width = <1>;
  190. clocks = <&coreclk 0>;
  191. status = "disabled";
  192. };
  193. uart3: serial@12300 {
  194. compatible = "snps,dw-apb-uart";
  195. reg = <0x12300 0x100>;
  196. reg-shift = <2>;
  197. interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  198. reg-io-width = <1>;
  199. clocks = <&coreclk 0>;
  200. status = "disabled";
  201. };
  202. pinctrl@18000 {
  203. i2c0_pins: i2c0-pins {
  204. marvell,pins = "mpp2", "mpp3";
  205. marvell,function = "i2c0";
  206. };
  207. uart0_pins: uart0-pins {
  208. marvell,pins = "mpp0", "mpp1";
  209. marvell,function = "ua0";
  210. };
  211. uart1_pins: uart1-pins {
  212. marvell,pins = "mpp19", "mpp20";
  213. marvell,function = "ua1";
  214. };
  215. spi1_pins: spi1-pins {
  216. marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
  217. marvell,function = "spi1";
  218. };
  219. nand_pins: nand-pins {
  220. marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
  221. "mpp38", "mpp28", "mpp40", "mpp42",
  222. "mpp35", "mpp36", "mpp25", "mpp30",
  223. "mpp32";
  224. marvell,function = "dev";
  225. };
  226. };
  227. gpio0: gpio@18100 {
  228. compatible = "marvell,orion-gpio";
  229. reg = <0x18100 0x40>;
  230. ngpios = <32>;
  231. gpio-controller;
  232. #gpio-cells = <2>;
  233. interrupt-controller;
  234. #interrupt-cells = <2>;
  235. interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  236. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  237. <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  238. <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  239. };
  240. gpio1: gpio@18140 {
  241. compatible = "marvell,orion-gpio";
  242. reg = <0x18140 0x40>;
  243. ngpios = <28>;
  244. gpio-controller;
  245. #gpio-cells = <2>;
  246. interrupt-controller;
  247. #interrupt-cells = <2>;
  248. interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
  249. <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
  250. <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
  251. <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  252. };
  253. system-controller@18200 {
  254. compatible = "marvell,armada-390-system-controller",
  255. "marvell,armada-370-xp-system-controller";
  256. reg = <0x18200 0x100>;
  257. };
  258. gateclk: clock-gating-control@18220 {
  259. compatible = "marvell,armada-390-gating-clock";
  260. reg = <0x18220 0x4>;
  261. clocks = <&coreclk 0>;
  262. #clock-cells = <1>;
  263. };
  264. coreclk: mvebu-sar@18600 {
  265. compatible = "marvell,armada-390-core-clock";
  266. reg = <0x18600 0x04>;
  267. #clock-cells = <1>;
  268. };
  269. mbusc: mbus-controller@20000 {
  270. compatible = "marvell,mbus-controller";
  271. reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
  272. };
  273. mpic: interrupt-controller@20a00 {
  274. compatible = "marvell,mpic";
  275. reg = <0x20a00 0x2d0>, <0x21070 0x58>;
  276. #interrupt-cells = <1>;
  277. #size-cells = <1>;
  278. interrupt-controller;
  279. msi-controller;
  280. interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
  281. };
  282. timer@20300 {
  283. compatible = "marvell,armada-380-timer",
  284. "marvell,armada-xp-timer";
  285. reg = <0x20300 0x30>, <0x21040 0x30>;
  286. interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  287. <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  288. <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
  289. <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  290. <&mpic 5>,
  291. <&mpic 6>;
  292. clocks = <&coreclk 2>, <&coreclk 5>;
  293. clock-names = "nbclk", "fixed";
  294. };
  295. watchdog@20300 {
  296. compatible = "marvell,armada-380-wdt";
  297. reg = <0x20300 0x34>, <0x20704 0x4>,
  298. <0x18260 0x4>;
  299. clocks = <&coreclk 2>, <&refclk>;
  300. clock-names = "nbclk", "fixed";
  301. };
  302. cpurst@20800 {
  303. compatible = "marvell,armada-370-cpu-reset";
  304. reg = <0x20800 0x10>;
  305. };
  306. mpcore-soc-ctrl@20d20 {
  307. compatible = "marvell,armada-380-mpcore-soc-ctrl";
  308. reg = <0x20d20 0x6c>;
  309. };
  310. coherency-fabric@21010 {
  311. compatible = "marvell,armada-380-coherency-fabric";
  312. reg = <0x21010 0x1c>;
  313. };
  314. pmsu@22000 {
  315. compatible = "marvell,armada-390-pmsu",
  316. "marvell,armada-380-pmsu";
  317. reg = <0x22000 0x1000>;
  318. };
  319. xor@60800 {
  320. compatible = "marvell,armada-380-xor", "marvell,orion-xor";
  321. reg = <0x60800 0x100
  322. 0x60a00 0x100>;
  323. clocks = <&gateclk 22>;
  324. status = "okay";
  325. xor00 {
  326. interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
  327. dmacap,memcpy;
  328. dmacap,xor;
  329. };
  330. xor01 {
  331. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  332. dmacap,memcpy;
  333. dmacap,xor;
  334. dmacap,memset;
  335. };
  336. };
  337. xor@60900 {
  338. compatible = "marvell,armada-380-xor", "marvell,orion-xor";
  339. reg = <0x60900 0x100
  340. 0x60b00 0x100>;
  341. clocks = <&gateclk 28>;
  342. status = "okay";
  343. xor10 {
  344. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  345. dmacap,memcpy;
  346. dmacap,xor;
  347. };
  348. xor11 {
  349. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  350. dmacap,memcpy;
  351. dmacap,xor;
  352. dmacap,memset;
  353. };
  354. };
  355. rtc@a3800 {
  356. compatible = "marvell,armada-380-rtc";
  357. reg = <0xa3800 0x20>, <0x184a0 0x0c>;
  358. reg-names = "rtc", "rtc-soc";
  359. interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
  360. };
  361. flash@d0000 {
  362. compatible = "marvell,armada370-nand";
  363. reg = <0xd0000 0x54>;
  364. #address-cells = <1>;
  365. #size-cells = <1>;
  366. interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  367. clocks = <&coredivclk 0>;
  368. status = "disabled";
  369. };
  370. sdhci@d8000 {
  371. compatible = "marvell,armada-380-sdhci";
  372. reg-names = "sdhci", "mbus", "conf-sdio3";
  373. reg = <0xd8000 0x1000>,
  374. <0xdc000 0x100>,
  375. <0x18454 0x4>;
  376. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  377. clocks = <&gateclk 17>;
  378. mrvl,clk-delay-cycles = <0x1F>;
  379. status = "disabled";
  380. };
  381. coredivclk: clock@e4250 {
  382. compatible = "marvell,armada-390-corediv-clock",
  383. "marvell,armada-380-corediv-clock";
  384. reg = <0xe4250 0xc>;
  385. #clock-cells = <1>;
  386. clocks = <&mainpll>;
  387. clock-output-names = "nand";
  388. };
  389. thermal@e8078 {
  390. compatible = "marvell,armada380-thermal";
  391. reg = <0xe4078 0x4>, <0xe4074 0x4>;
  392. status = "okay";
  393. };
  394. };
  395. pcie-controller {
  396. compatible = "marvell,armada-370-pcie";
  397. status = "disabled";
  398. device_type = "pci";
  399. #address-cells = <3>;
  400. #size-cells = <2>;
  401. msi-parent = <&mpic>;
  402. bus-range = <0x00 0xff>;
  403. ranges =
  404. <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
  405. 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
  406. 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
  407. 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
  408. 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
  409. 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
  410. 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
  411. 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
  412. 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
  413. 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
  414. 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
  415. 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
  416. /*
  417. * This port can be either x4 or x1. When
  418. * configured in x4 by the bootloader, then
  419. * pcie@4,0 is not available.
  420. */
  421. pcie@1,0 {
  422. device_type = "pci";
  423. assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
  424. reg = <0x0800 0 0 0 0>;
  425. #address-cells = <3>;
  426. #size-cells = <2>;
  427. #interrupt-cells = <1>;
  428. ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
  429. 0x81000000 0 0 0x81000000 0x1 0 1 0>;
  430. interrupt-map-mask = <0 0 0 0>;
  431. interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  432. marvell,pcie-port = <0>;
  433. marvell,pcie-lane = <0>;
  434. clocks = <&gateclk 8>;
  435. status = "disabled";
  436. };
  437. /* x1 port */
  438. pcie@2,0 {
  439. device_type = "pci";
  440. assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
  441. reg = <0x1000 0 0 0 0>;
  442. #address-cells = <3>;
  443. #size-cells = <2>;
  444. #interrupt-cells = <1>;
  445. ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
  446. 0x81000000 0 0 0x81000000 0x2 0 1 0>;
  447. interrupt-map-mask = <0 0 0 0>;
  448. interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  449. marvell,pcie-port = <1>;
  450. marvell,pcie-lane = <0>;
  451. clocks = <&gateclk 5>;
  452. status = "disabled";
  453. };
  454. /* x1 port */
  455. pcie@3,0 {
  456. device_type = "pci";
  457. assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
  458. reg = <0x1800 0 0 0 0>;
  459. #address-cells = <3>;
  460. #size-cells = <2>;
  461. #interrupt-cells = <1>;
  462. ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
  463. 0x81000000 0 0 0x81000000 0x3 0 1 0>;
  464. interrupt-map-mask = <0 0 0 0>;
  465. interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  466. marvell,pcie-port = <2>;
  467. marvell,pcie-lane = <0>;
  468. clocks = <&gateclk 6>;
  469. status = "disabled";
  470. };
  471. /*
  472. * x1 port only available when pcie@1,0 is
  473. * configured as a x1 port
  474. */
  475. pcie@4,0 {
  476. device_type = "pci";
  477. assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
  478. reg = <0x2000 0 0 0 0>;
  479. #address-cells = <3>;
  480. #size-cells = <2>;
  481. #interrupt-cells = <1>;
  482. ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
  483. 0x81000000 0 0 0x81000000 0x4 0 1 0>;
  484. interrupt-map-mask = <0 0 0 0>;
  485. interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  486. marvell,pcie-port = <3>;
  487. marvell,pcie-lane = <0>;
  488. clocks = <&gateclk 7>;
  489. status = "disabled";
  490. };
  491. };
  492. spi0: spi@10600 {
  493. compatible = "marvell,armada-390-spi",
  494. "marvell,orion-spi";
  495. reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
  496. #address-cells = <1>;
  497. #size-cells = <0>;
  498. cell-index = <0>;
  499. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  500. clocks = <&coreclk 0>;
  501. status = "disabled";
  502. };
  503. spi1: spi@10680 {
  504. compatible = "marvell,armada-390-spi",
  505. "marvell,orion-spi";
  506. reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
  507. #address-cells = <1>;
  508. #size-cells = <0>;
  509. cell-index = <1>;
  510. interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  511. clocks = <&coreclk 0>;
  512. status = "disabled";
  513. };
  514. };
  515. clocks {
  516. /* 2 GHz fixed main PLL */
  517. mainpll: mainpll {
  518. compatible = "fixed-clock";
  519. #clock-cells = <0>;
  520. clock-frequency = <1000000000>;
  521. };
  522. /* 25 MHz reference crystal */
  523. refclk: oscillator {
  524. compatible = "fixed-clock";
  525. #clock-cells = <0>;
  526. clock-frequency = <25000000>;
  527. };
  528. };
  529. };