armada-38x.dtsi 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679
  1. /*
  2. * Device Tree Include file for Marvell Armada 38x family of SoCs.
  3. *
  4. * Copyright (C) 2014 Marvell
  5. *
  6. * Lior Amsalem <alior@marvell.com>
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  9. *
  10. * This file is dual-licensed: you can use it either under the terms
  11. * of the GPL or the X11 license, at your option. Note that this dual
  12. * licensing only applies to this file, and not this project as a
  13. * whole.
  14. *
  15. * a) This file is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of the
  18. * License, or (at your option) any later version.
  19. *
  20. * This file is distributed in the hope that it will be useful
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * Or, alternatively
  26. *
  27. * b) Permission is hereby granted, free of charge, to any person
  28. * obtaining a copy of this software and associated documentation
  29. * files (the "Software"), to deal in the Software without
  30. * restriction, including without limitation the rights to use
  31. * copy, modify, merge, publish, distribute, sublicense, and/or
  32. * sell copies of the Software, and to permit persons to whom the
  33. * Software is furnished to do so, subject to the following
  34. * conditions:
  35. *
  36. * The above copyright notice and this permission notice shall be
  37. * included in all copies or substantial portions of the Software.
  38. *
  39. * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  40. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  44. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46. * OTHER DEALINGS IN THE SOFTWARE.
  47. */
  48. #include "skeleton.dtsi"
  49. #include <dt-bindings/interrupt-controller/arm-gic.h>
  50. #include <dt-bindings/interrupt-controller/irq.h>
  51. #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  52. / {
  53. model = "Marvell Armada 38x family SoC";
  54. compatible = "marvell,armada380";
  55. aliases {
  56. gpio0 = &gpio0;
  57. gpio1 = &gpio1;
  58. serial0 = &uart0;
  59. serial1 = &uart1;
  60. };
  61. pmu {
  62. compatible = "arm,cortex-a9-pmu";
  63. interrupts-extended = <&mpic 3>;
  64. };
  65. soc {
  66. compatible = "marvell,armada380-mbus", "simple-bus";
  67. #address-cells = <2>;
  68. #size-cells = <1>;
  69. controller = <&mbusc>;
  70. interrupt-parent = <&gic>;
  71. pcie-mem-aperture = <0xe0000000 0x8000000>;
  72. pcie-io-aperture = <0xe8000000 0x100000>;
  73. bootrom {
  74. compatible = "marvell,bootrom";
  75. reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
  76. };
  77. devbus-bootcs {
  78. compatible = "marvell,mvebu-devbus";
  79. reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
  80. ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
  81. #address-cells = <1>;
  82. #size-cells = <1>;
  83. clocks = <&coreclk 0>;
  84. status = "disabled";
  85. };
  86. devbus-cs0 {
  87. compatible = "marvell,mvebu-devbus";
  88. reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
  89. ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
  90. #address-cells = <1>;
  91. #size-cells = <1>;
  92. clocks = <&coreclk 0>;
  93. status = "disabled";
  94. };
  95. devbus-cs1 {
  96. compatible = "marvell,mvebu-devbus";
  97. reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
  98. ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
  99. #address-cells = <1>;
  100. #size-cells = <1>;
  101. clocks = <&coreclk 0>;
  102. status = "disabled";
  103. };
  104. devbus-cs2 {
  105. compatible = "marvell,mvebu-devbus";
  106. reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
  107. ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
  108. #address-cells = <1>;
  109. #size-cells = <1>;
  110. clocks = <&coreclk 0>;
  111. status = "disabled";
  112. };
  113. devbus-cs3 {
  114. compatible = "marvell,mvebu-devbus";
  115. reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
  116. ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
  117. #address-cells = <1>;
  118. #size-cells = <1>;
  119. clocks = <&coreclk 0>;
  120. status = "disabled";
  121. };
  122. internal-regs {
  123. compatible = "simple-bus";
  124. #address-cells = <1>;
  125. #size-cells = <1>;
  126. ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
  127. L2: cache-controller@8000 {
  128. compatible = "arm,pl310-cache";
  129. reg = <0x8000 0x1000>;
  130. cache-unified;
  131. cache-level = <2>;
  132. arm,double-linefill-incr = <0>;
  133. arm,double-linefill-wrap = <0>;
  134. arm,double-linefill = <0>;
  135. prefetch-data = <1>;
  136. };
  137. scu@c000 {
  138. compatible = "arm,cortex-a9-scu";
  139. reg = <0xc000 0x58>;
  140. };
  141. timer@c600 {
  142. compatible = "arm,cortex-a9-twd-timer";
  143. reg = <0xc600 0x20>;
  144. interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
  145. clocks = <&coreclk 2>;
  146. };
  147. gic: interrupt-controller@d000 {
  148. compatible = "arm,cortex-a9-gic";
  149. #interrupt-cells = <3>;
  150. #size-cells = <0>;
  151. interrupt-controller;
  152. reg = <0xd000 0x1000>,
  153. <0xc100 0x100>;
  154. };
  155. i2c0: i2c@11000 {
  156. compatible = "marvell,mv64xxx-i2c";
  157. reg = <0x11000 0x20>;
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  161. timeout-ms = <1000>;
  162. clocks = <&coreclk 0>;
  163. status = "disabled";
  164. };
  165. i2c1: i2c@11100 {
  166. compatible = "marvell,mv64xxx-i2c";
  167. reg = <0x11100 0x20>;
  168. #address-cells = <1>;
  169. #size-cells = <0>;
  170. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  171. timeout-ms = <1000>;
  172. clocks = <&coreclk 0>;
  173. status = "disabled";
  174. };
  175. uart0: serial@12000 {
  176. compatible = "snps,dw-apb-uart";
  177. reg = <0x12000 0x100>;
  178. reg-shift = <2>;
  179. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  180. reg-io-width = <1>;
  181. clocks = <&coreclk 0>;
  182. status = "disabled";
  183. };
  184. uart1: serial@12100 {
  185. compatible = "snps,dw-apb-uart";
  186. reg = <0x12100 0x100>;
  187. reg-shift = <2>;
  188. interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  189. reg-io-width = <1>;
  190. clocks = <&coreclk 0>;
  191. status = "disabled";
  192. };
  193. pinctrl: pinctrl@18000 {
  194. reg = <0x18000 0x20>;
  195. ge0_rgmii_pins: ge-rgmii-pins-0 {
  196. marvell,pins = "mpp6", "mpp7", "mpp8",
  197. "mpp9", "mpp10", "mpp11",
  198. "mpp12", "mpp13", "mpp14",
  199. "mpp15", "mpp16", "mpp17";
  200. marvell,function = "ge0";
  201. };
  202. ge1_rgmii_pins: ge-rgmii-pins-1 {
  203. marvell,pins = "mpp21", "mpp27", "mpp28",
  204. "mpp29", "mpp30", "mpp31",
  205. "mpp32", "mpp37", "mpp38",
  206. "mpp39", "mpp40", "mpp41";
  207. marvell,function = "ge1";
  208. };
  209. i2c0_pins: i2c-pins-0 {
  210. marvell,pins = "mpp2", "mpp3";
  211. marvell,function = "i2c0";
  212. };
  213. mdio_pins: mdio-pins {
  214. marvell,pins = "mpp4", "mpp5";
  215. marvell,function = "ge";
  216. };
  217. ref_clk0_pins: ref-clk-pins-0 {
  218. marvell,pins = "mpp45";
  219. marvell,function = "ref";
  220. };
  221. ref_clk1_pins: ref-clk-pins-1 {
  222. marvell,pins = "mpp46";
  223. marvell,function = "ref";
  224. };
  225. spi0_pins: spi-pins-0 {
  226. marvell,pins = "mpp22", "mpp23", "mpp24",
  227. "mpp25";
  228. marvell,function = "spi0";
  229. };
  230. spi1_pins: spi-pins-1 {
  231. marvell,pins = "mpp56", "mpp57", "mpp58",
  232. "mpp59";
  233. marvell,function = "spi1";
  234. };
  235. nand_pins: nand-pins {
  236. marvell,pins = "mpp22", "mpp34", "mpp23",
  237. "mpp33", "mpp38", "mpp28",
  238. "mpp40", "mpp42", "mpp35",
  239. "mpp36", "mpp25", "mpp30",
  240. "mpp32";
  241. marvell,function = "dev";
  242. };
  243. uart0_pins: uart-pins-0 {
  244. marvell,pins = "mpp0", "mpp1";
  245. marvell,function = "ua0";
  246. };
  247. uart1_pins: uart-pins-1 {
  248. marvell,pins = "mpp19", "mpp20";
  249. marvell,function = "ua1";
  250. };
  251. sdhci_pins: sdhci-pins {
  252. marvell,pins = "mpp48", "mpp49", "mpp50",
  253. "mpp52", "mpp53", "mpp54",
  254. "mpp55", "mpp57", "mpp58",
  255. "mpp59";
  256. marvell,function = "sd0";
  257. };
  258. sata0_pins: sata-pins-0 {
  259. marvell,pins = "mpp20";
  260. marvell,function = "sata0";
  261. };
  262. sata1_pins: sata-pins-1 {
  263. marvell,pins = "mpp19";
  264. marvell,function = "sata1";
  265. };
  266. sata2_pins: sata-pins-2 {
  267. marvell,pins = "mpp47";
  268. marvell,function = "sata2";
  269. };
  270. sata3_pins: sata-pins-3 {
  271. marvell,pins = "mpp44";
  272. marvell,function = "sata3";
  273. };
  274. };
  275. gpio0: gpio@18100 {
  276. compatible = "marvell,orion-gpio";
  277. reg = <0x18100 0x40>;
  278. ngpios = <32>;
  279. gpio-controller;
  280. #gpio-cells = <2>;
  281. interrupt-controller;
  282. #interrupt-cells = <2>;
  283. interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  284. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  285. <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  286. <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  287. };
  288. gpio1: gpio@18140 {
  289. compatible = "marvell,orion-gpio";
  290. reg = <0x18140 0x40>;
  291. ngpios = <28>;
  292. gpio-controller;
  293. #gpio-cells = <2>;
  294. interrupt-controller;
  295. #interrupt-cells = <2>;
  296. interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
  297. <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
  298. <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
  299. <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  300. };
  301. system-controller@18200 {
  302. compatible = "marvell,armada-380-system-controller",
  303. "marvell,armada-370-xp-system-controller";
  304. reg = <0x18200 0x100>;
  305. };
  306. gateclk: clock-gating-control@18220 {
  307. compatible = "marvell,armada-380-gating-clock";
  308. reg = <0x18220 0x4>;
  309. clocks = <&coreclk 0>;
  310. #clock-cells = <1>;
  311. };
  312. coreclk: mvebu-sar@18600 {
  313. compatible = "marvell,armada-380-core-clock";
  314. reg = <0x18600 0x04>;
  315. #clock-cells = <1>;
  316. };
  317. mbusc: mbus-controller@20000 {
  318. compatible = "marvell,mbus-controller";
  319. reg = <0x20000 0x100>, <0x20180 0x20>;
  320. };
  321. mpic: interrupt-controller@20a00 {
  322. compatible = "marvell,mpic";
  323. reg = <0x20a00 0x2d0>, <0x21070 0x58>;
  324. #interrupt-cells = <1>;
  325. #size-cells = <1>;
  326. interrupt-controller;
  327. msi-controller;
  328. interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
  329. };
  330. timer@20300 {
  331. compatible = "marvell,armada-380-timer",
  332. "marvell,armada-xp-timer";
  333. reg = <0x20300 0x30>, <0x21040 0x30>;
  334. interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  335. <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  336. <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
  337. <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  338. <&mpic 5>,
  339. <&mpic 6>;
  340. clocks = <&coreclk 2>, <&refclk>;
  341. clock-names = "nbclk", "fixed";
  342. };
  343. watchdog@20300 {
  344. compatible = "marvell,armada-380-wdt";
  345. reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
  346. clocks = <&coreclk 2>, <&refclk>;
  347. clock-names = "nbclk", "fixed";
  348. };
  349. cpurst@20800 {
  350. compatible = "marvell,armada-370-cpu-reset";
  351. reg = <0x20800 0x10>;
  352. };
  353. mpcore-soc-ctrl@20d20 {
  354. compatible = "marvell,armada-380-mpcore-soc-ctrl";
  355. reg = <0x20d20 0x6c>;
  356. };
  357. coherency-fabric@21010 {
  358. compatible = "marvell,armada-380-coherency-fabric";
  359. reg = <0x21010 0x1c>;
  360. };
  361. pmsu@22000 {
  362. compatible = "marvell,armada-380-pmsu";
  363. reg = <0x22000 0x1000>;
  364. };
  365. /*
  366. * As a special exception to the "order by
  367. * register address" rule, the eth0 node is
  368. * placed here to ensure that it gets
  369. * registered as the first interface, since
  370. * the network subsystem doesn't allow naming
  371. * interfaces using DT aliases. Without this,
  372. * the ordering of interfaces is different
  373. * from the one used in U-Boot and the
  374. * labeling of interfaces on the boards, which
  375. * is very confusing for users.
  376. */
  377. eth0: ethernet@70000 {
  378. compatible = "marvell,armada-370-neta";
  379. reg = <0x70000 0x4000>;
  380. interrupts-extended = <&mpic 8>;
  381. clocks = <&gateclk 4>;
  382. tx-csum-limit = <9800>;
  383. status = "disabled";
  384. };
  385. eth1: ethernet@30000 {
  386. compatible = "marvell,armada-370-neta";
  387. reg = <0x30000 0x4000>;
  388. interrupts-extended = <&mpic 10>;
  389. clocks = <&gateclk 3>;
  390. status = "disabled";
  391. };
  392. eth2: ethernet@34000 {
  393. compatible = "marvell,armada-370-neta";
  394. reg = <0x34000 0x4000>;
  395. interrupts-extended = <&mpic 12>;
  396. clocks = <&gateclk 2>;
  397. status = "disabled";
  398. };
  399. usb@58000 {
  400. compatible = "marvell,orion-ehci";
  401. reg = <0x58000 0x500>;
  402. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
  403. clocks = <&gateclk 18>;
  404. status = "disabled";
  405. };
  406. xor@60800 {
  407. compatible = "marvell,armada-380-xor", "marvell,orion-xor";
  408. reg = <0x60800 0x100
  409. 0x60a00 0x100>;
  410. clocks = <&gateclk 22>;
  411. status = "okay";
  412. xor00 {
  413. interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
  414. dmacap,memcpy;
  415. dmacap,xor;
  416. };
  417. xor01 {
  418. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  419. dmacap,memcpy;
  420. dmacap,xor;
  421. dmacap,memset;
  422. };
  423. };
  424. xor@60900 {
  425. compatible = "marvell,armada-380-xor", "marvell,orion-xor";
  426. reg = <0x60900 0x100
  427. 0x60b00 0x100>;
  428. clocks = <&gateclk 28>;
  429. status = "okay";
  430. xor10 {
  431. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  432. dmacap,memcpy;
  433. dmacap,xor;
  434. };
  435. xor11 {
  436. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  437. dmacap,memcpy;
  438. dmacap,xor;
  439. dmacap,memset;
  440. };
  441. };
  442. mdio: mdio@72004 {
  443. #address-cells = <1>;
  444. #size-cells = <0>;
  445. compatible = "marvell,orion-mdio";
  446. reg = <0x72004 0x4>;
  447. clocks = <&gateclk 4>;
  448. };
  449. crypto@90000 {
  450. compatible = "marvell,armada-38x-crypto";
  451. reg = <0x90000 0x10000>;
  452. reg-names = "regs";
  453. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
  454. <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  455. clocks = <&gateclk 23>, <&gateclk 21>,
  456. <&gateclk 14>, <&gateclk 16>;
  457. clock-names = "cesa0", "cesa1",
  458. "cesaz0", "cesaz1";
  459. marvell,crypto-srams = <&crypto_sram0>,
  460. <&crypto_sram1>;
  461. marvell,crypto-sram-size = <0x800>;
  462. };
  463. rtc@a3800 {
  464. compatible = "marvell,armada-380-rtc";
  465. reg = <0xa3800 0x20>, <0x184a0 0x0c>;
  466. reg-names = "rtc", "rtc-soc";
  467. interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
  468. };
  469. sata@a8000 {
  470. compatible = "marvell,armada-380-ahci";
  471. reg = <0xa8000 0x2000>;
  472. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  473. clocks = <&gateclk 15>;
  474. status = "disabled";
  475. };
  476. bm: bm@c8000 {
  477. compatible = "marvell,armada-380-neta-bm";
  478. reg = <0xc8000 0xac>;
  479. clocks = <&gateclk 13>;
  480. internal-mem = <&bm_bppi>;
  481. status = "disabled";
  482. };
  483. sata@e0000 {
  484. compatible = "marvell,armada-380-ahci";
  485. reg = <0xe0000 0x2000>;
  486. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  487. clocks = <&gateclk 30>;
  488. status = "disabled";
  489. };
  490. coredivclk: clock@e4250 {
  491. compatible = "marvell,armada-380-corediv-clock";
  492. reg = <0xe4250 0xc>;
  493. #clock-cells = <1>;
  494. clocks = <&mainpll>;
  495. clock-output-names = "nand";
  496. };
  497. thermal@e8078 {
  498. compatible = "marvell,armada380-thermal";
  499. reg = <0xe4078 0x4>, <0xe4074 0x4>;
  500. status = "okay";
  501. };
  502. flash@d0000 {
  503. compatible = "marvell,armada370-nand";
  504. reg = <0xd0000 0x54>;
  505. #address-cells = <1>;
  506. #size-cells = <1>;
  507. interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  508. clocks = <&coredivclk 0>;
  509. status = "disabled";
  510. };
  511. sdhci@d8000 {
  512. compatible = "marvell,armada-380-sdhci";
  513. reg-names = "sdhci", "mbus", "conf-sdio3";
  514. reg = <0xd8000 0x1000>,
  515. <0xdc000 0x100>,
  516. <0x18454 0x4>;
  517. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  518. clocks = <&gateclk 17>;
  519. mrvl,clk-delay-cycles = <0x1F>;
  520. status = "disabled";
  521. };
  522. usb3@f0000 {
  523. compatible = "marvell,armada-380-xhci";
  524. reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
  525. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  526. clocks = <&gateclk 9>;
  527. status = "disabled";
  528. };
  529. usb3@f8000 {
  530. compatible = "marvell,armada-380-xhci";
  531. reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
  532. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  533. clocks = <&gateclk 10>;
  534. status = "disabled";
  535. };
  536. };
  537. crypto_sram0: sa-sram0 {
  538. compatible = "mmio-sram";
  539. reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
  540. clocks = <&gateclk 23>;
  541. #address-cells = <1>;
  542. #size-cells = <1>;
  543. ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
  544. };
  545. crypto_sram1: sa-sram1 {
  546. compatible = "mmio-sram";
  547. reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
  548. clocks = <&gateclk 21>;
  549. #address-cells = <1>;
  550. #size-cells = <1>;
  551. ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
  552. };
  553. bm_bppi: bm-bppi {
  554. compatible = "mmio-sram";
  555. reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
  556. ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
  557. #address-cells = <1>;
  558. #size-cells = <1>;
  559. clocks = <&gateclk 13>;
  560. no-memory-wc;
  561. status = "disabled";
  562. };
  563. spi0: spi@10600 {
  564. compatible = "marvell,armada-380-spi",
  565. "marvell,orion-spi";
  566. reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
  567. #address-cells = <1>;
  568. #size-cells = <0>;
  569. cell-index = <0>;
  570. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  571. clocks = <&coreclk 0>;
  572. status = "disabled";
  573. };
  574. spi1: spi@10680 {
  575. compatible = "marvell,armada-380-spi",
  576. "marvell,orion-spi";
  577. reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
  578. #address-cells = <1>;
  579. #size-cells = <0>;
  580. cell-index = <1>;
  581. interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  582. clocks = <&coreclk 0>;
  583. status = "disabled";
  584. };
  585. };
  586. clocks {
  587. /* 2 GHz fixed main PLL */
  588. mainpll: mainpll {
  589. compatible = "fixed-clock";
  590. #clock-cells = <0>;
  591. clock-frequency = <1000000000>;
  592. };
  593. /* 25 MHz reference crystal */
  594. refclk: oscillator {
  595. compatible = "fixed-clock";
  596. #clock-cells = <0>;
  597. clock-frequency = <25000000>;
  598. };
  599. };
  600. };