armada-385.dtsi 5.9 KB

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  1. /*
  2. * Device Tree Include file for Marvell Armada 385 SoC.
  3. *
  4. * Copyright (C) 2014 Marvell
  5. *
  6. * Lior Amsalem <alior@marvell.com>
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  9. *
  10. * This file is dual-licensed: you can use it either under the terms
  11. * of the GPL or the X11 license, at your option. Note that this dual
  12. * licensing only applies to this file, and not this project as a
  13. * whole.
  14. *
  15. * a) This file is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of the
  18. * License, or (at your option) any later version.
  19. *
  20. * This file is distributed in the hope that it will be useful
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * Or, alternatively
  26. *
  27. * b) Permission is hereby granted, free of charge, to any person
  28. * obtaining a copy of this software and associated documentation
  29. * files (the "Software"), to deal in the Software without
  30. * restriction, including without limitation the rights to use
  31. * copy, modify, merge, publish, distribute, sublicense, and/or
  32. * sell copies of the Software, and to permit persons to whom the
  33. * Software is furnished to do so, subject to the following
  34. * conditions:
  35. *
  36. * The above copyright notice and this permission notice shall be
  37. * included in all copies or substantial portions of the Software.
  38. *
  39. * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  40. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  44. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46. * OTHER DEALINGS IN THE SOFTWARE.
  47. */
  48. #include "armada-38x.dtsi"
  49. / {
  50. model = "Marvell Armada 385 family SoC";
  51. compatible = "marvell,armada385", "marvell,armada380";
  52. cpus {
  53. #address-cells = <1>;
  54. #size-cells = <0>;
  55. enable-method = "marvell,armada-380-smp";
  56. cpu@0 {
  57. device_type = "cpu";
  58. compatible = "arm,cortex-a9";
  59. reg = <0>;
  60. };
  61. cpu@1 {
  62. device_type = "cpu";
  63. compatible = "arm,cortex-a9";
  64. reg = <1>;
  65. };
  66. };
  67. soc {
  68. internal-regs {
  69. pinctrl@18000 {
  70. compatible = "marvell,mv88f6820-pinctrl";
  71. };
  72. };
  73. pcie-controller {
  74. compatible = "marvell,armada-370-pcie";
  75. status = "disabled";
  76. device_type = "pci";
  77. #address-cells = <3>;
  78. #size-cells = <2>;
  79. msi-parent = <&mpic>;
  80. bus-range = <0x00 0xff>;
  81. ranges =
  82. <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
  83. 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
  84. 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
  85. 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
  86. 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
  87. 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
  88. 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
  89. 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
  90. 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
  91. 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
  92. 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
  93. 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
  94. /*
  95. * This port can be either x4 or x1. When
  96. * configured in x4 by the bootloader, then
  97. * pcie@4,0 is not available.
  98. */
  99. pcie@1,0 {
  100. device_type = "pci";
  101. assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
  102. reg = <0x0800 0 0 0 0>;
  103. #address-cells = <3>;
  104. #size-cells = <2>;
  105. #interrupt-cells = <1>;
  106. ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
  107. 0x81000000 0 0 0x81000000 0x1 0 1 0>;
  108. interrupt-map-mask = <0 0 0 0>;
  109. interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  110. marvell,pcie-port = <0>;
  111. marvell,pcie-lane = <0>;
  112. clocks = <&gateclk 8>;
  113. status = "disabled";
  114. };
  115. /* x1 port */
  116. pcie@2,0 {
  117. device_type = "pci";
  118. assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
  119. reg = <0x1000 0 0 0 0>;
  120. #address-cells = <3>;
  121. #size-cells = <2>;
  122. #interrupt-cells = <1>;
  123. ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
  124. 0x81000000 0 0 0x81000000 0x2 0 1 0>;
  125. interrupt-map-mask = <0 0 0 0>;
  126. interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  127. marvell,pcie-port = <1>;
  128. marvell,pcie-lane = <0>;
  129. clocks = <&gateclk 5>;
  130. status = "disabled";
  131. };
  132. /* x1 port */
  133. pcie@3,0 {
  134. device_type = "pci";
  135. assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
  136. reg = <0x1800 0 0 0 0>;
  137. #address-cells = <3>;
  138. #size-cells = <2>;
  139. #interrupt-cells = <1>;
  140. ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
  141. 0x81000000 0 0 0x81000000 0x3 0 1 0>;
  142. interrupt-map-mask = <0 0 0 0>;
  143. interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  144. marvell,pcie-port = <2>;
  145. marvell,pcie-lane = <0>;
  146. clocks = <&gateclk 6>;
  147. status = "disabled";
  148. };
  149. /*
  150. * x1 port only available when pcie@1,0 is
  151. * configured as a x1 port
  152. */
  153. pcie@4,0 {
  154. device_type = "pci";
  155. assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
  156. reg = <0x2000 0 0 0 0>;
  157. #address-cells = <3>;
  158. #size-cells = <2>;
  159. #interrupt-cells = <1>;
  160. ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
  161. 0x81000000 0 0 0x81000000 0x4 0 1 0>;
  162. interrupt-map-mask = <0 0 0 0>;
  163. interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  164. marvell,pcie-port = <3>;
  165. marvell,pcie-lane = <0>;
  166. clocks = <&gateclk 7>;
  167. status = "disabled";
  168. };
  169. };
  170. };
  171. };