armada-380.dtsi 5.0 KB

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  1. /*
  2. * Device Tree Include file for Marvell Armada 380 SoC.
  3. *
  4. * Copyright (C) 2014 Marvell
  5. *
  6. * Lior Amsalem <alior@marvell.com>
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  9. *
  10. * This file is dual-licensed: you can use it either under the terms
  11. * of the GPL or the X11 license, at your option. Note that this dual
  12. * licensing only applies to this file, and not this project as a
  13. * whole.
  14. *
  15. * a) This file is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of the
  18. * License, or (at your option) any later version.
  19. *
  20. * This file is distributed in the hope that it will be useful
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * Or, alternatively
  26. *
  27. * b) Permission is hereby granted, free of charge, to any person
  28. * obtaining a copy of this software and associated documentation
  29. * files (the "Software"), to deal in the Software without
  30. * restriction, including without limitation the rights to use
  31. * copy, modify, merge, publish, distribute, sublicense, and/or
  32. * sell copies of the Software, and to permit persons to whom the
  33. * Software is furnished to do so, subject to the following
  34. * conditions:
  35. *
  36. * The above copyright notice and this permission notice shall be
  37. * included in all copies or substantial portions of the Software.
  38. *
  39. * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  40. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  44. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46. * OTHER DEALINGS IN THE SOFTWARE.
  47. */
  48. #include "armada-38x.dtsi"
  49. / {
  50. model = "Marvell Armada 380 family SoC";
  51. compatible = "marvell,armada380";
  52. cpus {
  53. #address-cells = <1>;
  54. #size-cells = <0>;
  55. enable-method = "marvell,armada-380-smp";
  56. cpu@0 {
  57. device_type = "cpu";
  58. compatible = "arm,cortex-a9";
  59. reg = <0>;
  60. };
  61. };
  62. soc {
  63. internal-regs {
  64. pinctrl@18000 {
  65. compatible = "marvell,mv88f6810-pinctrl";
  66. };
  67. };
  68. pcie-controller {
  69. compatible = "marvell,armada-370-pcie";
  70. status = "disabled";
  71. device_type = "pci";
  72. #address-cells = <3>;
  73. #size-cells = <2>;
  74. msi-parent = <&mpic>;
  75. bus-range = <0x00 0xff>;
  76. ranges =
  77. <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
  78. 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
  79. 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
  80. 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
  81. 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
  82. 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
  83. 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
  84. 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
  85. 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
  86. 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
  87. /* x1 port */
  88. pcie@1,0 {
  89. device_type = "pci";
  90. assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
  91. reg = <0x0800 0 0 0 0>;
  92. #address-cells = <3>;
  93. #size-cells = <2>;
  94. #interrupt-cells = <1>;
  95. ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
  96. 0x81000000 0 0 0x81000000 0x1 0 1 0>;
  97. interrupt-map-mask = <0 0 0 0>;
  98. interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  99. marvell,pcie-port = <0>;
  100. marvell,pcie-lane = <0>;
  101. clocks = <&gateclk 8>;
  102. status = "disabled";
  103. };
  104. /* x1 port */
  105. pcie@2,0 {
  106. device_type = "pci";
  107. assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
  108. reg = <0x1000 0 0 0 0>;
  109. #address-cells = <3>;
  110. #size-cells = <2>;
  111. #interrupt-cells = <1>;
  112. ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
  113. 0x81000000 0 0 0x81000000 0x2 0 1 0>;
  114. interrupt-map-mask = <0 0 0 0>;
  115. interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  116. marvell,pcie-port = <1>;
  117. marvell,pcie-lane = <0>;
  118. clocks = <&gateclk 5>;
  119. status = "disabled";
  120. };
  121. /* x1 port */
  122. pcie@3,0 {
  123. device_type = "pci";
  124. assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
  125. reg = <0x1800 0 0 0 0>;
  126. #address-cells = <3>;
  127. #size-cells = <2>;
  128. #interrupt-cells = <1>;
  129. ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
  130. 0x81000000 0 0 0x81000000 0x3 0 1 0>;
  131. interrupt-map-mask = <0 0 0 0>;
  132. interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  133. marvell,pcie-port = <2>;
  134. marvell,pcie-lane = <0>;
  135. clocks = <&gateclk 6>;
  136. status = "disabled";
  137. };
  138. };
  139. };
  140. };