armada-375.dtsi 17 KB

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  1. /*
  2. * Device Tree Include file for Marvell Armada 375 family SoC
  3. *
  4. * Copyright (C) 2014 Marvell
  5. *
  6. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  7. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  8. *
  9. * This file is dual-licensed: you can use it either under the terms
  10. * of the GPL or the X11 license, at your option. Note that this dual
  11. * licensing only applies to this file, and not this project as a
  12. * whole.
  13. *
  14. * a) This file is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of the
  17. * License, or (at your option) any later version.
  18. *
  19. * This file is distributed in the hope that it will be useful
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * Or, alternatively
  25. *
  26. * b) Permission is hereby granted, free of charge, to any person
  27. * obtaining a copy of this software and associated documentation
  28. * files (the "Software"), to deal in the Software without
  29. * restriction, including without limitation the rights to use
  30. * copy, modify, merge, publish, distribute, sublicense, and/or
  31. * sell copies of the Software, and to permit persons to whom the
  32. * Software is furnished to do so, subject to the following
  33. * conditions:
  34. *
  35. * The above copyright notice and this permission notice shall be
  36. * included in all copies or substantial portions of the Software.
  37. *
  38. * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  39. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  43. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45. * OTHER DEALINGS IN THE SOFTWARE.
  46. */
  47. #include "skeleton.dtsi"
  48. #include <dt-bindings/interrupt-controller/arm-gic.h>
  49. #include <dt-bindings/interrupt-controller/irq.h>
  50. #include <dt-bindings/phy/phy.h>
  51. #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  52. / {
  53. model = "Marvell Armada 375 family SoC";
  54. compatible = "marvell,armada375";
  55. aliases {
  56. gpio0 = &gpio0;
  57. gpio1 = &gpio1;
  58. gpio2 = &gpio2;
  59. serial0 = &uart0;
  60. serial1 = &uart1;
  61. };
  62. clocks {
  63. /* 2 GHz fixed main PLL */
  64. mainpll: mainpll {
  65. compatible = "fixed-clock";
  66. #clock-cells = <0>;
  67. clock-frequency = <1000000000>;
  68. };
  69. /* 25 MHz reference crystal */
  70. refclk: oscillator {
  71. compatible = "fixed-clock";
  72. #clock-cells = <0>;
  73. clock-frequency = <25000000>;
  74. };
  75. };
  76. cpus {
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. enable-method = "marvell,armada-375-smp";
  80. cpu@0 {
  81. device_type = "cpu";
  82. compatible = "arm,cortex-a9";
  83. reg = <0>;
  84. };
  85. cpu@1 {
  86. device_type = "cpu";
  87. compatible = "arm,cortex-a9";
  88. reg = <1>;
  89. };
  90. };
  91. pmu {
  92. compatible = "arm,cortex-a9-pmu";
  93. interrupts-extended = <&mpic 3>;
  94. };
  95. soc {
  96. compatible = "marvell,armada375-mbus", "simple-bus";
  97. #address-cells = <2>;
  98. #size-cells = <1>;
  99. controller = <&mbusc>;
  100. interrupt-parent = <&gic>;
  101. pcie-mem-aperture = <0xe0000000 0x8000000>;
  102. pcie-io-aperture = <0xe8000000 0x100000>;
  103. bootrom {
  104. compatible = "marvell,bootrom";
  105. reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
  106. };
  107. devbus-bootcs {
  108. compatible = "marvell,mvebu-devbus";
  109. reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
  110. ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
  111. #address-cells = <1>;
  112. #size-cells = <1>;
  113. clocks = <&coreclk 0>;
  114. status = "disabled";
  115. };
  116. devbus-cs0 {
  117. compatible = "marvell,mvebu-devbus";
  118. reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
  119. ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
  120. #address-cells = <1>;
  121. #size-cells = <1>;
  122. clocks = <&coreclk 0>;
  123. status = "disabled";
  124. };
  125. devbus-cs1 {
  126. compatible = "marvell,mvebu-devbus";
  127. reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
  128. ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
  129. #address-cells = <1>;
  130. #size-cells = <1>;
  131. clocks = <&coreclk 0>;
  132. status = "disabled";
  133. };
  134. devbus-cs2 {
  135. compatible = "marvell,mvebu-devbus";
  136. reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
  137. ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
  138. #address-cells = <1>;
  139. #size-cells = <1>;
  140. clocks = <&coreclk 0>;
  141. status = "disabled";
  142. };
  143. devbus-cs3 {
  144. compatible = "marvell,mvebu-devbus";
  145. reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
  146. ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
  147. #address-cells = <1>;
  148. #size-cells = <1>;
  149. clocks = <&coreclk 0>;
  150. status = "disabled";
  151. };
  152. internal-regs {
  153. compatible = "simple-bus";
  154. #address-cells = <1>;
  155. #size-cells = <1>;
  156. ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
  157. L2: cache-controller@8000 {
  158. compatible = "arm,pl310-cache";
  159. reg = <0x8000 0x1000>;
  160. cache-unified;
  161. cache-level = <2>;
  162. arm,double-linefill-incr = <0>;
  163. arm,double-linefill-wrap = <0>;
  164. arm,double-linefill = <0>;
  165. prefetch-data = <1>;
  166. };
  167. scu@c000 {
  168. compatible = "arm,cortex-a9-scu";
  169. reg = <0xc000 0x58>;
  170. };
  171. timer@c600 {
  172. compatible = "arm,cortex-a9-twd-timer";
  173. reg = <0xc600 0x20>;
  174. interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
  175. clocks = <&coreclk 2>;
  176. };
  177. gic: interrupt-controller@d000 {
  178. compatible = "arm,cortex-a9-gic";
  179. #interrupt-cells = <3>;
  180. #size-cells = <0>;
  181. interrupt-controller;
  182. reg = <0xd000 0x1000>,
  183. <0xc100 0x100>;
  184. };
  185. mdio {
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. compatible = "marvell,orion-mdio";
  189. reg = <0xc0054 0x4>;
  190. clocks = <&gateclk 19>;
  191. };
  192. /* Network controller */
  193. ethernet@f0000 {
  194. compatible = "marvell,armada-375-pp2";
  195. reg = <0xf0000 0xa000>, /* Packet Processor regs */
  196. <0xc0000 0x3060>, /* LMS regs */
  197. <0xc4000 0x100>, /* eth0 regs */
  198. <0xc5000 0x100>; /* eth1 regs */
  199. clocks = <&gateclk 3>, <&gateclk 19>;
  200. clock-names = "pp_clk", "gop_clk";
  201. status = "disabled";
  202. eth0: eth0@c4000 {
  203. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  204. port-id = <0>;
  205. status = "disabled";
  206. };
  207. eth1: eth1@c5000 {
  208. interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  209. port-id = <1>;
  210. status = "disabled";
  211. };
  212. };
  213. rtc@10300 {
  214. compatible = "marvell,orion-rtc";
  215. reg = <0x10300 0x20>;
  216. interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
  217. };
  218. spi0: spi@10600 {
  219. compatible = "marvell,armada-375-spi",
  220. "marvell,orion-spi";
  221. reg = <0x10600 0x50>;
  222. #address-cells = <1>;
  223. #size-cells = <0>;
  224. cell-index = <0>;
  225. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  226. clocks = <&coreclk 0>;
  227. status = "disabled";
  228. };
  229. spi1: spi@10680 {
  230. compatible = "marvell,armada-375-spi",
  231. "marvell,orion-spi";
  232. reg = <0x10680 0x50>;
  233. #address-cells = <1>;
  234. #size-cells = <0>;
  235. cell-index = <1>;
  236. interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  237. clocks = <&coreclk 0>;
  238. status = "disabled";
  239. };
  240. i2c0: i2c@11000 {
  241. compatible = "marvell,mv64xxx-i2c";
  242. reg = <0x11000 0x20>;
  243. #address-cells = <1>;
  244. #size-cells = <0>;
  245. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  246. timeout-ms = <1000>;
  247. clocks = <&coreclk 0>;
  248. status = "disabled";
  249. };
  250. i2c1: i2c@11100 {
  251. compatible = "marvell,mv64xxx-i2c";
  252. reg = <0x11100 0x20>;
  253. #address-cells = <1>;
  254. #size-cells = <0>;
  255. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  256. timeout-ms = <1000>;
  257. clocks = <&coreclk 0>;
  258. status = "disabled";
  259. };
  260. uart0: serial@12000 {
  261. compatible = "snps,dw-apb-uart";
  262. reg = <0x12000 0x100>;
  263. reg-shift = <2>;
  264. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  265. reg-io-width = <1>;
  266. clocks = <&coreclk 0>;
  267. status = "disabled";
  268. };
  269. uart1: serial@12100 {
  270. compatible = "snps,dw-apb-uart";
  271. reg = <0x12100 0x100>;
  272. reg-shift = <2>;
  273. interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  274. reg-io-width = <1>;
  275. clocks = <&coreclk 0>;
  276. status = "disabled";
  277. };
  278. pinctrl {
  279. compatible = "marvell,mv88f6720-pinctrl";
  280. reg = <0x18000 0x24>;
  281. i2c0_pins: i2c0-pins {
  282. marvell,pins = "mpp14", "mpp15";
  283. marvell,function = "i2c0";
  284. };
  285. i2c1_pins: i2c1-pins {
  286. marvell,pins = "mpp61", "mpp62";
  287. marvell,function = "i2c1";
  288. };
  289. nand_pins: nand-pins {
  290. marvell,pins = "mpp0", "mpp1", "mpp2",
  291. "mpp3", "mpp4", "mpp5",
  292. "mpp6", "mpp7", "mpp8",
  293. "mpp9", "mpp10", "mpp11",
  294. "mpp12", "mpp13";
  295. marvell,function = "nand";
  296. };
  297. sdio_pins: sdio-pins {
  298. marvell,pins = "mpp24", "mpp25", "mpp26",
  299. "mpp27", "mpp28", "mpp29";
  300. marvell,function = "sd";
  301. };
  302. spi0_pins: spi0-pins {
  303. marvell,pins = "mpp0", "mpp1", "mpp4",
  304. "mpp5", "mpp8", "mpp9";
  305. marvell,function = "spi0";
  306. };
  307. };
  308. gpio0: gpio@18100 {
  309. compatible = "marvell,orion-gpio";
  310. reg = <0x18100 0x40>;
  311. ngpios = <32>;
  312. gpio-controller;
  313. #gpio-cells = <2>;
  314. interrupt-controller;
  315. #interrupt-cells = <2>;
  316. interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  317. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  318. <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  319. <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  320. };
  321. gpio1: gpio@18140 {
  322. compatible = "marvell,orion-gpio";
  323. reg = <0x18140 0x40>;
  324. ngpios = <32>;
  325. gpio-controller;
  326. #gpio-cells = <2>;
  327. interrupt-controller;
  328. #interrupt-cells = <2>;
  329. interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
  330. <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
  331. <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
  332. <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  333. };
  334. gpio2: gpio@18180 {
  335. compatible = "marvell,orion-gpio";
  336. reg = <0x18180 0x40>;
  337. ngpios = <3>;
  338. gpio-controller;
  339. #gpio-cells = <2>;
  340. interrupt-controller;
  341. #interrupt-cells = <2>;
  342. interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  343. };
  344. system-controller@18200 {
  345. compatible = "marvell,armada-375-system-controller";
  346. reg = <0x18200 0x100>;
  347. };
  348. gateclk: clock-gating-control@18220 {
  349. compatible = "marvell,armada-375-gating-clock";
  350. reg = <0x18220 0x4>;
  351. clocks = <&coreclk 0>;
  352. #clock-cells = <1>;
  353. };
  354. usbcluster: usb-cluster@18400 {
  355. compatible = "marvell,armada-375-usb-cluster";
  356. reg = <0x18400 0x4>;
  357. #phy-cells = <1>;
  358. };
  359. mbusc: mbus-controller@20000 {
  360. compatible = "marvell,mbus-controller";
  361. reg = <0x20000 0x100>, <0x20180 0x20>;
  362. };
  363. mpic: interrupt-controller@20a00 {
  364. compatible = "marvell,mpic";
  365. reg = <0x20a00 0x2d0>, <0x21070 0x58>;
  366. #interrupt-cells = <1>;
  367. #size-cells = <1>;
  368. interrupt-controller;
  369. msi-controller;
  370. interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
  371. };
  372. timer@20300 {
  373. compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
  374. reg = <0x20300 0x30>, <0x21040 0x30>;
  375. interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  376. <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  377. <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
  378. <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  379. <&mpic 5>,
  380. <&mpic 6>;
  381. clocks = <&coreclk 0>, <&refclk>;
  382. clock-names = "nbclk", "fixed";
  383. };
  384. watchdog@20300 {
  385. compatible = "marvell,armada-375-wdt";
  386. reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
  387. clocks = <&coreclk 0>, <&refclk>;
  388. clock-names = "nbclk", "fixed";
  389. };
  390. cpurst@20800 {
  391. compatible = "marvell,armada-370-cpu-reset";
  392. reg = <0x20800 0x10>;
  393. };
  394. coherency-fabric@21010 {
  395. compatible = "marvell,armada-375-coherency-fabric";
  396. reg = <0x21010 0x1c>;
  397. };
  398. usb@50000 {
  399. compatible = "marvell,orion-ehci";
  400. reg = <0x50000 0x500>;
  401. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  402. clocks = <&gateclk 18>;
  403. phys = <&usbcluster PHY_TYPE_USB2>;
  404. phy-names = "usb";
  405. status = "disabled";
  406. };
  407. usb@54000 {
  408. compatible = "marvell,orion-ehci";
  409. reg = <0x54000 0x500>;
  410. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
  411. clocks = <&gateclk 26>;
  412. status = "disabled";
  413. };
  414. usb3@58000 {
  415. compatible = "marvell,armada-375-xhci";
  416. reg = <0x58000 0x20000>,<0x5b880 0x80>;
  417. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  418. clocks = <&gateclk 16>;
  419. phys = <&usbcluster PHY_TYPE_USB3>;
  420. phy-names = "usb";
  421. status = "disabled";
  422. };
  423. xor@60800 {
  424. compatible = "marvell,orion-xor";
  425. reg = <0x60800 0x100
  426. 0x60A00 0x100>;
  427. clocks = <&gateclk 22>;
  428. status = "okay";
  429. xor00 {
  430. interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
  431. dmacap,memcpy;
  432. dmacap,xor;
  433. };
  434. xor01 {
  435. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  436. dmacap,memcpy;
  437. dmacap,xor;
  438. dmacap,memset;
  439. };
  440. };
  441. xor@60900 {
  442. compatible = "marvell,orion-xor";
  443. reg = <0x60900 0x100
  444. 0x60b00 0x100>;
  445. clocks = <&gateclk 23>;
  446. status = "okay";
  447. xor10 {
  448. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  449. dmacap,memcpy;
  450. dmacap,xor;
  451. };
  452. xor11 {
  453. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  454. dmacap,memcpy;
  455. dmacap,xor;
  456. dmacap,memset;
  457. };
  458. };
  459. crypto@90000 {
  460. compatible = "marvell,armada-375-crypto";
  461. reg = <0x90000 0x10000>;
  462. reg-names = "regs";
  463. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
  464. <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  465. clocks = <&gateclk 30>, <&gateclk 31>,
  466. <&gateclk 28>, <&gateclk 29>;
  467. clock-names = "cesa0", "cesa1",
  468. "cesaz0", "cesaz1";
  469. marvell,crypto-srams = <&crypto_sram0>,
  470. <&crypto_sram1>;
  471. marvell,crypto-sram-size = <0x800>;
  472. };
  473. sata@a0000 {
  474. compatible = "marvell,armada-370-sata";
  475. reg = <0xa0000 0x5000>;
  476. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  477. clocks = <&gateclk 14>, <&gateclk 20>;
  478. clock-names = "0", "1";
  479. status = "disabled";
  480. };
  481. nand@d0000 {
  482. compatible = "marvell,armada370-nand";
  483. reg = <0xd0000 0x54>;
  484. #address-cells = <1>;
  485. #size-cells = <1>;
  486. interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  487. clocks = <&gateclk 11>;
  488. status = "disabled";
  489. };
  490. mvsdio@d4000 {
  491. compatible = "marvell,orion-sdio";
  492. reg = <0xd4000 0x200>;
  493. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  494. clocks = <&gateclk 17>;
  495. bus-width = <4>;
  496. cap-sdio-irq;
  497. cap-sd-highspeed;
  498. cap-mmc-highspeed;
  499. status = "disabled";
  500. };
  501. thermal@e8078 {
  502. compatible = "marvell,armada375-thermal";
  503. reg = <0xe8078 0x4>, <0xe807c 0x8>;
  504. status = "okay";
  505. };
  506. coreclk: mvebu-sar@e8204 {
  507. compatible = "marvell,armada-375-core-clock";
  508. reg = <0xe8204 0x04>;
  509. #clock-cells = <1>;
  510. };
  511. coredivclk: corediv-clock@e8250 {
  512. compatible = "marvell,armada-375-corediv-clock";
  513. reg = <0xe8250 0xc>;
  514. #clock-cells = <1>;
  515. clocks = <&mainpll>;
  516. clock-output-names = "nand";
  517. };
  518. };
  519. pcie-controller {
  520. compatible = "marvell,armada-370-pcie";
  521. status = "disabled";
  522. device_type = "pci";
  523. #address-cells = <3>;
  524. #size-cells = <2>;
  525. msi-parent = <&mpic>;
  526. bus-range = <0x00 0xff>;
  527. ranges =
  528. <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
  529. 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
  530. 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
  531. 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
  532. 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
  533. 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
  534. pcie@1,0 {
  535. device_type = "pci";
  536. assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
  537. reg = <0x0800 0 0 0 0>;
  538. #address-cells = <3>;
  539. #size-cells = <2>;
  540. #interrupt-cells = <1>;
  541. ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
  542. 0x81000000 0 0 0x81000000 0x1 0 1 0>;
  543. interrupt-map-mask = <0 0 0 0>;
  544. interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  545. marvell,pcie-port = <0>;
  546. marvell,pcie-lane = <0>;
  547. clocks = <&gateclk 5>;
  548. status = "disabled";
  549. };
  550. pcie@2,0 {
  551. device_type = "pci";
  552. assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
  553. reg = <0x1000 0 0 0 0>;
  554. #address-cells = <3>;
  555. #size-cells = <2>;
  556. #interrupt-cells = <1>;
  557. ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
  558. 0x81000000 0 0 0x81000000 0x2 0 1 0>;
  559. interrupt-map-mask = <0 0 0 0>;
  560. interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  561. marvell,pcie-port = <0>;
  562. marvell,pcie-lane = <1>;
  563. clocks = <&gateclk 6>;
  564. status = "disabled";
  565. };
  566. };
  567. crypto_sram0: sa-sram0 {
  568. compatible = "mmio-sram";
  569. reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
  570. clocks = <&gateclk 30>;
  571. #address-cells = <1>;
  572. #size-cells = <1>;
  573. ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
  574. };
  575. crypto_sram1: sa-sram1 {
  576. compatible = "mmio-sram";
  577. reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
  578. clocks = <&gateclk 31>;
  579. #address-cells = <1>;
  580. #size-cells = <1>;
  581. ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
  582. };
  583. };
  584. };