armada-370.dtsi 11 KB

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  1. /*
  2. * Device Tree Include file for Marvell Armada 370 family SoC
  3. *
  4. * Copyright (C) 2012 Marvell
  5. *
  6. * Lior Amsalem <alior@marvell.com>
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  9. *
  10. * This file is dual-licensed: you can use it either under the terms
  11. * of the GPL or the X11 license, at your option. Note that this dual
  12. * licensing only applies to this file, and not this project as a
  13. * whole.
  14. *
  15. * a) This file is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of the
  18. * License, or (at your option) any later version.
  19. *
  20. * This file is distributed in the hope that it will be useful
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * Or, alternatively
  26. *
  27. * b) Permission is hereby granted, free of charge, to any person
  28. * obtaining a copy of this software and associated documentation
  29. * files (the "Software"), to deal in the Software without
  30. * restriction, including without limitation the rights to use
  31. * copy, modify, merge, publish, distribute, sublicense, and/or
  32. * sell copies of the Software, and to permit persons to whom the
  33. * Software is furnished to do so, subject to the following
  34. * conditions:
  35. *
  36. * The above copyright notice and this permission notice shall be
  37. * included in all copies or substantial portions of the Software.
  38. *
  39. * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  40. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  44. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46. * OTHER DEALINGS IN THE SOFTWARE.
  47. *
  48. * Contains definitions specific to the Armada 370 SoC that are not
  49. * common to all Armada SoCs.
  50. */
  51. #include "armada-370-xp.dtsi"
  52. /include/ "skeleton.dtsi"
  53. / {
  54. model = "Marvell Armada 370 family SoC";
  55. compatible = "marvell,armada370", "marvell,armada-370-xp";
  56. aliases {
  57. gpio0 = &gpio0;
  58. gpio1 = &gpio1;
  59. gpio2 = &gpio2;
  60. };
  61. soc {
  62. compatible = "marvell,armada370-mbus", "simple-bus";
  63. bootrom {
  64. compatible = "marvell,bootrom";
  65. reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
  66. };
  67. pcie-controller {
  68. compatible = "marvell,armada-370-pcie";
  69. status = "disabled";
  70. device_type = "pci";
  71. #address-cells = <3>;
  72. #size-cells = <2>;
  73. msi-parent = <&mpic>;
  74. bus-range = <0x00 0xff>;
  75. ranges =
  76. <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
  77. 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
  78. 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
  79. 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
  80. 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
  81. 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
  82. pcie@1,0 {
  83. device_type = "pci";
  84. assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
  85. reg = <0x0800 0 0 0 0>;
  86. #address-cells = <3>;
  87. #size-cells = <2>;
  88. #interrupt-cells = <1>;
  89. ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
  90. 0x81000000 0 0 0x81000000 0x1 0 1 0>;
  91. interrupt-map-mask = <0 0 0 0>;
  92. interrupt-map = <0 0 0 0 &mpic 58>;
  93. marvell,pcie-port = <0>;
  94. marvell,pcie-lane = <0>;
  95. clocks = <&gateclk 5>;
  96. status = "disabled";
  97. };
  98. pcie@2,0 {
  99. device_type = "pci";
  100. assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
  101. reg = <0x1000 0 0 0 0>;
  102. #address-cells = <3>;
  103. #size-cells = <2>;
  104. #interrupt-cells = <1>;
  105. ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
  106. 0x81000000 0 0 0x81000000 0x2 0 1 0>;
  107. interrupt-map-mask = <0 0 0 0>;
  108. interrupt-map = <0 0 0 0 &mpic 62>;
  109. marvell,pcie-port = <1>;
  110. marvell,pcie-lane = <0>;
  111. clocks = <&gateclk 9>;
  112. status = "disabled";
  113. };
  114. };
  115. internal-regs {
  116. L2: l2-cache {
  117. compatible = "marvell,aurora-outer-cache";
  118. reg = <0x08000 0x1000>;
  119. cache-id-part = <0x100>;
  120. cache-level = <2>;
  121. cache-unified;
  122. wt-override;
  123. };
  124. i2c0: i2c@11000 {
  125. reg = <0x11000 0x20>;
  126. };
  127. i2c1: i2c@11100 {
  128. reg = <0x11100 0x20>;
  129. };
  130. gpio0: gpio@18100 {
  131. compatible = "marvell,orion-gpio";
  132. reg = <0x18100 0x40>;
  133. ngpios = <32>;
  134. gpio-controller;
  135. #gpio-cells = <2>;
  136. interrupt-controller;
  137. #interrupt-cells = <2>;
  138. interrupts = <82>, <83>, <84>, <85>;
  139. };
  140. gpio1: gpio@18140 {
  141. compatible = "marvell,orion-gpio";
  142. reg = <0x18140 0x40>;
  143. ngpios = <32>;
  144. gpio-controller;
  145. #gpio-cells = <2>;
  146. interrupt-controller;
  147. #interrupt-cells = <2>;
  148. interrupts = <87>, <88>, <89>, <90>;
  149. };
  150. gpio2: gpio@18180 {
  151. compatible = "marvell,orion-gpio";
  152. reg = <0x18180 0x40>;
  153. ngpios = <2>;
  154. gpio-controller;
  155. #gpio-cells = <2>;
  156. interrupt-controller;
  157. #interrupt-cells = <2>;
  158. interrupts = <91>;
  159. };
  160. /*
  161. * Default UART pinctrl setting without RTS/CTS, can
  162. * be overwritten on board level if a different
  163. * configuration is used.
  164. */
  165. uart0: serial@12000 {
  166. pinctrl-0 = <&uart0_pins>;
  167. pinctrl-names = "default";
  168. };
  169. uart1: serial@12100 {
  170. pinctrl-0 = <&uart1_pins>;
  171. pinctrl-names = "default";
  172. };
  173. system-controller@18200 {
  174. compatible = "marvell,armada-370-xp-system-controller";
  175. reg = <0x18200 0x100>;
  176. };
  177. gateclk: clock-gating-control@18220 {
  178. compatible = "marvell,armada-370-gating-clock";
  179. reg = <0x18220 0x4>;
  180. clocks = <&coreclk 0>;
  181. #clock-cells = <1>;
  182. };
  183. coreclk: mvebu-sar@18230 {
  184. compatible = "marvell,armada-370-core-clock";
  185. reg = <0x18230 0x08>;
  186. #clock-cells = <1>;
  187. };
  188. thermal@18300 {
  189. compatible = "marvell,armada370-thermal";
  190. reg = <0x18300 0x4
  191. 0x18304 0x4>;
  192. status = "okay";
  193. };
  194. sscg@18330 {
  195. reg = <0x18330 0x4>;
  196. };
  197. interrupt-controller@20a00 {
  198. reg = <0x20a00 0x1d0>, <0x21870 0x58>;
  199. };
  200. timer@20300 {
  201. compatible = "marvell,armada-370-timer";
  202. clocks = <&coreclk 2>;
  203. };
  204. watchdog@20300 {
  205. compatible = "marvell,armada-370-wdt";
  206. clocks = <&coreclk 2>;
  207. };
  208. cpurst@20800 {
  209. compatible = "marvell,armada-370-cpu-reset";
  210. reg = <0x20800 0x8>;
  211. };
  212. cpu-config@21000 {
  213. compatible = "marvell,armada-370-cpu-config";
  214. reg = <0x21000 0x8>;
  215. };
  216. audio_controller: audio-controller@30000 {
  217. #sound-dai-cells = <1>;
  218. compatible = "marvell,armada370-audio";
  219. reg = <0x30000 0x4000>;
  220. interrupts = <93>;
  221. clocks = <&gateclk 0>;
  222. clock-names = "internal";
  223. status = "disabled";
  224. };
  225. usb@50000 {
  226. clocks = <&coreclk 0>;
  227. };
  228. usb@51000 {
  229. clocks = <&coreclk 0>;
  230. };
  231. xor@60800 {
  232. compatible = "marvell,orion-xor";
  233. reg = <0x60800 0x100
  234. 0x60A00 0x100>;
  235. status = "okay";
  236. xor00 {
  237. interrupts = <51>;
  238. dmacap,memcpy;
  239. dmacap,xor;
  240. };
  241. xor01 {
  242. interrupts = <52>;
  243. dmacap,memcpy;
  244. dmacap,xor;
  245. dmacap,memset;
  246. };
  247. };
  248. xor@60900 {
  249. compatible = "marvell,orion-xor";
  250. reg = <0x60900 0x100
  251. 0x60b00 0x100>;
  252. status = "okay";
  253. xor10 {
  254. interrupts = <94>;
  255. dmacap,memcpy;
  256. dmacap,xor;
  257. };
  258. xor11 {
  259. interrupts = <95>;
  260. dmacap,memcpy;
  261. dmacap,xor;
  262. dmacap,memset;
  263. };
  264. };
  265. ethernet@70000 {
  266. compatible = "marvell,armada-370-neta";
  267. };
  268. ethernet@74000 {
  269. compatible = "marvell,armada-370-neta";
  270. };
  271. crypto@90000 {
  272. compatible = "marvell,armada-370-crypto";
  273. reg = <0x90000 0x10000>;
  274. reg-names = "regs";
  275. interrupts = <48>;
  276. clocks = <&gateclk 23>;
  277. clock-names = "cesa0";
  278. marvell,crypto-srams = <&crypto_sram>;
  279. marvell,crypto-sram-size = <0x7e0>;
  280. };
  281. };
  282. crypto_sram: sa-sram {
  283. compatible = "mmio-sram";
  284. reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
  285. reg-names = "sram";
  286. clocks = <&gateclk 23>;
  287. #address-cells = <1>;
  288. #size-cells = <1>;
  289. ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;
  290. /*
  291. * The Armada 370 has an erratum preventing the use of
  292. * the standard workflow for CPU idle support (relying
  293. * on the BootROM code to enter/exit idle state).
  294. * Reserve some amount of the crypto SRAM to put the
  295. * cpuidle workaround.
  296. */
  297. idle-sram@0 {
  298. reg = <0x0 0x20>;
  299. };
  300. };
  301. };
  302. };
  303. &pinctrl {
  304. compatible = "marvell,mv88f6710-pinctrl";
  305. spi0_pins1: spi0-pins1 {
  306. marvell,pins = "mpp33", "mpp34",
  307. "mpp35", "mpp36";
  308. marvell,function = "spi0";
  309. };
  310. spi0_pins2: spi0_pins2 {
  311. marvell,pins = "mpp32", "mpp63",
  312. "mpp64", "mpp65";
  313. marvell,function = "spi0";
  314. };
  315. spi1_pins: spi1-pins {
  316. marvell,pins = "mpp49", "mpp50",
  317. "mpp51", "mpp52";
  318. marvell,function = "spi1";
  319. };
  320. uart0_pins: uart0-pins {
  321. marvell,pins = "mpp0", "mpp1";
  322. marvell,function = "uart0";
  323. };
  324. uart1_pins: uart1-pins {
  325. marvell,pins = "mpp41", "mpp42";
  326. marvell,function = "uart1";
  327. };
  328. sdio_pins1: sdio-pins1 {
  329. marvell,pins = "mpp9", "mpp11", "mpp12",
  330. "mpp13", "mpp14", "mpp15";
  331. marvell,function = "sd0";
  332. };
  333. sdio_pins2: sdio-pins2 {
  334. marvell,pins = "mpp47", "mpp48", "mpp49",
  335. "mpp50", "mpp51", "mpp52";
  336. marvell,function = "sd0";
  337. };
  338. sdio_pins3: sdio-pins3 {
  339. marvell,pins = "mpp48", "mpp49", "mpp50",
  340. "mpp51", "mpp52", "mpp53";
  341. marvell,function = "sd0";
  342. };
  343. i2c0_pins: i2c0-pins {
  344. marvell,pins = "mpp2", "mpp3";
  345. marvell,function = "i2c0";
  346. };
  347. i2s_pins1: i2s-pins1 {
  348. marvell,pins = "mpp5", "mpp6", "mpp7",
  349. "mpp8", "mpp9", "mpp10",
  350. "mpp12", "mpp13";
  351. marvell,function = "audio";
  352. };
  353. i2s_pins2: i2s-pins2 {
  354. marvell,pins = "mpp49", "mpp47", "mpp50",
  355. "mpp59", "mpp57", "mpp61",
  356. "mpp62", "mpp60", "mpp58";
  357. marvell,function = "audio";
  358. };
  359. mdio_pins: mdio-pins {
  360. marvell,pins = "mpp17", "mpp18";
  361. marvell,function = "ge";
  362. };
  363. ge0_rgmii_pins: ge0-rgmii-pins {
  364. marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
  365. "mpp9", "mpp10", "mpp11", "mpp12",
  366. "mpp13", "mpp14", "mpp15", "mpp16";
  367. marvell,function = "ge0";
  368. };
  369. ge1_rgmii_pins: ge1-rgmii-pins {
  370. marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
  371. "mpp23", "mpp24", "mpp25", "mpp26",
  372. "mpp27", "mpp28", "mpp29", "mpp30";
  373. marvell,function = "ge1";
  374. };
  375. };
  376. /*
  377. * Default SPI pinctrl setting, can be overwritten on
  378. * board level if a different configuration is used.
  379. */
  380. &spi0 {
  381. compatible = "marvell,armada-370-spi", "marvell,orion-spi";
  382. pinctrl-0 = <&spi0_pins1>;
  383. pinctrl-names = "default";
  384. };
  385. &spi1 {
  386. compatible = "marvell,armada-370-spi", "marvell,orion-spi";
  387. pinctrl-0 = <&spi1_pins>;
  388. pinctrl-names = "default";
  389. };