am335x-nano.dts 12 KB

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  1. /*
  2. * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /dts-v1/;
  9. #include "am33xx.dtsi"
  10. / {
  11. model = "Newflow AM335x NanoBone";
  12. compatible = "ti,am33xx";
  13. cpus {
  14. cpu@0 {
  15. cpu0-supply = <&dcdc2_reg>;
  16. };
  17. };
  18. memory@80000000 {
  19. device_type = "memory";
  20. reg = <0x80000000 0x10000000>; /* 256 MB */
  21. };
  22. leds {
  23. compatible = "gpio-leds";
  24. led0 {
  25. label = "nanobone:green:usr1";
  26. gpios = <&gpio1 5 0>;
  27. default-state = "off";
  28. };
  29. };
  30. };
  31. &am33xx_pinmux {
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&misc_pins>;
  34. misc_pins: misc_pins {
  35. pinctrl-single,pins = <
  36. AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */
  37. >;
  38. };
  39. gpmc_pins: gpmc_pins {
  40. pinctrl-single,pins = <
  41. AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
  42. AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
  43. AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
  44. AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
  45. AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
  46. AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
  47. AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
  48. AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
  49. AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */
  50. AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */
  51. AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */
  52. AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */
  53. AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */
  54. AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */
  55. AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */
  56. AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */
  57. AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
  58. AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
  59. AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn1.gpmc_csn1 */
  60. AM33XX_IOPAD(0x884, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn2.gpmc_csn2 */
  61. AM33XX_IOPAD(0x888, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn3.gpmc_csn3 */
  62. AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
  63. AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
  64. AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
  65. AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0_cle.gpmc_ben0_cle */
  66. AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE1) /* lcd_data1.gpmc_a1 */
  67. AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE1) /* lcd_data2.gpmc_a2 */
  68. AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE1) /* lcd_data3.gpmc_a3 */
  69. AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE1) /* lcd_data4.gpmc_a4 */
  70. AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE1) /* lcd_data5.gpmc_a5 */
  71. AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE1) /* lcd_data6.gpmc_a6 */
  72. AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE1) /* lcd_data7.gpmc_a7 */
  73. AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8 */
  74. AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9 */
  75. AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10 */
  76. >;
  77. };
  78. i2c0_pins: i2c0_pins {
  79. pinctrl-single,pins = <
  80. AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_sda.i2c0_sda */
  81. AM33XX_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_scl.i2c0_scl */
  82. >;
  83. };
  84. uart0_pins: uart0_pins {
  85. pinctrl-single,pins = <
  86. AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
  87. AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */
  88. >;
  89. };
  90. uart1_pins: uart1_pins {
  91. pinctrl-single,pins = <
  92. AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */
  93. AM33XX_IOPAD(0x97c, PIN_OUTPUT | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */
  94. AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
  95. AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */
  96. >;
  97. };
  98. uart2_pins: uart2_pins {
  99. pinctrl-single,pins = <
  100. AM33XX_IOPAD(0x8c0, PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_data8.gpio2[14] */
  101. AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7) /* lcd_data9.gpio2[15] */
  102. AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */
  103. AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */
  104. >;
  105. };
  106. uart3_pins: uart3_pins {
  107. pinctrl-single,pins = <
  108. AM33XX_IOPAD(0x8c8, PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data10.uart3_ctsn */
  109. AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE6) /* lcd_data11.uart3_rtsn */
  110. AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE1) /* spi0_cs1.uart3_rxd */
  111. AM33XX_IOPAD(0x964, PIN_OUTPUT | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
  112. >;
  113. };
  114. uart4_pins: uart4_pins {
  115. pinctrl-single,pins = <
  116. AM33XX_IOPAD(0x8d0, PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data12.uart4_ctsn */
  117. AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE6) /* lcd_data13.uart4_rtsn */
  118. AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE1) /* uart0_ctsn.uart4_rxd */
  119. AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE1) /* uart0_rtsn.uart4_txd */
  120. >;
  121. };
  122. uart5_pins: uart5_pins {
  123. pinctrl-single,pins = <
  124. AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE4) /* lcd_data14.uart5_rxd */
  125. AM33XX_IOPAD(0x944, PIN_OUTPUT | MUX_MODE3) /* rmiii1_refclk.uart5_txd */
  126. >;
  127. };
  128. mmc1_pins: mmc1_pins {
  129. pinctrl-single,pins = <
  130. AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
  131. AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
  132. AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
  133. AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
  134. AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
  135. AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
  136. AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
  137. AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */
  138. >;
  139. };
  140. };
  141. &uart0 {
  142. pinctrl-names = "default";
  143. pinctrl-0 = <&uart0_pins>;
  144. status = "okay";
  145. };
  146. &uart1 {
  147. pinctrl-names = "default";
  148. pinctrl-0 = <&uart1_pins>;
  149. status = "okay";
  150. rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
  151. rs485-rts-active-high;
  152. rs485-rx-during-tx;
  153. rs485-rts-delay = <1 1>;
  154. linux,rs485-enabled-at-boot-time;
  155. };
  156. &uart2 {
  157. pinctrl-names = "default";
  158. pinctrl-0 = <&uart2_pins>;
  159. status = "okay";
  160. rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
  161. rs485-rts-active-high;
  162. rs485-rts-delay = <1 1>;
  163. linux,rs485-enabled-at-boot-time;
  164. };
  165. &uart3 {
  166. pinctrl-names = "default";
  167. pinctrl-0 = <&uart3_pins>;
  168. status = "okay";
  169. };
  170. &uart4 {
  171. pinctrl-names = "default";
  172. pinctrl-0 = <&uart4_pins>;
  173. status = "okay";
  174. };
  175. &uart5 {
  176. pinctrl-names = "default";
  177. pinctrl-0 = <&uart5_pins>;
  178. status = "okay";
  179. };
  180. &i2c0 {
  181. status = "okay";
  182. pinctrl-names = "default";
  183. clock-frequency = <400000>;
  184. pinctrl-names = "default";
  185. pinctrl-0 = <&i2c0_pins>;
  186. gpio@20 {
  187. compatible = "microchip,mcp23017";
  188. gpio-controller;
  189. #gpio-cells = <2>;
  190. reg = <0x20>;
  191. };
  192. tps: tps@24 {
  193. reg = <0x24>;
  194. };
  195. eeprom@53 {
  196. compatible = "microchip,24c02";
  197. reg = <0x53>;
  198. pagesize = <8>;
  199. };
  200. rtc@68 {
  201. compatible = "dallas,ds1307";
  202. reg = <0x68>;
  203. };
  204. };
  205. &elm {
  206. status = "okay";
  207. };
  208. &gpmc {
  209. compatible = "ti,am3352-gpmc";
  210. ti,hwmods = "gpmc";
  211. status = "okay";
  212. gpmc,num-waitpins = <2>;
  213. pinctrl-names = "default";
  214. pinctrl-0 = <&gpmc_pins>;
  215. #address-cells = <2>;
  216. #size-cells = <1>;
  217. ranges = <0 0 0x08000000 0x08000000>; /* CS0: NOR 128M */
  218. nor@0,0 {
  219. reg = <0 0x00000000 0x08000000>;
  220. compatible = "cfi-flash";
  221. linux,mtd-name = "spansion,s29gl010p11t";
  222. bank-width = <2>;
  223. gpmc,mux-add-data = <2>;
  224. gpmc,sync-clk-ps = <0>;
  225. gpmc,cs-on-ns = <0>;
  226. gpmc,cs-rd-off-ns = <160>;
  227. gpmc,cs-wr-off-ns = <160>;
  228. gpmc,adv-on-ns = <10>;
  229. gpmc,adv-rd-off-ns = <30>;
  230. gpmc,adv-wr-off-ns = <30>;
  231. gpmc,oe-on-ns = <40>;
  232. gpmc,oe-off-ns = <160>;
  233. gpmc,we-on-ns = <40>;
  234. gpmc,we-off-ns = <160>;
  235. gpmc,rd-cycle-ns = <160>;
  236. gpmc,wr-cycle-ns = <160>;
  237. gpmc,access-ns = <150>;
  238. gpmc,page-burst-access-ns = <10>;
  239. gpmc,cycle2cycle-samecsen;
  240. gpmc,cycle2cycle-delay-ns = <20>;
  241. gpmc,wr-data-mux-bus-ns = <70>;
  242. gpmc,wr-access-ns = <80>;
  243. #address-cells = <1>;
  244. #size-cells = <1>;
  245. /*
  246. MTD partition table
  247. ===================
  248. +------------+-->0x00000000-> U-Boot start
  249. | |
  250. | |-->0x000BFFFF-> U-Boot end
  251. | |-->0x000C0000-> ENV1 start
  252. | |
  253. | |-->0x000DFFFF-> ENV1 end
  254. | |-->0x000E0000-> ENV2 start
  255. | |
  256. | |-->0x000FFFFF-> ENV2 end
  257. | |-->0x00100000-> Kernel start
  258. | |
  259. | |-->0x004FFFFF-> Kernel end
  260. | |-->0x00500000-> File system start
  261. | |
  262. | |-->0x01FFFFFF-> File system end
  263. | |-->0x02000000-> User data start
  264. | |
  265. | |-->0x03FFFFFF-> User data end
  266. | |-->0x04000000-> Data storage start
  267. | |
  268. +------------+-->0x08000000-> NOR end (Free end)
  269. */
  270. partition@0 {
  271. label = "boot";
  272. reg = <0x00000000 0x000c0000>; /* 768KB */
  273. };
  274. partition@1 {
  275. label = "env1";
  276. reg = <0x000c0000 0x00020000>; /* 128KB */
  277. };
  278. partition@2 {
  279. label = "env2";
  280. reg = <0x000e0000 0x00020000>; /* 128KB */
  281. };
  282. partition@3 {
  283. label = "kernel";
  284. reg = <0x00100000 0x00400000>; /* 4MB */
  285. };
  286. partition@4 {
  287. label = "rootfs";
  288. reg = <0x00500000 0x01b00000>; /* 27MB */
  289. };
  290. partition@5 {
  291. label = "user";
  292. reg = <0x02000000 0x02000000>; /* 32MB */
  293. };
  294. partition@6 {
  295. label = "data";
  296. reg = <0x04000000 0x04000000>; /* 64MB */
  297. };
  298. };
  299. };
  300. &mac {
  301. dual_emac;
  302. status = "okay";
  303. };
  304. &davinci_mdio {
  305. status = "okay";
  306. };
  307. &cpsw_emac0 {
  308. phy_id = <&davinci_mdio>, <0>;
  309. phy-mode = "mii";
  310. dual_emac_res_vlan = <1>;
  311. };
  312. &cpsw_emac1 {
  313. phy_id = <&davinci_mdio>, <1>;
  314. phy-mode = "mii";
  315. dual_emac_res_vlan = <2>;
  316. };
  317. &mmc1 {
  318. status = "okay";
  319. vmmc-supply = <&ldo4_reg>;
  320. pinctrl-names = "default";
  321. pinctrl-0 = <&mmc1_pins>;
  322. bus-width = <4>;
  323. cd-gpios = <&gpio3 8 0>;
  324. wp-gpios = <&gpio3 18 0>;
  325. };
  326. #include "tps65217.dtsi"
  327. &tps {
  328. regulators {
  329. dcdc1_reg: regulator@0 {
  330. /* +1.5V voltage with ±4% tolerance */
  331. regulator-min-microvolt = <1450000>;
  332. regulator-max-microvolt = <1550000>;
  333. regulator-boot-on;
  334. regulator-always-on;
  335. };
  336. dcdc2_reg: regulator@1 {
  337. /* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */
  338. regulator-name = "vdd_mpu";
  339. regulator-min-microvolt = <915000>;
  340. regulator-max-microvolt = <1140000>;
  341. regulator-boot-on;
  342. regulator-always-on;
  343. };
  344. dcdc3_reg: regulator@2 {
  345. /* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */
  346. regulator-name = "vdd_core";
  347. regulator-min-microvolt = <915000>;
  348. regulator-max-microvolt = <1140000>;
  349. regulator-boot-on;
  350. regulator-always-on;
  351. };
  352. ldo1_reg: regulator@3 {
  353. /* +1.8V voltage with ±4% tolerance */
  354. regulator-min-microvolt = <1750000>;
  355. regulator-max-microvolt = <1870000>;
  356. regulator-boot-on;
  357. regulator-always-on;
  358. };
  359. ldo2_reg: regulator@4 {
  360. /* +3.3V voltage with ±4% tolerance */
  361. regulator-min-microvolt = <3175000>;
  362. regulator-max-microvolt = <3430000>;
  363. regulator-boot-on;
  364. regulator-always-on;
  365. };
  366. ldo3_reg: regulator@5 {
  367. /* +1.8V voltage with ±4% tolerance */
  368. regulator-min-microvolt = <1750000>;
  369. regulator-max-microvolt = <1870000>;
  370. regulator-boot-on;
  371. regulator-always-on;
  372. };
  373. ldo4_reg: regulator@6 {
  374. /* +3.3V voltage with ±4% tolerance */
  375. regulator-min-microvolt = <3175000>;
  376. regulator-max-microvolt = <3430000>;
  377. regulator-boot-on;
  378. regulator-always-on;
  379. };
  380. };
  381. };