am335x-baltos.dtsi 11 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /*
  9. * VScom OnRISC
  10. * http://www.vscom.de
  11. */
  12. #include "am33xx.dtsi"
  13. #include <dt-bindings/pwm/pwm.h>
  14. #include <dt-bindings/interrupt-controller/irq.h>
  15. / {
  16. compatible = "vscom,onrisc", "ti,am33xx";
  17. cpus {
  18. cpu@0 {
  19. cpu0-supply = <&vdd1_reg>;
  20. };
  21. };
  22. memory@80000000 {
  23. device_type = "memory";
  24. reg = <0x80000000 0x10000000>; /* 256 MB */
  25. };
  26. vbat: fixedregulator0 {
  27. compatible = "regulator-fixed";
  28. regulator-name = "vbat";
  29. regulator-min-microvolt = <5000000>;
  30. regulator-max-microvolt = <5000000>;
  31. regulator-boot-on;
  32. };
  33. wl12xx_vmmc: fixedregulator2 {
  34. pinctrl-names = "default";
  35. pinctrl-0 = <&wl12xx_gpio>;
  36. compatible = "regulator-fixed";
  37. regulator-name = "vwl1271";
  38. regulator-min-microvolt = <3300000>;
  39. regulator-max-microvolt = <3300000>;
  40. gpio = <&gpio3 8 0>;
  41. startup-delay-us = <70000>;
  42. enable-active-high;
  43. };
  44. };
  45. &am33xx_pinmux {
  46. mmc2_pins: pinmux_mmc2_pins {
  47. pinctrl-single,pins = <
  48. AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */
  49. AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */
  50. AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */
  51. AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */
  52. AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */
  53. AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */
  54. AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */
  55. >;
  56. };
  57. wl12xx_gpio: pinmux_wl12xx_gpio {
  58. pinctrl-single,pins = <
  59. AM33XX_IOPAD(0x9e8, PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
  60. >;
  61. };
  62. tps65910_pins: pinmux_tps65910_pins {
  63. pinctrl-single,pins = <
  64. AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */
  65. >;
  66. };
  67. i2c1_pins: pinmux_i2c1_pins {
  68. pinctrl-single,pins = <
  69. AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */
  70. AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */
  71. >;
  72. };
  73. uart0_pins: pinmux_uart0_pins {
  74. pinctrl-single,pins = <
  75. AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
  76. AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
  77. >;
  78. };
  79. cpsw_default: cpsw_default {
  80. pinctrl-single,pins = <
  81. /* Slave 1 */
  82. AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
  83. AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */
  84. AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
  85. AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
  86. AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
  87. AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
  88. AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
  89. /* Slave 2 */
  90. AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
  91. AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
  92. AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
  93. AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
  94. AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
  95. AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
  96. AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
  97. AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
  98. AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
  99. AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
  100. AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
  101. AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
  102. >;
  103. };
  104. cpsw_sleep: cpsw_sleep {
  105. pinctrl-single,pins = <
  106. /* Slave 1 reset value */
  107. AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  108. AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
  109. AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
  110. AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
  111. AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  112. AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
  113. AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
  114. /* Slave 2 reset value*/
  115. AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
  116. AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
  117. AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
  118. AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  119. AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
  120. AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
  121. AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
  122. AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  123. AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
  124. AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
  125. AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
  126. AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  127. >;
  128. };
  129. davinci_mdio_default: davinci_mdio_default {
  130. pinctrl-single,pins = <
  131. /* MDIO */
  132. AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
  133. AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
  134. >;
  135. };
  136. davinci_mdio_sleep: davinci_mdio_sleep {
  137. pinctrl-single,pins = <
  138. /* MDIO reset value */
  139. AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
  140. AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  141. >;
  142. };
  143. nandflash_pins_s0: nandflash_pins_s0 {
  144. pinctrl-single,pins = <
  145. AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
  146. AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
  147. AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
  148. AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
  149. AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
  150. AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
  151. AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
  152. AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
  153. AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
  154. AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
  155. AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
  156. AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
  157. AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
  158. AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
  159. AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
  160. >;
  161. };
  162. };
  163. &elm {
  164. status = "okay";
  165. };
  166. &gpmc {
  167. pinctrl-names = "default";
  168. pinctrl-0 = <&nandflash_pins_s0>;
  169. ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
  170. status = "okay";
  171. nand@0,0 {
  172. compatible = "ti,omap2-nand";
  173. reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  174. interrupt-parent = <&gpmc>;
  175. interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  176. <1 IRQ_TYPE_NONE>; /* termcount */
  177. rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
  178. nand-bus-width = <8>;
  179. ti,nand-ecc-opt = "bch8";
  180. ti,nand-xfer-type = "polled";
  181. gpmc,device-nand = "true";
  182. gpmc,device-width = <1>;
  183. gpmc,sync-clk-ps = <0>;
  184. gpmc,cs-on-ns = <0>;
  185. gpmc,cs-rd-off-ns = <44>;
  186. gpmc,cs-wr-off-ns = <44>;
  187. gpmc,adv-on-ns = <6>;
  188. gpmc,adv-rd-off-ns = <34>;
  189. gpmc,adv-wr-off-ns = <44>;
  190. gpmc,we-on-ns = <0>;
  191. gpmc,we-off-ns = <40>;
  192. gpmc,oe-on-ns = <0>;
  193. gpmc,oe-off-ns = <54>;
  194. gpmc,access-ns = <64>;
  195. gpmc,rd-cycle-ns = <82>;
  196. gpmc,wr-cycle-ns = <82>;
  197. gpmc,bus-turnaround-ns = <0>;
  198. gpmc,cycle2cycle-delay-ns = <0>;
  199. gpmc,clk-activation-ns = <0>;
  200. gpmc,wr-access-ns = <40>;
  201. gpmc,wr-data-mux-bus-ns = <0>;
  202. #address-cells = <1>;
  203. #size-cells = <1>;
  204. ti,elm-id = <&elm>;
  205. };
  206. };
  207. &uart0 {
  208. pinctrl-names = "default";
  209. pinctrl-0 = <&uart0_pins>;
  210. status = "okay";
  211. };
  212. &i2c1 {
  213. pinctrl-names = "default";
  214. pinctrl-0 = <&i2c1_pins>;
  215. status = "okay";
  216. clock-frequency = <400000>;
  217. tps: tps@2d {
  218. reg = <0x2d>;
  219. gpio-controller;
  220. #gpio-cells = <2>;
  221. interrupt-parent = <&gpio1>;
  222. interrupts = <28 GPIO_ACTIVE_LOW>;
  223. pinctrl-names = "default";
  224. pinctrl-0 = <&tps65910_pins>;
  225. };
  226. at24@50 {
  227. compatible = "at24,24c02";
  228. pagesize = <8>;
  229. reg = <0x50>;
  230. };
  231. };
  232. &usb {
  233. status = "okay";
  234. };
  235. &usb_ctrl_mod {
  236. status = "okay";
  237. };
  238. &cppi41dma {
  239. status = "okay";
  240. };
  241. #include "tps65910.dtsi"
  242. &tps {
  243. vcc1-supply = <&vbat>;
  244. vcc2-supply = <&vbat>;
  245. vcc3-supply = <&vbat>;
  246. vcc4-supply = <&vbat>;
  247. vcc5-supply = <&vbat>;
  248. vcc6-supply = <&vbat>;
  249. vcc7-supply = <&vbat>;
  250. vccio-supply = <&vbat>;
  251. ti,en-ck32k-xtal = <1>;
  252. regulators {
  253. vrtc_reg: regulator@0 {
  254. regulator-always-on;
  255. };
  256. vio_reg: regulator@1 {
  257. regulator-always-on;
  258. };
  259. vdd1_reg: regulator@2 {
  260. /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
  261. regulator-name = "vdd_mpu";
  262. regulator-min-microvolt = <912500>;
  263. regulator-max-microvolt = <1312500>;
  264. regulator-boot-on;
  265. regulator-always-on;
  266. };
  267. vdd2_reg: regulator@3 {
  268. /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
  269. regulator-name = "vdd_core";
  270. regulator-min-microvolt = <912500>;
  271. regulator-max-microvolt = <1150000>;
  272. regulator-boot-on;
  273. regulator-always-on;
  274. };
  275. vdd3_reg: regulator@4 {
  276. regulator-always-on;
  277. };
  278. vdig1_reg: regulator@5 {
  279. regulator-always-on;
  280. };
  281. vdig2_reg: regulator@6 {
  282. regulator-always-on;
  283. };
  284. vpll_reg: regulator@7 {
  285. regulator-always-on;
  286. };
  287. vdac_reg: regulator@8 {
  288. regulator-always-on;
  289. };
  290. vaux1_reg: regulator@9 {
  291. regulator-always-on;
  292. };
  293. vaux2_reg: regulator@10 {
  294. regulator-always-on;
  295. };
  296. vaux33_reg: regulator@11 {
  297. regulator-always-on;
  298. };
  299. vmmc_reg: regulator@12 {
  300. regulator-min-microvolt = <1800000>;
  301. regulator-max-microvolt = <3300000>;
  302. regulator-always-on;
  303. };
  304. };
  305. };
  306. &mac {
  307. pinctrl-names = "default", "sleep";
  308. pinctrl-0 = <&cpsw_default>;
  309. pinctrl-1 = <&cpsw_sleep>;
  310. dual_emac = <1>;
  311. status = "okay";
  312. };
  313. &davinci_mdio {
  314. pinctrl-names = "default", "sleep";
  315. pinctrl-0 = <&davinci_mdio_default>;
  316. pinctrl-1 = <&davinci_mdio_sleep>;
  317. status = "okay";
  318. };
  319. &mmc1 {
  320. vmmc-supply = <&vmmc_reg>;
  321. status = "okay";
  322. };
  323. &mmc2 {
  324. status = "okay";
  325. vmmc-supply = <&wl12xx_vmmc>;
  326. ti,non-removable;
  327. bus-width = <4>;
  328. cap-power-off-card;
  329. pinctrl-names = "default";
  330. pinctrl-0 = <&mmc2_pins>;
  331. #address-cells = <1>;
  332. #size-cells = <0>;
  333. wlcore: wlcore@2 {
  334. compatible = "ti,wl1835";
  335. reg = <2>;
  336. interrupt-parent = <&gpio3>;
  337. interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
  338. };
  339. };
  340. &sham {
  341. status = "okay";
  342. };
  343. &aes {
  344. status = "okay";
  345. };
  346. &gpio0 {
  347. ti,no-reset-on-init;
  348. };